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authorHoria Geanta <horia.geanta@freescale.com>2014-07-21 16:03:21 +0300
committerHerbert Xu <herbert@gondor.apana.org.au>2014-07-23 21:31:37 +0800
commit8f1da7b945b65513fb02b75ce25040c67ce32726 (patch)
tree73f0b4286ad7335238c9cb4b34f4bcdd887b10d7 /drivers/crypto
parent71d932d99d7e6c644172e1d686bb41d667d8fa37 (diff)
crypto: caam - fix DECO RSR polling
RSR (Request Source Register) is not used when virtualization is disabled, thus don't poll for Valid bit. Besides this, if used, timeout has to be reinitialized. Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'drivers/crypto')
-rw-r--r--drivers/crypto/caam/ctrl.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index cedb56500b61..3cade79ea41e 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -89,12 +89,15 @@ static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
/* Set the bit to request direct access to DECO0 */
topregs = (struct caam_full __iomem *)ctrlpriv->ctrl;
- if (ctrlpriv->virt_en == 1)
+ if (ctrlpriv->virt_en == 1) {
setbits32(&topregs->ctrl.deco_rsr, DECORSR_JR0);
- while (!(rd_reg32(&topregs->ctrl.deco_rsr) & DECORSR_VALID) &&
- --timeout)
- cpu_relax();
+ while (!(rd_reg32(&topregs->ctrl.deco_rsr) & DECORSR_VALID) &&
+ --timeout)
+ cpu_relax();
+
+ timeout = 100000;
+ }
setbits32(&topregs->ctrl.deco_rq, DECORR_RQD0ENABLE);