drm/amdgpu: rename amdgpu_ip_funcs to amd_ip_funcs (v2)

The structure is renamed and moved to amd_shared.h to make
the component independent.  This makes it easier to add
new components in the future.

v2: fix include path

Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: yanyang1 <young.yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 35 insertions, 19 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index f200df3cf97a..303d961d57bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -169,18 +169,21 @@ static int vce_v2_0_start(struct amdgpu_device *adev)
 	return 0;
 }
 
-static int vce_v2_0_early_init(struct amdgpu_device *adev)
+static int vce_v2_0_early_init(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
 	vce_v2_0_set_ring_funcs(adev);
 	vce_v2_0_set_irq_funcs(adev);
 
 	return 0;
 }
 
-static int vce_v2_0_sw_init(struct amdgpu_device *adev)
+static int vce_v2_0_sw_init(void *handle)
 {
 	struct amdgpu_ring *ring;
 	int r;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	/* VCE */
 	r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
@@ -213,9 +216,10 @@ static int vce_v2_0_sw_init(struct amdgpu_device *adev)
 	return r;
 }
 
-static int vce_v2_0_sw_fini(struct amdgpu_device *adev)
+static int vce_v2_0_sw_fini(void *handle)
 {
 	int r;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	r = amdgpu_vce_suspend(adev);
 	if (r)
@@ -228,10 +232,11 @@ static int vce_v2_0_sw_fini(struct amdgpu_device *adev)
 	return r;
 }
 
-static int vce_v2_0_hw_init(struct amdgpu_device *adev)
+static int vce_v2_0_hw_init(void *handle)
 {
 	struct amdgpu_ring *ring;
 	int r;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	r = vce_v2_0_start(adev);
 	if (r)
@@ -258,15 +263,15 @@ static int vce_v2_0_hw_init(struct amdgpu_device *adev)
 	return 0;
 }
 
-static int vce_v2_0_hw_fini(struct amdgpu_device *adev)
+static int vce_v2_0_hw_fini(void *handle)
 {
-	// TODO
 	return 0;
 }
 
-static int vce_v2_0_suspend(struct amdgpu_device *adev)
+static int vce_v2_0_suspend(void *handle)
 {
 	int r;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	r = vce_v2_0_hw_fini(adev);
 	if (r)
@@ -279,9 +284,10 @@ static int vce_v2_0_suspend(struct amdgpu_device *adev)
 	return r;
 }
 
-static int vce_v2_0_resume(struct amdgpu_device *adev)
+static int vce_v2_0_resume(void *handle)
 {
 	int r;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	r = amdgpu_vce_resume(adev);
 	if (r)
@@ -442,14 +448,17 @@ static void vce_v2_0_mc_resume(struct amdgpu_device *adev)
 	vce_v2_0_init_cg(adev);
 }
 
-static bool vce_v2_0_is_idle(struct amdgpu_device *adev)
+static bool vce_v2_0_is_idle(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
 	return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK);
 }
 
-static int vce_v2_0_wait_for_idle(struct amdgpu_device *adev)
+static int vce_v2_0_wait_for_idle(void *handle)
 {
 	unsigned i;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	for (i = 0; i < adev->usec_timeout; i++) {
 		if (!(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK))
@@ -458,8 +467,10 @@ static int vce_v2_0_wait_for_idle(struct amdgpu_device *adev)
 	return -ETIMEDOUT;
 }
 
-static int vce_v2_0_soft_reset(struct amdgpu_device *adev)
+static int vce_v2_0_soft_reset(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
 	WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK,
 			~SRBM_SOFT_RESET__SOFT_RESET_VCE_MASK);
 	mdelay(5);
@@ -467,8 +478,10 @@ static int vce_v2_0_soft_reset(struct amdgpu_device *adev)
 	return vce_v2_0_start(adev);
 }
 
-static void vce_v2_0_print_status(struct amdgpu_device *adev)
+static void vce_v2_0_print_status(void *handle)
 {
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
 	dev_info(adev->dev, "VCE 2.0 registers\n");
 	dev_info(adev->dev, "  VCE_STATUS=0x%08X\n",
 		 RREG32(mmVCE_STATUS));
@@ -569,12 +582,13 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
 	return 0;
 }
 
-static int vce_v2_0_set_clockgating_state(struct amdgpu_device *adev,
-					  enum amdgpu_clockgating_state state)
+static int vce_v2_0_set_clockgating_state(void *handle,
+					  enum amd_clockgating_state state)
 {
 	bool gate = false;
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	if (state == AMDGPU_CG_STATE_GATE)
+	if (state == AMD_CG_STATE_GATE)
 		gate = true;
 
 	vce_v2_0_enable_mgcg(adev, gate);
@@ -582,8 +596,8 @@ static int vce_v2_0_set_clockgating_state(struct amdgpu_device *adev,
 	return 0;
 }
 
-static int vce_v2_0_set_powergating_state(struct amdgpu_device *adev,
-					  enum amdgpu_powergating_state state)
+static int vce_v2_0_set_powergating_state(void *handle,
+					  enum amd_powergating_state state)
 {
 	/* This doesn't actually powergate the VCE block.
 	 * That's done in the dpm code via the SMC.  This
@@ -592,14 +606,16 @@ static int vce_v2_0_set_powergating_state(struct amdgpu_device *adev,
 	 * revisit this when there is a cleaner line between
 	 * the smc and the hw blocks
 	 */
-	if (state == AMDGPU_PG_STATE_GATE)
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+	if (state == AMD_PG_STATE_GATE)
 		/* XXX do we need a vce_v2_0_stop()? */
 		return 0;
 	else
 		return vce_v2_0_start(adev);
 }
 
-const struct amdgpu_ip_funcs vce_v2_0_ip_funcs = {
+const struct amd_ip_funcs vce_v2_0_ip_funcs = {
 	.early_init = vce_v2_0_early_init,
 	.late_init = NULL,
 	.sw_init = vce_v2_0_sw_init,