diff options
| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-06-29 13:34:36 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-06-29 13:47:29 -0700 |
| commit | 1c70c0cebd1295a42fec75045b8a6b4419cedef3 (patch) | |
| tree | 4d647dcde647e0852736aa356ca4f4fc13a0085a /drivers/gpu/drm/i915/intel_display.c | |
| parent | 8eb2c0ee67f4853c0e433394f65ef8143a748c80 (diff) | |
drm/i915: enable ring freq scaling, RC6 and graphics turbo on Ivy Bridge v3
They use the same register interfaces, so we can simply enable the
existing code on IVB.
v2:
- resolve conflict with ring freq scaling, we can enable it too
v3:
- resolve conflict again, this time on drm-intel-next
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 804ac4d6cb48..823b8d99d9e6 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -7970,7 +7970,7 @@ void intel_modeset_init(struct drm_device *dev) intel_init_emon(dev); } - if (IS_GEN6(dev)) { + if (IS_GEN6(dev) || IS_GEN7(dev)) { gen6_enable_rps(dev_priv); gen6_update_ring_freq(dev_priv); } @@ -8014,7 +8014,7 @@ void intel_modeset_cleanup(struct drm_device *dev) if (IS_IRONLAKE_M(dev)) ironlake_disable_drps(dev); - if (IS_GEN6(dev)) + if (IS_GEN6(dev) || IS_GEN7(dev)) gen6_disable_rps(dev); if (IS_IRONLAKE_M(dev)) |