diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2010-12-15 11:01:56 -0500 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2010-12-16 10:08:26 +1000 |
| commit | 6f2f48a9a061a94d059f89c69472f467839cc616 (patch) | |
| tree | 980b2ea58eb2fe24bd52125da8d512c58dd54b79 /drivers/gpu/drm/radeon/evergreend.h | |
| parent | a1a8213392b29c2b427567b86e2ccfe88ded58cc (diff) | |
drm/radeon/kms/evergreen: flush hdp cache when flushing gart tlb
Make sure vram changes hit memory. This mirrors the
6xx/7xx behavior.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreend.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreend.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 113c70cc8b39..a73b53c44359 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h @@ -174,6 +174,7 @@ #define HDP_NONSURFACE_BASE 0x2C04 #define HDP_NONSURFACE_INFO 0x2C08 #define HDP_NONSURFACE_SIZE 0x2C0C +#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 #define HDP_TILING_CONFIG 0x2F3C |