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authorBhuvanchandra DV <bhuvanchandra.dv@toradex.com>2015-12-09 11:10:58 +0530
committerMarcel Ziswiler <marcel.ziswiler@toradex.com>2015-12-15 14:50:51 +0100
commit1dcb97e485420a25461cc44d43f987c8bbf50e7a (patch)
treeefda13106831653e3b8f425d14807a8cfe507e70 /drivers/gpu/drm/radeon/radeon_state.c
parent5f3e5fc6003cb0767ce5cc3bc3526344d037db39 (diff)
spi-fsl-dspi: Fix CTAR Register access
DSPI instances in Vybrid have a different amount of chip selects and CTARs (Clock and transfer Attributes Register). In case of DSPI1 we only have 2 CTAR registers and 4 CS. In present driver implementation CTAR offset is derived from CS instance which will lead to out of bound access if chip select instance is greater than CTAR register instance, hence use single CTAR0 register for all CS instances. Since we write the CTAR register anyway before each access, there is no value in using the additional CTAR registers. Also one should not program a value in CTAS for a CTAR register that is not present, hence configure CTAS to use CTAR0. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_state.c')
0 files changed, 0 insertions, 0 deletions