diff options
| author | Liu Ying <victor.liu@nxp.com> | 2018-07-20 15:24:20 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:41:33 +0300 |
| commit | 4b710fe10f0f6c6a41b1e15b13b04bb355997e5c (patch) | |
| tree | d68d48e4afb14ecf2968f8e80a0632e2c70cead0 /drivers/gpu/imx/dpu | |
| parent | 03e08b3f29b9d7a6d7bace93977e2216b77858d6 (diff) | |
MLK-18990 gpu: imx: dpu: framegen: Don't set clk_disp rate for TMDS encoder
When TMDS encoder is used, the encoder would provide framegen display clock
directly via clk_bypass. So, we don't have to set clk_disp rate. This
should work with or without pixel combiner(pixel combiner would combine
two framegens' output to drive high pixel rate displays via TMDS encoder
only currently).
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'drivers/gpu/imx/dpu')
| -rw-r--r-- | drivers/gpu/imx/dpu/dpu-framegen.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/imx/dpu/dpu-framegen.c b/drivers/gpu/imx/dpu/dpu-framegen.c index bb75bf8135b2..fc2db992554e 100644 --- a/drivers/gpu/imx/dpu/dpu-framegen.c +++ b/drivers/gpu/imx/dpu/dpu-framegen.c @@ -292,9 +292,6 @@ framegen_cfg_videomode(struct dpu_framegen *fg, struct drm_display_mode *m, if (devtype->has_disp_sel_clk && encoder_type_has_tmds) { clk_set_parent(fg->clk_disp_sel, fg->clk_bypass); - clk_get_rate(fg->clk_disp); - clk_set_rate(fg->clk_disp, disp_clock_rate); - fg->use_bypass_clk = true; } else { /* find an even divisor for PLL */ |