diff options
| author | Liu Ying <victor.liu@nxp.com> | 2018-10-09 16:53:04 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:34:27 +0800 |
| commit | 14cb66b5e92c2f5c274ec6d8e3faf21dbe6d73ff (patch) | |
| tree | ee2d4eb1373ccc357ac5bdac122937dfc46b1b12 /drivers/gpu/imx | |
| parent | 1201a0e8194da559703d64a26aa346a8de387baa (diff) | |
MLK-19849 drm/imx: dpu: crtc: Use pixel clock from stream0 when pc is used
According to pixel combiner spec, there is a clock mux before
the display clock input of stream1 to choose the clock from
disp1 clock(only for stream1) or disp0 clock(usually for stream0).
So, we should enable disp0 clock when pixel combiner is used
instead of enabling the display clock of master stream.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'drivers/gpu/imx')
| -rw-r--r-- | drivers/gpu/imx/dpu/dpu-framegen.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/imx/dpu/dpu-framegen.c b/drivers/gpu/imx/dpu/dpu-framegen.c index e39d5d8cf839..55a956e75d8d 100644 --- a/drivers/gpu/imx/dpu/dpu-framegen.c +++ b/drivers/gpu/imx/dpu/dpu-framegen.c @@ -500,7 +500,7 @@ void framegen_wait_done(struct dpu_framegen *fg, struct drm_display_mode *m) /* fall back to display mode's clock */ dotclock = m->crtc_clock; - if (!(fg->side_by_side && framegen_is_slave(fg))) + if (!(fg->side_by_side && fg->id == 1)) dev_warn(fg->dpu->dev, "pixel clock for FrameGen%d is zero\n", fg->id); } |