diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2018-01-24 15:03:41 +0100 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2018-01-24 15:03:41 +0100 |
| commit | 0710597796a48009846e1aa72644c27e846296a9 (patch) | |
| tree | fbeb9a6ed9d1248fa022a549bcd50a7750de8dbe /drivers/i2c | |
| parent | 953c6e30c9701fda69ef08e2476c541dc4fb1453 (diff) | |
| parent | 7bbc6ca4887794cc44b41412a35bdfbe0cbd1c50 (diff) | |
Merge tag 'v4.9.76' into 4.9-1.0.x-imx-stable-merge
This is the 4.9.76 stable release
Resolved conflicts
drivers/clk/imx/clk-imx6q.c
drivers/net/ethernet/freescale/fec_main.c
Diffstat (limited to 'drivers/i2c')
| -rw-r--r-- | drivers/i2c/busses/i2c-cadence.c | 8 | ||||
| -rw-r--r-- | drivers/i2c/busses/i2c-riic.c | 6 |
2 files changed, 9 insertions, 5 deletions
diff --git a/drivers/i2c/busses/i2c-cadence.c b/drivers/i2c/busses/i2c-cadence.c index 686971263bef..45d6771fac8c 100644 --- a/drivers/i2c/busses/i2c-cadence.c +++ b/drivers/i2c/busses/i2c-cadence.c @@ -962,10 +962,6 @@ static int cdns_i2c_probe(struct platform_device *pdev) goto err_clk_dis; } - ret = i2c_add_adapter(&id->adap); - if (ret < 0) - goto err_clk_dis; - /* * Cadence I2C controller has a bug wherein it generates * invalid read transaction after HW timeout in master receiver mode. @@ -975,6 +971,10 @@ static int cdns_i2c_probe(struct platform_device *pdev) */ cdns_i2c_writereg(CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET); + ret = i2c_add_adapter(&id->adap); + if (ret < 0) + goto err_clk_dis; + dev_info(&pdev->dev, "%u kHz mmio %08lx irq %d\n", id->i2c_clk / 1000, (unsigned long)r_mem->start, id->irq); diff --git a/drivers/i2c/busses/i2c-riic.c b/drivers/i2c/busses/i2c-riic.c index 8f11d347b3ec..c811af4c8d81 100644 --- a/drivers/i2c/busses/i2c-riic.c +++ b/drivers/i2c/busses/i2c-riic.c @@ -218,8 +218,12 @@ static irqreturn_t riic_tend_isr(int irq, void *data) } if (riic->is_last || riic->err) { - riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER); + riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER); writeb(ICCR2_SP, riic->base + RIIC_ICCR2); + } else { + /* Transfer is complete, but do not send STOP */ + riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER); + complete(&riic->msg_done); } return IRQ_HANDLED; |