i2c: tegra: switch to using the NVIDIA RM-based I2C driver

since the RM APIs are used by ODM kits prior to device initialization
(to read EEPROMs and the like), implementing the RM on top of Linux's
I2C API won't happen immediately

Change-Id: I8a97e13a7fda8bafaf74e2251e8bd1b0e32dc058

1 files changed, 163 insertions, 577 deletions

diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index c37430c8b333..c65305b8dca8 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -1,481 +1,58 @@
 /*
  * drivers/i2c/busses/i2c-tegra.c
  *
- * Copyright (C) 2010 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
+ * I2C bus driver for internal I2C controllers in NVIDIA Tegra SoCs
  *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
+ * Copyright (C) 2009-2010 NVIDIA Corporation
  *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
  *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
-#include <linux/kernel.h>
+#define NV_DEBUG 0
+
+#include <linux/err.h>
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
 #include <linux/i2c.h>
-#include <linux/io.h>
 #include <linux/interrupt.h>
+#include <linux/platform_device.h>
 #include <linux/delay.h>
-#include <linux/slab.h>
-
-#include <asm/unaligned.h>
+#include <linux/io.h>
+#include <asm/uaccess.h>
 
+#include <mach/nvrm_linux.h>
 #include <mach/i2c.h>
-#include <mach/pinmux.h>
-#include <mach/clk.h>
-
-#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
-#define BYTES_PER_FIFO_WORD 4
-
-#define I2C_CNFG				0x000
-#define I2C_CNFG_PACKET_MODE_EN			(1<<10)
-#define I2C_CNFG_NEW_MASTER_FSM			(1<<11)
-#define I2C_SL_CNFG				0x020
-#define I2C_SL_CNFG_NEWSL			(1<<2)
-#define I2C_SL_ADDR1				0x02c
-#define I2C_TX_FIFO				0x050
-#define I2C_RX_FIFO				0x054
-#define I2C_PACKET_TRANSFER_STATUS		0x058
-#define I2C_FIFO_CONTROL			0x05c
-#define I2C_FIFO_CONTROL_TX_FLUSH		(1<<1)
-#define I2C_FIFO_CONTROL_RX_FLUSH		(1<<0)
-#define I2C_FIFO_CONTROL_TX_TRIG_SHIFT		5
-#define I2C_FIFO_CONTROL_RX_TRIG_SHIFT		2
-#define I2C_FIFO_STATUS				0x060
-#define I2C_FIFO_STATUS_TX_MASK			0xF0
-#define I2C_FIFO_STATUS_TX_SHIFT		4
-#define I2C_FIFO_STATUS_RX_MASK			0x0F
-#define I2C_FIFO_STATUS_RX_SHIFT		0
-#define I2C_INT_MASK				0x064
-#define I2C_INT_STATUS				0x068
-#define I2C_INT_PACKET_XFER_COMPLETE		(1<<7)
-#define I2C_INT_ALL_PACKETS_XFER_COMPLETE	(1<<6)
-#define I2C_INT_TX_FIFO_OVERFLOW		(1<<5)
-#define I2C_INT_RX_FIFO_UNDERFLOW		(1<<4)
-#define I2C_INT_NO_ACK				(1<<3)
-#define I2C_INT_ARBITRATION_LOST		(1<<2)
-#define I2C_INT_TX_FIFO_DATA_REQ		(1<<1)
-#define I2C_INT_RX_FIFO_DATA_REQ		(1<<0)
-#define I2C_CLK_DIVISOR				0x06c
-
-#define DVC_CTRL_REG1				0x000
-#define DVC_CTRL_REG1_INTR_EN			(1<<10)
-#define DVC_CTRL_REG2				0x004
-#define DVC_CTRL_REG3				0x008
-#define DVC_CTRL_REG3_SW_PROG			(1<<26)
-#define DVC_CTRL_REG3_I2C_DONE_INTR_EN		(1<<30)
-#define DVC_STATUS				0x00c
-#define DVC_STATUS_I2C_DONE_INTR		(1<<30)
-
-#define I2C_ERR_NONE 				0x00
-#define I2C_ERR_NO_ACK				0x01
-#define I2C_ERR_ARBITRATION_LOST		0x02
-
-#define PACKET_HEADER0_HEADER_SIZE_SHIFT	28
-#define PACKET_HEADER0_PACKET_ID_SHIFT		16
-#define PACKET_HEADER0_CONT_ID_SHIFT		12
-#define PACKET_HEADER0_PROTOCOL_I2C		(1<<4)
-
-#define I2C_HEADER_HIGHSPEED_MODE		(1<<22)
-#define I2C_HEADER_CONT_ON_NAK			(1<<21)
-#define I2C_HEADER_SEND_START_BYTE		(1<<20)
-#define I2C_HEADER_READ				(1<<19)
-#define I2C_HEADER_10BIT_ADDR			(1<<18)
-#define I2C_HEADER_IE_ENABLE			(1<<17)
-#define I2C_HEADER_REPEAT_START			(1<<16)
-#define I2C_HEADER_MASTER_ADDR_SHIFT		12
-#define I2C_HEADER_SLAVE_ADDR_SHIFT		1
+#include <nvodm_modules.h>
+#include <nvrm_i2c.h>
 
 struct tegra_i2c_dev;
 
 struct tegra_i2c_bus {
-	struct tegra_i2c_dev *dev;
+	struct tegra_i2c_dev *i2c_dev;
+	unsigned int pinmux;
+	unsigned long rate;
 	struct mutex *bus_lock;
-	const struct tegra_pingroup_config *mux;
-	int mux_len;
 	struct i2c_adapter adapter;
 };
 
 struct tegra_i2c_dev {
 	struct device *dev;
-	struct clk *clk;
-	struct clk *i2c_clk;
-	struct resource *iomem;
-	void __iomem *base;
-	int cont_id;
-	int irq;
-	int is_dvc;
-	struct completion msg_complete;
-	int msg_err;
-	u8 *msg_buf;
-	size_t msg_buf_remaining;
-	int msg_read;
-	int msg_transfer_complete;
+	NvRmI2cHandle rm_i2c;
 	int bus_count;
 	struct tegra_i2c_bus busses[1];
 };
 
-static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
-{
-	writel(val, i2c_dev->base + reg);
-}
-
-static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
-{
-	return readl(i2c_dev->base + reg);
-}
-
-/* i2c_writel and i2c_readl will offset the register if necessary to talk
- * to the I2C block inside the DVC block
- */
-static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned long reg)
-{
-	if (i2c_dev->is_dvc)
-		reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
-	writel(val, i2c_dev->base + reg);
-}
-
-static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned long reg)
-{
-	if (i2c_dev->is_dvc)
-		reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
-	return readl(i2c_dev->base + reg);
-}
-
-static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
-{
-	u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
-	int_mask &= ~mask;
-	i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
-}
-
-static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
-{
-	u32 int_mask = i2c_readl(i2c_dev, I2C_INT_MASK);
-	int_mask |= mask;
-	i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
-}
-
-static void tegra_i2c_set_clk(struct tegra_i2c_dev *i2c_dev, unsigned int freq)
-{
-	u32 val;
-	unsigned long input_freq = clk_get_rate(i2c_dev->i2c_clk);
-	val = input_freq / 12 / freq - 1;
-	dev_dbg(i2c_dev->dev, "clock %lu to %u: %x\n", input_freq, freq, val);
-	dev_dbg(i2c_dev->dev, "clock was %x\n", i2c_readl(i2c_dev, I2C_CLK_DIVISOR));
-	i2c_writel(i2c_dev, val, I2C_CLK_DIVISOR);
-	dev_dbg(i2c_dev->dev, "clock is %x\n", i2c_readl(i2c_dev, I2C_CLK_DIVISOR));
-}
-
-static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
-{
-	unsigned long timeout = jiffies + HZ;
-	u32 val = i2c_readl(i2c_dev, I2C_FIFO_CONTROL);
-	val |= I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH;
-	i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
-
-	while (i2c_readl(i2c_dev, I2C_FIFO_CONTROL) &
-		(I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH)) {
-		if (time_after(jiffies, timeout)) {
-			dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n");
-			return -ETIMEDOUT;
-		}
-		msleep(1);
-	}
-	return 0;
-}
-
-static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
-{
-	u32 val;
-	int rx_fifo_avail;
-	int word;
-	u8 *buf = i2c_dev->msg_buf;
-	size_t buf_remaining = i2c_dev->msg_buf_remaining;
-	int words_to_transfer;
-
-	val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
-	rx_fifo_avail = (val & I2C_FIFO_STATUS_RX_MASK) >>
-		I2C_FIFO_STATUS_RX_SHIFT;
-
-	words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
-	if (words_to_transfer > rx_fifo_avail)
-		words_to_transfer = rx_fifo_avail;
-
-	for (word=0; word < words_to_transfer; word++) {
-		val = i2c_readl(i2c_dev, I2C_RX_FIFO);
-		put_unaligned_le32(val, buf);
-		buf += BYTES_PER_FIFO_WORD;
-		buf_remaining -= BYTES_PER_FIFO_WORD;
-		rx_fifo_avail--;
-	}
-
-	if (rx_fifo_avail > 0 && buf_remaining > 0) {
-		int bytes_to_transfer = buf_remaining;
-		int byte;
-		BUG_ON(bytes_to_transfer > 3);
-		val = i2c_readl(i2c_dev, I2C_RX_FIFO);
-		for (byte = 0; byte < bytes_to_transfer; byte++) {
-			*buf++ = val & 0xFF;
-			val >>= 8;
-		}
-		buf_remaining -= bytes_to_transfer;
-		rx_fifo_avail--;
-	}
-	BUG_ON(rx_fifo_avail > 0 && buf_remaining > 0);
-	i2c_dev->msg_buf_remaining = buf_remaining;
-	i2c_dev->msg_buf = buf;
-	return 0;
-}
-
-static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
-{
-	u32 val;
-	int tx_fifo_avail;
-	int word;
-	u8 *buf = i2c_dev->msg_buf;
-	size_t buf_remaining = i2c_dev->msg_buf_remaining;
-	int words_to_transfer;
-
-	val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
-	tx_fifo_avail = (val & I2C_FIFO_STATUS_TX_MASK) >>
-		I2C_FIFO_STATUS_TX_SHIFT;
-
-	words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
-	if (words_to_transfer > tx_fifo_avail)
-		words_to_transfer = tx_fifo_avail;
-	dev_dbg(i2c_dev->dev, "fill_tx_fifo: tx_fifo_avail %d\n", tx_fifo_avail);
-	dev_dbg(i2c_dev->dev, "fill_tx_fifo: words_to_transfer %d\n", words_to_transfer);
-	for (word=0; word < words_to_transfer; word++) {
-		val = get_unaligned_le32(buf);
-		i2c_writel(i2c_dev, val, I2C_TX_FIFO);
-		buf += BYTES_PER_FIFO_WORD;
-		buf_remaining -= BYTES_PER_FIFO_WORD;
-		tx_fifo_avail--;
-	}
-
-	if (tx_fifo_avail > 0 && buf_remaining > 0) {
-		int bytes_to_transfer = buf_remaining;
-		int byte;
-		dev_dbg(i2c_dev->dev, "fill_tx_fifo: bytes_to_transfer %d\n", bytes_to_transfer);
-		BUG_ON(bytes_to_transfer > 3);
-		val = 0;
-		for (byte = 0; byte < bytes_to_transfer; byte++) {
-			val |= (*buf++) << (byte * 8);
-		}
-		i2c_writel(i2c_dev, val, I2C_TX_FIFO);
-		buf_remaining -= bytes_to_transfer;
-		tx_fifo_avail--;
-	}
-	BUG_ON(tx_fifo_avail > 0 && buf_remaining > 0);
-	i2c_dev->msg_buf_remaining = buf_remaining;
-	i2c_dev->msg_buf = buf;
-	return 0;
-}
-
-/* One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
- * block.  This block is identical to the rest of the I2C blocks, except that
- * it only supports master mode, it has registers moved around, and it needs
- * some extra init to get it into I2C mode.  The register moves are handled
- * by i2c_readl and i2c_writel
- */
-static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
-{
-	u32 val = 0;
-	dev_dbg(i2c_dev->dev, "dvc init\n");
-	val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
-	val |= DVC_CTRL_REG3_SW_PROG;
-	val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
-	dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
-
-	val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
-	val |= DVC_CTRL_REG1_INTR_EN;
-	dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
-}
-
-static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
-{
-	u32 val;
-	int err = 0;
-
-	tegra_periph_reset_assert(i2c_dev->clk);
-	msleep(1);
-	tegra_periph_reset_deassert(i2c_dev->clk);
-	msleep(1);
-
-	clk_enable(i2c_dev->clk);
-
-	dev_dbg(i2c_dev->dev, "init\n");
-	if (i2c_dev->is_dvc)
-		tegra_dvc_init(i2c_dev);
-
-	val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN;
-	i2c_writel(i2c_dev, val, I2C_CNFG);
-	i2c_writel(i2c_dev, 0, I2C_INT_MASK);
-	tegra_i2c_set_clk(i2c_dev, 100000);
-
-	val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
-		0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
-	i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
-
-	if (tegra_i2c_flush_fifos(i2c_dev))
-		err = -ETIMEDOUT;
-
-	clk_disable(i2c_dev->clk);
-	return 0;
-}
-
-static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
-{
-	u32 status;
-	const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
-	struct tegra_i2c_dev *i2c_dev = dev_id;
-
-	status = i2c_readl(i2c_dev, I2C_INT_STATUS);
-
-	if (status == 0) {
-		printk("irq status 0 %08x\n", i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
-		//BUG();
-		return IRQ_HANDLED;
-	}
-
-	dev_dbg(i2c_dev->dev, "irq status %02x\n", status);
-	dev_dbg(i2c_dev->dev, "irq mask %02x\n", i2c_readl(i2c_dev, I2C_INT_MASK));
-	dev_dbg(i2c_dev->dev, "transfer: %08x fifo %02x\n", i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), i2c_readl(i2c_dev, I2C_FIFO_STATUS));
-	dev_dbg(i2c_dev->dev, "remaining: %d\n", i2c_dev->msg_buf_remaining);
-	dev_dbg(i2c_dev->dev, "xfer complete: %d \n", i2c_dev->msg_transfer_complete);
-	if (i2c_dev->is_dvc)
-		dev_dbg(i2c_dev->dev, "dvc status: %08x\n", dvc_readl(i2c_dev, DVC_STATUS));
-	if (unlikely(status & status_err)) {
-		if (status & I2C_INT_NO_ACK)
-			i2c_dev->msg_err |= I2C_ERR_NO_ACK;
-		if (status & I2C_INT_ARBITRATION_LOST)
-			i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
-		complete(&i2c_dev->msg_complete);
-		goto err;
-	}
-
-	if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
-		if (i2c_dev->msg_buf_remaining)
-			tegra_i2c_empty_rx_fifo(i2c_dev);
-		else
-			BUG();
-	}
-
-	if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
-		if (i2c_dev->msg_buf_remaining)
-			tegra_i2c_fill_tx_fifo(i2c_dev);
-		else
-			tegra_i2c_mask_irq(i2c_dev, I2C_INT_TX_FIFO_DATA_REQ);
-	}
-
-	if (status & I2C_INT_PACKET_XFER_COMPLETE)
-		i2c_dev->msg_transfer_complete = 1;
-
-	if (i2c_dev->msg_transfer_complete && !i2c_dev->msg_buf_remaining)
-		complete(&i2c_dev->msg_complete);
-	i2c_writel(i2c_dev, status, I2C_INT_STATUS);
-	if (i2c_dev->is_dvc)
-		dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
-	return IRQ_HANDLED;
-err:
-	/* An error occured, mask all interrupts */
-	tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
-		I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
-		I2C_INT_RX_FIFO_DATA_REQ);
-	i2c_writel(i2c_dev, status, I2C_INT_STATUS);
-	return IRQ_HANDLED;
-}
-
-static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
-	struct i2c_msg *msg, int stop)
-{
-	u32 packet_header;
-	u32 int_mask;
-	int ret;
-
-	tegra_i2c_flush_fifos(i2c_dev);
-	i2c_writel(i2c_dev, 0xFF, I2C_INT_STATUS);
-
-	dev_dbg(i2c_dev->dev, "%s: addr 0x%04x, len %d, flags 0x%x, stop %d\n",
-		__func__, msg->addr, msg->len, msg->flags, stop);
-	if (msg->len == 0)
-		return -EINVAL;
-
-	i2c_dev->msg_buf = msg->buf;
-	i2c_dev->msg_buf_remaining = msg->len;
-	i2c_dev->msg_err = I2C_ERR_NONE;
-	i2c_dev->msg_transfer_complete = 0;
-	i2c_dev->msg_read = (msg->flags & I2C_M_RD);
-	INIT_COMPLETION(i2c_dev->msg_complete);
-
-	packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
-			PACKET_HEADER0_PROTOCOL_I2C |
-			(i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
-			(1 << PACKET_HEADER0_PACKET_ID_SHIFT);
-	i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
-
-	packet_header = msg->len - 1;
-	i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
-
-	packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
-	packet_header |= I2C_HEADER_IE_ENABLE;
-	if (msg->flags & I2C_M_TEN)
-		packet_header |= I2C_HEADER_10BIT_ADDR;
-	if (msg->flags & I2C_M_IGNORE_NAK)
-		packet_header |= I2C_HEADER_CONT_ON_NAK;
-	if (msg->flags & I2C_M_NOSTART)
-		packet_header |= I2C_HEADER_REPEAT_START;
-	if (msg->flags & I2C_M_RD)
-		packet_header |= I2C_HEADER_READ;
-	i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
-
-	if (!(msg->flags & I2C_M_RD))
-		tegra_i2c_fill_tx_fifo(i2c_dev);
-
-	dev_dbg(i2c_dev->dev, "before transfer: %08x fifo %02x\n", i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), i2c_readl(i2c_dev, I2C_FIFO_STATUS));
-
-	int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
-	if (msg->flags & I2C_M_RD)
-		int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
-	else if (i2c_dev->msg_buf_remaining)
-		int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
-	tegra_i2c_unmask_irq(i2c_dev, int_mask);
-	pr_debug("unmasked irq: %02x\n", i2c_readl(i2c_dev, I2C_INT_MASK));
-
-	ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
-	tegra_i2c_mask_irq(i2c_dev, int_mask);
-
-	dev_dbg(i2c_dev->dev, "after transfer: %08x fifo %02x\n", i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS), i2c_readl(i2c_dev, I2C_FIFO_STATUS));
-	if (ret == 0) {
-		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
-
-		tegra_i2c_init(i2c_dev);
-		return -ETIMEDOUT;
-	}
-
-	pr_debug("transfer complete: %d %d %d\n", ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
-
-	if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
-		return 0;
-
-	tegra_i2c_init(i2c_dev);
-	if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
-		if (msg->flags & I2C_M_IGNORE_NAK)
-			return 0;
-		return -EREMOTEIO;
-	}
-
-	return -EIO;
-}
-
 static int tegra_i2c_lock(struct tegra_i2c_bus *i2c_bus)
 {
 	if (likely(i2c_bus->bus_lock == &i2c_bus->adapter.bus_lock))
@@ -498,45 +75,118 @@ static void tegra_i2c_unlock(struct tegra_i2c_bus *i2c_bus)
 	mutex_unlock(i2c_bus->bus_lock);
 }
 
-static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
+#define kzalloc_stack(num, buff)					\
+	({								\
+		typeof(buff[0]) *bptr = buff;				\
+		if (num > ARRAY_SIZE(buff))				\
+			bptr = kzalloc(sizeof(*bptr)*num, GFP_ATOMIC);	\
+		bptr;							\
+	})
+
+#define kfree_stack(ptr, buff)				\
+	do {						\
+		if (ptr && ptr != buff)			\
+			kfree(ptr);			\
+	} while (0);
+
+static int tegra_i2c_xfer(struct i2c_adapter *adap,
+	struct i2c_msg msgs[], int num)
 {
 	struct tegra_i2c_bus *i2c_bus = i2c_get_adapdata(adap);
-	struct tegra_i2c_dev *i2c_dev = i2c_bus->dev;
-	int ret = 0;
+	struct tegra_i2c_dev *i2c_dev = i2c_bus->i2c_dev;
+	NvRmI2cTransactionInfo onstack_tx[3];
+	NvRmI2cTransactionInfo *rm_tx = NULL;
+	NvU8 onstack_data[32];	
+	NvU8 *data = NULL, *cpy;
+	unsigned int len = 0;
+	int rc = 0;
 	int i;
 
-	if (i2c_bus->mux && i2c_bus->mux_len) {
-		if (i2c_dev->bus_count > 1) {
-			if (tegra_i2c_lock(i2c_bus))
-				return -EAGAIN;
-			tegra_pinmux_config_pinmux_table(i2c_bus->mux,
-				i2c_bus->mux_len, true);
-		}
+	for(i=0; i<num; i++)
+		len += msgs[i].len;
+
+	if (tegra_i2c_lock(i2c_bus))
+		return -EAGAIN;
 
-		tegra_pinmux_config_tristate_table(i2c_bus->mux,
-			i2c_bus->mux_len, TEGRA_TRI_NORMAL);
+	i = 0;
+
+	rm_tx = kzalloc_stack(num, onstack_tx);
+	if (!rm_tx) {
+		dev_err(i2c_dev->dev, "allocate transaction array failed\n");
+		rc = -ENOMEM;
+		goto clean;
 	}
 
-	clk_enable(i2c_dev->clk);
-	for (i = 0; i < num; i++) {
-		int stop = (i == (num - 1)) ? 1  : 0;
-		ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], stop);
-		if (ret)
-			break;
+	if (len) {
+		data = kzalloc_stack(len, onstack_data);
+		if (!data) {
+			dev_err(i2c_dev->dev, "allocate data array failed\n");
+			rc = -ENOMEM;
+			goto clean;
+		}
 	}
-	clk_disable(i2c_dev->clk);
 
-	if (i2c_bus->mux && i2c_bus->mux_len) {
-		tegra_pinmux_config_tristate_table(i2c_bus->mux,
-			i2c_bus->mux_len, TEGRA_TRI_TRISTATE);
+	cpy = data;
 
-		if (i2c_dev->bus_count > 1) {
-			tegra_pinmux_config_pinmux_table(i2c_bus->mux,
-				i2c_bus->mux_len, false);
-			tegra_i2c_unlock(i2c_bus);
+	for (i=0; i<num; i++) {
+		if (msgs[i].flags & I2C_M_NOSTART) {
+			rm_tx[i].Flags |= NVRM_I2C_NOSTOP;
+		}
+		if (msgs[i].flags & I2C_M_IGNORE_NAK) {
+			rm_tx[i].Flags |= NVRM_I2C_NOACK;
+		}
+		if (msgs[i].flags & I2C_M_RD) {
+			rm_tx[i].Flags |= NVRM_I2C_READ;
+		} else {
+			rm_tx[i].Flags |= NVRM_I2C_WRITE;
+			memcpy(cpy, msgs[i].buf, msgs[i].len);
 		}
+		cpy += msgs[i].len;
+		rm_tx[i].NumBytes = msgs[i].len;
+		rm_tx[i].Address = msgs[i].addr << 1;
+		rm_tx[i].Is10BitAddress = !!(msgs[i].flags & I2C_M_TEN);
 	}
 
+	switch (NvRmI2cTransaction(i2c_dev->rm_i2c, i2c_bus->pinmux, 1000,
+				   i2c_bus->rate/1000, data, len, rm_tx, num)) {
+	case NvSuccess:
+		break;
+	case NvError_I2cDeviceNotFound:
+		dev_err(i2c_dev->dev, "no slave found on adapter %d at "
+			"address 0x%x\n", i2c_bus->adapter.nr, msgs[i].addr);
+		rc = -ENXIO;
+		break;
+	case NvError_I2cReadFailed:
+	case NvError_I2cWriteFailed:
+		dev_err(i2c_dev->dev, "read/write failed on adapter %d at "
+			"address 0x%x\n", i2c_bus->adapter.nr, msgs[i].addr);
+		rc = -EIO;
+		break;
+	case NvError_Timeout:
+		dev_err(i2c_dev->dev, "i2c timeout on adapter %d at "
+			"address 0x%x\n", i2c_bus->adapter.nr, msgs[i].addr);
+		rc = -EIO;
+		break;
+	default:
+		dev_err(i2c_dev->dev, "unknown error on adapter %d at "
+			"address 0x%x\n", i2c_bus->adapter.nr, msgs[i].addr);
+		rc = -ENXIO;
+		break;
+	}
+
+	num = i;
+
+	cpy = data;
+	for (i=0; i<num; i++) {
+		if (rm_tx[i].Flags & NVRM_I2C_READ)
+			memcpy(msgs[i].buf, cpy, msgs[i].len);
+		cpy += msgs[i].len;
+	}
+
+clean:
+	kfree_stack(data, onstack_data);
+	kfree_stack(rm_tx, onstack_tx);
+	tegra_i2c_unlock(i2c_bus);
 	return i;
 }
 
@@ -556,105 +206,52 @@ static int tegra_i2c_probe(struct platform_device *pdev)
 {
 	struct tegra_i2c_dev *i2c_dev;
 	struct tegra_i2c_plat_parms *plat = pdev->dev.platform_data;
-	/*struct tegra_i2c_platform_data *pdata = pdev->dev.platform_data;*/
-	struct resource *res;
-	struct resource *iomem;
-	struct clk *clk;
-	struct clk *i2c_clk;
-	void *base;
-	int irq;
+	int ret = 0;
 	int nbus;
+	NvError e;
 	int i = 0;
-	int ret = 0;
+
+	dev_dbg(&pdev->dev, "%s: %p\n", __func__, plat);
 
 	if (!plat) {
 		dev_err(&pdev->dev, "no platform data?\n");
 		return -ENODEV;
 	}
 
-	if (plat->bus_count <= 0 || plat->adapter_nr < 0) {
-		dev_err(&pdev->dev, "invalid platform data?\n");
-		return -ENODEV;
-	}
-
 	WARN_ON(plat->bus_count > TEGRA_I2C_MAX_BUS);
 	nbus = min(TEGRA_I2C_MAX_BUS, plat->bus_count);
+	BUG_ON(!nbus);
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res) {
-		dev_err(&pdev->dev, "no mem resource?\n");
-		return -ENODEV;
-	}
-	iomem = request_mem_region(res->start, resource_size(res), pdev->name);
-	if (!iomem) {
-		dev_err(&pdev->dev, "I2C region already claimed\n");
-		return -EBUSY;
-	}
+	i2c_dev = kzalloc(sizeof(*i2c_dev) +
+			  (nbus-1)*sizeof(struct tegra_i2c_bus), GFP_KERNEL);
 
-	base = ioremap(iomem->start, resource_size(iomem));
-	if (!base) {
-		dev_err(&pdev->dev, "Can't ioremap I2C region\n");
+	if (!i2c_dev) {
+		dev_err(&pdev->dev, "%s: out of memory\n", __func__);
 		return -ENOMEM;
 	}
 
-	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (!res) {
-		dev_err(&pdev->dev, "no irq resource?\n");
-		ret = -ENODEV;
-		goto err_iounmap;
-	}
-	irq = res->start;
-
-	clk = clk_get(&pdev->dev, NULL);
-	if (!clk) {
-		ret = -ENOMEM;
-		goto err_release_region;
-	}
-
-	i2c_clk = clk_get(&pdev->dev, "i2c");
-	if (!i2c_clk) {
-		ret = -ENOMEM;
-		goto err_clk_put;
+	platform_set_drvdata(pdev, i2c_dev);
+	if (plat->is_dvc) {
+		e = NvRmI2cOpen(s_hRmGlobal, NvOdmIoModule_I2c_Pmu,
+				0, &i2c_dev->rm_i2c);
+	} else {
+		e = NvRmI2cOpen(s_hRmGlobal, NvOdmIoModule_I2c,
+				pdev->id, &i2c_dev->rm_i2c);
 	}
-
-	i2c_dev = kzalloc(sizeof(struct tegra_i2c_dev) +
-			  (nbus-1) * sizeof(struct tegra_i2c_bus), GFP_KERNEL);
-	if (!i2c_dev) {
-		ret = -ENOMEM;
-		goto err_i2c_clk_put;
+	if (e != NvSuccess) {
+		dev_err(&pdev->dev, "failed to open RM I2C\n");
+		kfree(i2c_dev);
+		return -ENODEV;
 	}
 
-	i2c_dev->base = base;
-	i2c_dev->clk = clk;
-	i2c_dev->i2c_clk = i2c_clk;
-	i2c_dev->iomem = iomem;
-	i2c_dev->irq = irq;
-	i2c_dev->cont_id = pdev->id;
 	i2c_dev->dev = &pdev->dev;
-	i2c_dev->is_dvc = plat->is_dvc;
-	init_completion(&i2c_dev->msg_complete);
-
-	platform_set_drvdata(pdev, i2c_dev);
-
-	ret = tegra_i2c_init(i2c_dev);
-	if (ret)
-		goto err_free;
-
-	ret = request_irq(i2c_dev->irq, tegra_i2c_isr, IRQF_DISABLED,
-		pdev->name, i2c_dev);
-	if (ret) {
-		dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq);
-		goto err_free;
-	}
-
-	clk_enable(i2c_dev->i2c_clk);
 
 	for (i=0; i<nbus; i++) {
 		struct tegra_i2c_bus *i2c_bus = &i2c_dev->busses[i];
 
-		i2c_bus->dev = i2c_dev;
-		i2c_bus->mux = plat->bus_mux[i];
-		i2c_bus->mux_len = plat->bus_mux_len[i];
+		i2c_bus->i2c_dev = i2c_dev;
+		i2c_bus->pinmux = plat->bus_mux[i];
+		i2c_bus->rate = plat->bus_clk[i];
 		i2c_bus->bus_lock = &i2c_dev->busses[0].adapter.bus_lock;
 
 		i2c_bus->adapter.algo = &tegra_i2c_algo;
@@ -667,55 +264,43 @@ static int tegra_i2c_probe(struct platform_device *pdev)
 		i2c_bus->adapter.nr = plat->adapter_nr + i;
 		ret = i2c_add_numbered_adapter(&i2c_bus->adapter);
 		if (ret) {
-			dev_err(&pdev->dev, "Failed to add I2C adapter\n");
-			goto err_free_irq;
+			dev_err(&pdev->dev, "failed to add adapter %d\n", i);
+			goto err;
 		}
 		i2c_dev->bus_count++;
 	}
 
 	return 0;
-err_free_irq:
+
+err:
 	while (i2c_dev->bus_count--)
 		i2c_del_adapter(&i2c_dev->busses[i2c_dev->bus_count].adapter);
 
-	free_irq(i2c_dev->irq, i2c_dev);
-err_free:
 	kfree(i2c_dev);
-err_i2c_clk_put:
-	clk_put(i2c_clk);
-err_clk_put:
-	clk_put(clk);
-err_release_region:
-	release_mem_region(iomem->start, resource_size(iomem));
-err_iounmap:
-	iounmap(base);
 	return ret;
 }
 
 static int tegra_i2c_remove(struct platform_device *pdev)
 {
 	struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
+
 	while (i2c_dev->bus_count--)
 		i2c_del_adapter(&i2c_dev->busses[i2c_dev->bus_count].adapter);
 
-	free_irq(i2c_dev->irq, i2c_dev);
-	clk_put(i2c_dev->i2c_clk);
-	clk_put(i2c_dev->clk);
-	release_mem_region(i2c_dev->iomem->start, resource_size(i2c_dev->iomem));
-	iounmap(i2c_dev->base);
+	NvRmI2cClose(i2c_dev->rm_i2c);
 	kfree(i2c_dev);
 	return 0;
 }
 
 static int tegra_i2c_suspend(struct platform_device *pdev, pm_message_t state)
 {
-	/* FIXME to be implemented */
+	/* nothing to do; handled by RM */
 	return 0;
 }
 
 static int tegra_i2c_resume(struct platform_device *pdev)
 {
-	/* FIXME to be implemented */
+	/* nothing to do; handled by RM */
 	return 0;
 }
 
@@ -726,19 +311,20 @@ static struct platform_driver tegra_i2c_driver = {
 	.resume  = tegra_i2c_resume,
 	.driver  =
 	{
-		.name  = "tegra-i2c",
+		.name  = "tegra_i2c",
 		.owner = THIS_MODULE,
 	},
 };
 
-static int __init tegra_i2c_init_driver(void)
+/* I2C may be needed to bring up other drivers */
+static int __init tegra_i2c_init(void)
 {
 	return platform_driver_register(&tegra_i2c_driver);
 }
-module_init(tegra_i2c_init_driver);
+module_init(tegra_i2c_init);
 
-static void __exit tegra_i2c_exit_driver(void)
+static void __exit tegra_i2c_exit(void)
 {
 	platform_driver_unregister(&tegra_i2c_driver);
 }
-module_exit(tegra_i2c_exit_driver);
+module_exit(tegra_i2c_exit);