diff options
| author | Joerg Roedel <joerg.roedel@amd.com> | 2011-11-25 11:41:31 +0100 |
|---|---|---|
| committer | Hiroshi DOYU <hdoyu@nvidia.com> | 2012-01-23 11:11:39 +0200 |
| commit | 6ff803185644748146d45b9dbaade53cec7e6f24 (patch) | |
| tree | e42c93353e26d81f53181f050160f98ce4d10cdc /drivers/iommu | |
| parent | e4dd7206a1f364077a3887199766d3886a8ebb67 (diff) | |
iommu/amd: Enable GT mode when supported by IOMMU
This feature needs to be enabled before IOMMUv2 DTEs can be
set up.
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
Diffstat (limited to 'drivers/iommu')
| -rw-r--r-- | drivers/iommu/amd_iommu_init.c | 9 | ||||
| -rw-r--r-- | drivers/iommu/amd_iommu_types.h | 1 |
2 files changed, 10 insertions, 0 deletions
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c index 60716cefa7af..2c25ae306e7c 100644 --- a/drivers/iommu/amd_iommu_init.c +++ b/drivers/iommu/amd_iommu_init.c @@ -623,6 +623,14 @@ static void __init free_ppr_log(struct amd_iommu *iommu) free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); } +static void iommu_enable_gt(struct amd_iommu *iommu) +{ + if (!iommu_feature(iommu, FEATURE_GT)) + return; + + iommu_feature_enable(iommu, CONTROL_GT_EN); +} + /* sets a specific bit in the device table entry. */ static void set_dev_entry_bit(u16 devid, u8 bit) { @@ -1338,6 +1346,7 @@ static void enable_iommus(void) iommu_enable_command_buffer(iommu); iommu_enable_event_buffer(iommu); iommu_enable_ppr_log(iommu); + iommu_enable_gt(iommu); iommu_set_exclusion_range(iommu); iommu_init_msi(iommu); iommu_enable(iommu); diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h index 4dc230904fe9..a6e1dc616afe 100644 --- a/drivers/iommu/amd_iommu_types.h +++ b/drivers/iommu/amd_iommu_types.h @@ -129,6 +129,7 @@ #define CONTROL_PPFLOG_EN 0x0dULL #define CONTROL_PPFINT_EN 0x0eULL #define CONTROL_PPR_EN 0x0fULL +#define CONTROL_GT_EN 0x10ULL /* command specific defines */ #define CMD_COMPL_WAIT 0x01 |