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authorHiroshi Doyu <hdoyu@nvidia.com>2013-10-11 11:19:28 +0300
committerHiroshi Doyu <hdoyu@nvidia.com>2013-10-13 23:17:14 -0700
commitd6d56590c5c36d2f6e172e8e0e26d100be5125a3 (patch)
tree240aa2b9652ea6e6a3fb3c9b2b104a909cd5af73 /drivers/iommu
parent93b7b634092bc5d23af14c880866b3ac2e26f7d4 (diff)
ARM: tegra: Redefine SWGROUP ID
Redefine SWGROUP ID for the future chips with more HWAs. Also modified how to calculate MC_SMMU_<SWGROUP ID>_ASID_0 offset from ID in SMMU in order not to break git bisctability. Change-Id: Ie024985ae3fbbcf555199b951107f84346bb702d Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-on: http://git-master/r/289637 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Diffstat (limited to 'drivers/iommu')
-rw-r--r--drivers/iommu/tegra-smmu.c22
1 files changed, 14 insertions, 8 deletions
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
index a674f6473c17..ab05430ac6f3 100644
--- a/drivers/iommu/tegra-smmu.c
+++ b/drivers/iommu/tegra-smmu.c
@@ -303,15 +303,21 @@ static const u32 smmu_asid_security_ofs[] = {
SMMU_ASID_SECURITY_7,
};
-static size_t tegra_smmu_get_offset_base(int id)
+static size_t tegra_smmu_get_offset(int id)
{
- if (!(id & BIT(5)))
- return SMMU_SWGRP_ASID_BASE;
-
- if (id & BIT(4))
- return 0xa88 - SWGID_DC12 * sizeof(u32);
+ switch (id) {
+ case SWGID_DC14:
+ return 0x490;
+ case SWGID_DC12:
+ return 0xa88;
+ case SWGID_AFI...SWGID_ISP:
+ case SWGID_MPE...SWGID_PPCS1:
+ return (id - SWGID_AFI) * sizeof(u32) + SMMU_AFI_ASID;
+ case SWGID_SDMMC1A...63:
+ return (id - SWGID_SDMMC1A) * sizeof(u32) + 0xa94;
+ };
- return 0x490 - SWGID_DC14 * sizeof(u32);
+ BUG();
}
/*
@@ -480,7 +486,7 @@ static int __smmu_client_set_hwgrp(struct smmu_client *c, u64 map, int on)
if (i == SWGID_AFI)
continue;
- offs = i * sizeof(u32) + tegra_smmu_get_offset_base(i);
+ offs = tegra_smmu_get_offset(i);
val = smmu_read(smmu, offs);
val &= ~3; /* always overwrite ASID */