diff options
| author | Sri Deevi <srinivasa.deevi@conexant.com> | 2009-03-10 21:16:26 -0300 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2009-04-06 21:44:04 -0300 |
| commit | 6e4f574ba43511ac1cb860027275e08529c5a28f (patch) | |
| tree | 6e710a1f93e12c001b2d8634d1a344690586a6ac /drivers/media/video/cx231xx/cx231xx-conf-reg.h | |
| parent | b9255176453086b2531c5559350bd5c92b771cc5 (diff) | |
V4L/DVB (10958): cx231xx: some additional CodingStyle and minor fixes
changed the pcb-config.c/h to pcb-cfg.c/h for short names.
Signed-off-by: Srinivasa Deevi <srinivasa.deevi@conexant.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/cx231xx/cx231xx-conf-reg.h')
| -rw-r--r-- | drivers/media/video/cx231xx/cx231xx-conf-reg.h | 299 |
1 files changed, 153 insertions, 146 deletions
diff --git a/drivers/media/video/cx231xx/cx231xx-conf-reg.h b/drivers/media/video/cx231xx/cx231xx-conf-reg.h index a65f99ba109b..a6f398a175c5 100644 --- a/drivers/media/video/cx231xx/cx231xx-conf-reg.h +++ b/drivers/media/video/cx231xx/cx231xx-conf-reg.h @@ -42,30 +42,30 @@ #define PWR_CTL_EN 0x74 /* Polaris Endpoints capture mask for register EP_MODE_SET */ -#define ENABLE_EP1 0x01 /* Bit[0]=1 */ -#define ENABLE_EP2 0x02 /* Bit[1]=1 */ -#define ENABLE_EP3 0x04 /* Bit[2]=1 */ -#define ENABLE_EP4 0x08 /* Bit[3]=1 */ -#define ENABLE_EP5 0x10 /* Bit[4]=1 */ -#define ENABLE_EP6 0x20 /* Bit[5]=1 */ +#define ENABLE_EP1 0x01 /* Bit[0]=1 */ +#define ENABLE_EP2 0x02 /* Bit[1]=1 */ +#define ENABLE_EP3 0x04 /* Bit[2]=1 */ +#define ENABLE_EP4 0x08 /* Bit[3]=1 */ +#define ENABLE_EP5 0x10 /* Bit[4]=1 */ +#define ENABLE_EP6 0x20 /* Bit[5]=1 */ /* Bit definition for register PWR_CTL_EN */ #define PWR_MODE_MASK 0x17f -#define PWR_AV_EN 0x08 /* bit3 */ -#define PWR_ISO_EN 0x40 /* bit6 */ -#define PWR_AV_MODE 0x30 /* bit4,5 */ -#define PWR_TUNER_EN 0x04 /* bit2 */ -#define PWR_DEMOD_EN 0x02 /* bit1 */ -#define I2C_DEMOD_EN 0x01 /* bit0 */ -#define PWR_RESETOUT_EN 0x100 /* bit8 */ - -typedef enum { - POLARIS_AVMODE_DEFAULT = 0, - POLARIS_AVMODE_DIGITAL = 0x10, - POLARIS_AVMODE_ANALOGT_TV = 0x20, - POLARIS_AVMODE_ENXTERNAL_AV = 0x30, - -} AV_MODE; +#define PWR_AV_EN 0x08 /* bit3 */ +#define PWR_ISO_EN 0x40 /* bit6 */ +#define PWR_AV_MODE 0x30 /* bit4,5 */ +#define PWR_TUNER_EN 0x04 /* bit2 */ +#define PWR_DEMOD_EN 0x02 /* bit1 */ +#define I2C_DEMOD_EN 0x01 /* bit0 */ +#define PWR_RESETOUT_EN 0x100 /* bit8 */ + +enum AV_MODE{ + POLARIS_AVMODE_DEFAULT = 0, + POLARIS_AVMODE_DIGITAL = 0x10, + POLARIS_AVMODE_ANALOGT_TV = 0x20, + POLARIS_AVMODE_ENXTERNAL_AV = 0x30, + +}; /* Colibri Registers */ @@ -91,6 +91,13 @@ typedef enum { #define ADC_COM_BIAS3 0x0e #define TESTBUS_CTRL 0x12 +#define FLD_PWRDN_TUNING_BIAS 0x10 +#define FLD_PWRDN_ENABLE_PLL 0x08 +#define FLD_PWRDN_PD_BANDGAP 0x04 +#define FLD_PWRDN_PD_BIAS 0x02 +#define FLD_PWRDN_PD_TUNECK 0x01 + + #define ADC_STATUS_CH1 0x20 #define ADC_STATUS_CH2 0x40 #define ADC_STATUS_CH3 0x60 @@ -126,7 +133,7 @@ typedef enum { #define ADC_INPUT_CH1 0x28 #define ADC_INPUT_CH2 0x48 #define ADC_INPUT_CH3 0x68 -#define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */ +#define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */ #define ADC_NTF_PRECLMP_EN_CH1 0x29 #define ADC_NTF_PRECLMP_EN_CH2 0x49 @@ -150,128 +157,128 @@ typedef enum { #define DIRECT_IF_REVB_BASE 0x00300 /*****************************************************************************/ -#define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) /* Reg Size 32 */ +#define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) /*****************************************************************************/ #define FLD_DIF_PLL_LOCK 0x80000000 /* Reserved [30:29] */ #define FLD_DIF_PLL_FREE_RUN 0x10000000 -#define FLD_DIF_PLL_FREQ 0x0FFFFFFF +#define FLD_DIF_PLL_FREQ 0x0fffffff /*****************************************************************************/ -#define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) /* Reg Size 32 */ +#define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) /*****************************************************************************/ -#define FLD_DIF_KD_PD 0xFF000000 +#define FLD_DIF_KD_PD 0xff000000 /* Reserved [23:20] */ -#define FLD_DIF_KDS_PD 0x000F0000 -#define FLD_DIF_KI_PD 0x0000FF00 +#define FLD_DIF_KDS_PD 0x000f0000 +#define FLD_DIF_KI_PD 0x0000ff00 /* Reserved [7:4] */ -#define FLD_DIF_KIS_PD 0x0000000F +#define FLD_DIF_KIS_PD 0x0000000f /*****************************************************************************/ -#define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) /* Reg Size 32 */ +#define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) /*****************************************************************************/ -#define FLD_DIF_KD_FD 0xFF000000 +#define FLD_DIF_KD_FD 0xff000000 /* Reserved [23:20] */ -#define FLD_DIF_KDS_FD 0x000F0000 -#define FLD_DIF_KI_FD 0x0000FF00 -#define FLD_DIF_SIG_PROP_SZ 0x000000F0 -#define FLD_DIF_KIS_FD 0x0000000F +#define FLD_DIF_KDS_FD 0x000f0000 +#define FLD_DIF_KI_FD 0x0000ff00 +#define FLD_DIF_SIG_PROP_SZ 0x000000f0 +#define FLD_DIF_KIS_FD 0x0000000f /*****************************************************************************/ -#define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000C) /* Reg Size 32 */ +#define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000c) /*****************************************************************************/ -#define FLD_DIF_PLL_AGC_REF 0xFFF00000 -#define FLD_DIF_PLL_AGC_KI 0x000F0000 +#define FLD_DIF_PLL_AGC_REF 0xfff00000 +#define FLD_DIF_PLL_AGC_KI 0x000f0000 /* Reserved [15] */ #define FLD_DIF_FREQ_LIMIT 0x00007000 -#define FLD_DIF_K_FD 0x00000F00 -#define FLD_DIF_DOWNSMPL_FD 0x000000FF +#define FLD_DIF_K_FD 0x00000f00 +#define FLD_DIF_DOWNSMPL_FD 0x000000ff /*****************************************************************************/ -#define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) /* Reg Size 32 */ +#define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) /*****************************************************************************/ /* Reserved [31:16] */ #define FLD_DIF_PLL_AGC_EN 0x00008000 /* Reserved [14:12] */ -#define FLD_DIF_PLL_MAN_GAIN 0x00000FFF +#define FLD_DIF_PLL_MAN_GAIN 0x00000fff /*****************************************************************************/ -#define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) /* Reg Size 32 */ +#define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) /*****************************************************************************/ -#define FLD_DIF_K_AGC_RF 0xF0000000 -#define FLD_DIF_K_AGC_IF 0x0F000000 -#define FLD_DIF_K_AGC_INT 0x00F00000 +#define FLD_DIF_K_AGC_RF 0xf0000000 +#define FLD_DIF_K_AGC_IF 0x0f000000 +#define FLD_DIF_K_AGC_INT 0x00f00000 /* Reserved [19:12] */ -#define FLD_DIF_IF_REF 0x00000FFF +#define FLD_DIF_IF_REF 0x00000fff /*****************************************************************************/ -#define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) /* Reg Size 32 */ +#define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) /*****************************************************************************/ -#define FLD_DIF_IF_MAX 0xFF000000 -#define FLD_DIF_IF_MIN 0x00FF0000 -#define FLD_DIF_IF_AGC 0x0000FFFF +#define FLD_DIF_IF_MAX 0xff000000 +#define FLD_DIF_IF_MIN 0x00ff0000 +#define FLD_DIF_IF_AGC 0x0000ffff /*****************************************************************************/ -#define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001C) /* Reg Size 32 */ +#define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001c) /*****************************************************************************/ -#define FLD_DIF_INT_MAX 0xFF000000 -#define FLD_DIF_INT_MIN 0x00FF0000 -#define FLD_DIF_INT_AGC 0x0000FFFF +#define FLD_DIF_INT_MAX 0xff000000 +#define FLD_DIF_INT_MIN 0x00ff0000 +#define FLD_DIF_INT_AGC 0x0000ffff /*****************************************************************************/ -#define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) /* Reg Size 32 */ +#define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) /*****************************************************************************/ -#define FLD_DIF_RF_MAX 0xFF000000 -#define FLD_DIF_RF_MIN 0x00FF0000 -#define FLD_DIF_RF_AGC 0x0000FFFF +#define FLD_DIF_RF_MAX 0xff000000 +#define FLD_DIF_RF_MIN 0x00ff0000 +#define FLD_DIF_RF_AGC 0x0000ffff /*****************************************************************************/ -#define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) /* Reg Size 32 */ +#define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) /*****************************************************************************/ -#define FLD_DIF_IF_AGC_IN 0xFFFF0000 -#define FLD_DIF_INT_AGC_IN 0x0000FFFF +#define FLD_DIF_IF_AGC_IN 0xffff0000 +#define FLD_DIF_INT_AGC_IN 0x0000ffff /*****************************************************************************/ -#define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) /* Reg Size 32 */ +#define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) /*****************************************************************************/ /* Reserved [31:16] */ -#define FLD_DIF_RF_AGC_IN 0x0000FFFF +#define FLD_DIF_RF_AGC_IN 0x0000ffff /*****************************************************************************/ -#define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002C) /* Reg Size 32 */ +#define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002c) /*****************************************************************************/ -#define FLD_DIF_AFD 0xC0000000 +#define FLD_DIF_AFD 0xc0000000 #define FLD_DIF_K_VID_AGC 0x30000000 -#define FLD_DIF_LINE_LENGTH 0x0FFF0000 -#define FLD_DIF_AGC_GAIN 0x0000FFFF +#define FLD_DIF_LINE_LENGTH 0x0fff0000 +#define FLD_DIF_AGC_GAIN 0x0000ffff /*****************************************************************************/ -#define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) /* Reg Size 32 */ +#define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) /*****************************************************************************/ #define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000 /* Reserved [30:30] */ -#define FLD_DIF_AUDIO_MAN_GAIN 0x3F000000 +#define FLD_DIF_AUDIO_MAN_GAIN 0x3f000000 /* Reserved [23:17] */ #define FLD_DIF_VID_AGC_OVERRIDE 0x00010000 -#define FLD_DIF_VID_MAN_GAIN 0x0000FFFF +#define FLD_DIF_VID_MAN_GAIN 0x0000ffff /*****************************************************************************/ -#define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) /* Reg Size 32 */ +#define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) /*****************************************************************************/ -#define FLD_DIF_LPF_FREQ 0xC0000000 -#define FLD_DIF_AV_PHASE_INC 0x3F000000 -#define FLD_DIF_AUDIO_FREQ 0x00FFFFFF +#define FLD_DIF_LPF_FREQ 0xc0000000 +#define FLD_DIF_AV_PHASE_INC 0x3f000000 +#define FLD_DIF_AUDIO_FREQ 0x00ffffff /*****************************************************************************/ -#define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) /* Reg Size 32 */ +#define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) /*****************************************************************************/ /* Reserved [31:24] */ -#define FLD_DIF_IIR23_R2 0x00FF0000 -#define FLD_DIF_IIR23_R1 0x0000FF00 -#define FLD_DIF_IIR1_R1 0x000000FF +#define FLD_DIF_IIR23_R2 0x00ff0000 +#define FLD_DIF_IIR23_R1 0x0000ff00 +#define FLD_DIF_IIR1_R1 0x000000ff /*****************************************************************************/ -#define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003C) /* Reg Size 32 */ +#define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003c) /*****************************************************************************/ #define FLD_DIF_DIF_BYPASS 0x80000000 #define FLD_DIF_FM_NYQ_GAIN 0x40000000 @@ -289,184 +296,184 @@ typedef enum { /* Reserved [18] */ #define FLD_DIF_IF_FREQ 0x00030000 /* Reserved [15:14] */ -#define FLD_DIF_TIP_OFFSET 0x00003F00 +#define FLD_DIF_TIP_OFFSET 0x00003f00 /* Reserved [7:5] */ #define FLD_DIF_DITHER_ENA 0x00000010 /* Reserved [3:1] */ #define FLD_DIF_RF_IF_LOCK 0x00000001 /*****************************************************************************/ -#define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) /* Reg Size 32 */ +#define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) /*****************************************************************************/ /* Reserved [31:29] */ -#define FLD_DIF_PHASE_INC 0x1FFFFFFF +#define FLD_DIF_PHASE_INC 0x1fffffff /*****************************************************************************/ -#define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) /* Reg Size 32 */ +#define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) /*****************************************************************************/ /* Reserved [31:16] */ -#define FLD_DIF_SRC_KI 0x0000FF00 -#define FLD_DIF_SRC_KD 0x000000FF +#define FLD_DIF_SRC_KI 0x0000ff00 +#define FLD_DIF_SRC_KD 0x000000ff /*****************************************************************************/ -#define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) /* Reg Size 32 */ +#define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) /*****************************************************************************/ /* Reserved [31:19] */ #define FLD_DIF_BPF_COEFF_0 0x00070000 /* Reserved [15:4] */ -#define FLD_DIF_BPF_COEFF_1 0x0000000F +#define FLD_DIF_BPF_COEFF_1 0x0000000f /*****************************************************************************/ -#define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) /* Reg Size 32 */ +#define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) /*****************************************************************************/ /* Reserved [31:22] */ -#define FLD_DIF_BPF_COEFF_2 0x003F0000 +#define FLD_DIF_BPF_COEFF_2 0x003f0000 /* Reserved [15:7] */ -#define FLD_DIF_BPF_COEFF_3 0x0000007F +#define FLD_DIF_BPF_COEFF_3 0x0000007f /*****************************************************************************/ -#define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) /* Reg Size 32 */ +#define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) /*****************************************************************************/ /* Reserved [31:24] */ -#define FLD_DIF_BPF_COEFF_4 0x00FF0000 +#define FLD_DIF_BPF_COEFF_4 0x00ff0000 /* Reserved [15:8] */ -#define FLD_DIF_BPF_COEFF_5 0x000000FF +#define FLD_DIF_BPF_COEFF_5 0x000000ff /*****************************************************************************/ -#define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) /* Reg Size 32 */ +#define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) /*****************************************************************************/ /* Reserved [31:25] */ -#define FLD_DIF_BPF_COEFF_6 0x01FF0000 +#define FLD_DIF_BPF_COEFF_6 0x01ff0000 /* Reserved [15:9] */ -#define FLD_DIF_BPF_COEFF_7 0x000001FF +#define FLD_DIF_BPF_COEFF_7 0x000001ff /*****************************************************************************/ -#define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) /* Reg Size 32 */ +#define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) /*****************************************************************************/ /* Reserved [31:26] */ -#define FLD_DIF_BPF_COEFF_8 0x03FF0000 +#define FLD_DIF_BPF_COEFF_8 0x03ff0000 /* Reserved [15:10] */ -#define FLD_DIF_BPF_COEFF_9 0x000003FF +#define FLD_DIF_BPF_COEFF_9 0x000003ff /*****************************************************************************/ -#define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005C) /* Reg Size 32 */ +#define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005c) /*****************************************************************************/ /* Reserved [31:27] */ -#define FLD_DIF_BPF_COEFF_10 0x07FF0000 +#define FLD_DIF_BPF_COEFF_10 0x07ff0000 /* Reserved [15:11] */ -#define FLD_DIF_BPF_COEFF_11 0x000007FF +#define FLD_DIF_BPF_COEFF_11 0x000007ff /*****************************************************************************/ -#define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) /* Reg Size 32 */ +#define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) /*****************************************************************************/ /* Reserved [31:27] */ -#define FLD_DIF_BPF_COEFF_12 0x07FF0000 +#define FLD_DIF_BPF_COEFF_12 0x07ff0000 /* Reserved [15:12] */ -#define FLD_DIF_BPF_COEFF_13 0x00000FFF +#define FLD_DIF_BPF_COEFF_13 0x00000fff /*****************************************************************************/ -#define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) /* Reg Size 32 */ +#define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) /*****************************************************************************/ /* Reserved [31:28] */ -#define FLD_DIF_BPF_COEFF_14 0x0FFF0000 +#define FLD_DIF_BPF_COEFF_14 0x0fff0000 /* Reserved [15:12] */ -#define FLD_DIF_BPF_COEFF_15 0x00000FFF +#define FLD_DIF_BPF_COEFF_15 0x00000fff /*****************************************************************************/ -#define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) /* Reg Size 32 */ +#define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) /*****************************************************************************/ /* Reserved [31:29] */ -#define FLD_DIF_BPF_COEFF_16 0x1FFF0000 +#define FLD_DIF_BPF_COEFF_16 0x1fff0000 /* Reserved [15:13] */ -#define FLD_DIF_BPF_COEFF_17 0x00001FFF +#define FLD_DIF_BPF_COEFF_17 0x00001fff /*****************************************************************************/ -#define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006C) /* Reg Size 32 */ +#define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006c) /*****************************************************************************/ /* Reserved [31:29] */ -#define FLD_DIF_BPF_COEFF_18 0x1FFF0000 +#define FLD_DIF_BPF_COEFF_18 0x1fff0000 /* Reserved [15:13] */ -#define FLD_DIF_BPF_COEFF_19 0x00001FFF +#define FLD_DIF_BPF_COEFF_19 0x00001fff /*****************************************************************************/ -#define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) /* Reg Size 32 */ +#define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) /*****************************************************************************/ /* Reserved [31:29] */ -#define FLD_DIF_BPF_COEFF_20 0x1FFF0000 +#define FLD_DIF_BPF_COEFF_20 0x1fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_21 0x00003FFF +#define FLD_DIF_BPF_COEFF_21 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) /* Reg Size 32 */ +#define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_22 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_22 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_23 0x00003FFF +#define FLD_DIF_BPF_COEFF_23 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) /* Reg Size 32 */ +#define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_24 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_24 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_25 0x00003FFF +#define FLD_DIF_BPF_COEFF_25 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007C) /* Reg Size 32 */ +#define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007c) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_26 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_26 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_27 0x00003FFF +#define FLD_DIF_BPF_COEFF_27 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) /* Reg Size 32 */ +#define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_28 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_28 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_29 0x00003FFF +#define FLD_DIF_BPF_COEFF_29 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) /* Reg Size 32 */ +#define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_30 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_30 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_31 0x00003FFF +#define FLD_DIF_BPF_COEFF_31 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) /* Reg Size 32 */ +#define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_32 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_32 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_33 0x00003FFF +#define FLD_DIF_BPF_COEFF_33 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008C) /* Reg Size 32 */ +#define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008c) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_34 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_34 0x3fff0000 /* Reserved [15:14] */ -#define FLD_DIF_BPF_COEFF_35 0x00003FFF +#define FLD_DIF_BPF_COEFF_35 0x00003fff /*****************************************************************************/ -#define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) /* Reg Size 32 */ +#define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) /*****************************************************************************/ /* Reserved [31:30] */ -#define FLD_DIF_BPF_COEFF_36 0x3FFF0000 +#define FLD_DIF_BPF_COEFF_36 0x3fff0000 /* Reserved [15:0] */ /*****************************************************************************/ -#define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) /* Reg Size 32 */ +#define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) /*****************************************************************************/ /* Reserved [31:20] */ -#define FLD_DIF_RPT_VARIANCE 0x000FFFFF +#define FLD_DIF_RPT_VARIANCE 0x000fffff /*****************************************************************************/ -#define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) /* Reg Size 32 */ +#define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) /*****************************************************************************/ /* Reserved [31:8] */ #define FLD_DIF_DIF_SOFT_RST 0x00000080 @@ -479,9 +486,9 @@ typedef enum { #define FLD_DIF_PLL_RST_MSK 0x00000001 /*****************************************************************************/ -#define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009C) /* Reg Size 32 */ +#define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009c) /*****************************************************************************/ /* Reserved [31:25] */ -#define FLD_DIF_CTL_IP 0x01FFFFFF +#define FLD_DIF_CTL_IP 0x01ffffff #endif |