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authorDerek Basehore <dbasehore@chromium.org>2013-11-18 11:30:48 +0100
committerLee Jones <lee.jones@linaro.org>2014-01-06 09:13:23 +0000
commit49f91ac3310da217ba877b1872d2aba907022a22 (patch)
treed0fda36a016325a775f144892b971abace9c51e4 /drivers/mfd/cros_ec_spi.c
parent9981a3146cd9f07075dcac1611ca7c06f597d66b (diff)
mfd: cros ec: spi: Increase EC transaction delay
50 us is not a long enough delay between EC transactions. At least 70 us are needed for the 16 MHz STM32L part. Increase the delay to 200 us for an extra safety margin. Reviewed-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'drivers/mfd/cros_ec_spi.c')
-rw-r--r--drivers/mfd/cros_ec_spi.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/mfd/cros_ec_spi.c b/drivers/mfd/cros_ec_spi.c
index 367ccb58ecb1..ab49fe51a5d1 100644
--- a/drivers/mfd/cros_ec_spi.c
+++ b/drivers/mfd/cros_ec_spi.c
@@ -50,10 +50,11 @@
/*
* Time between raising the SPI chip select (for the end of a
* transaction) and dropping it again (for the next transaction).
- * If we go too fast, the EC will miss the transaction. It seems
- * that 50us is enough with the 16MHz STM32 EC.
+ * If we go too fast, the EC will miss the transaction. We know that we
+ * need at least 70 us with the 16 MHz STM32 EC, so go with 200 us to be
+ * safe.
*/
-#define EC_SPI_RECOVERY_TIME_NS (50 * 1000)
+#define EC_SPI_RECOVERY_TIME_NS (200 * 1000)
/**
* struct cros_ec_spi - information about a SPI-connected EC