diff options
author | Sumit Sharma <sumsharma@nvidia.com> | 2013-03-15 15:39:00 +0530 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:03:07 -0700 |
commit | 39d017f2cc8341417fa8fabdb13a45cf107fa437 (patch) | |
tree | 4bce6446b2fbd2e3e6c78933831b8b32b1f85e70 /drivers/mfd/palmas.c | |
parent | 1a9d8a7f2f46ef826ba917ef66053b5b02f05419 (diff) |
mfd: palmas: Add support for INT5 irqs
Added support for INT5 irqs for TPS80036
Change-Id: I7e37d833d3bf0aa84e202a678f9b420b1dada832
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/209991
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Diffstat (limited to 'drivers/mfd/palmas.c')
-rw-r--r-- | drivers/mfd/palmas.c | 43 |
1 files changed, 38 insertions, 5 deletions
diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c index abc454fbfd56..da6c11eb57ee 100644 --- a/drivers/mfd/palmas.c +++ b/drivers/mfd/palmas.c @@ -127,9 +127,6 @@ static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = { }, }; -#define PALMAS_MAX_INTERRUPT_MASK_REG 4 -#define PALMAS_MAX_INTERRUPT_EDGE_REG 8 - struct palmas_regs { int reg_base; int reg_add; @@ -148,12 +145,14 @@ static struct palmas_irq_regs palmas_irq_regs = { PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT2_MASK), PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT3_MASK), PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT4_MASK), + PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT5_MASK), }, .status_reg = { PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT1_STATUS), PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT2_STATUS), PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT3_STATUS), PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT4_STATUS), + PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT5_STATUS), }, .edge_reg = { PALMAS_REGS(PALMAS_INTERRUPT_BASE, @@ -170,6 +169,8 @@ static struct palmas_irq_regs palmas_irq_regs = { PALMAS_INT3_EDGE_DETECT2_RESERVED), PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT4_EDGE_DETECT1), PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT4_EDGE_DETECT2), + PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT5_EDGE_DETECT1), + PALMAS_REGS(PALMAS_INTERRUPT_BASE, PALMAS_INT5_EDGE_DETECT2), }, }; @@ -246,6 +247,31 @@ static struct palmas_irq palmas_irqs[] = { PALMAS_IRQ(GPIO_7_IRQ, INT4_STATUS_GPIO_7, 3, PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING, PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING, 7), + /* INT5 IRQs */ + PALMAS_IRQ(GPIO_8_IRQ, INT5_STATUS_GPIO_8, 4, + PALMAS_INT5_EDGE_DETECT1_GPIO_8_RISING, + PALMAS_INT5_EDGE_DETECT1_GPIO_8_FALLING, 8), + PALMAS_IRQ(GPIO_9_IRQ, INT5_STATUS_GPIO_9, 4, + PALMAS_INT5_EDGE_DETECT1_GPIO_9_RISING, + PALMAS_INT5_EDGE_DETECT1_GPIO_9_FALLING, 8), + PALMAS_IRQ(GPIO_10_IRQ, INT5_STATUS_GPIO_10, 4, + PALMAS_INT5_EDGE_DETECT1_GPIO_10_RISING, + PALMAS_INT5_EDGE_DETECT1_GPIO_10_FALLING, 8), + PALMAS_IRQ(GPIO_11_IRQ, INT5_STATUS_GPIO_11, 4, + PALMAS_INT5_EDGE_DETECT1_GPIO_11_RISING, + PALMAS_INT5_EDGE_DETECT1_GPIO_11_FALLING, 8), + PALMAS_IRQ(GPIO_12_IRQ, INT5_STATUS_GPIO_12, 4, + PALMAS_INT5_EDGE_DETECT2_GPIO_12_RISING, + PALMAS_INT5_EDGE_DETECT2_GPIO_12_FALLING, 9), + PALMAS_IRQ(GPIO_13_IRQ, INT5_STATUS_GPIO_13, 4, + PALMAS_INT5_EDGE_DETECT2_GPIO_13_RISING, + PALMAS_INT5_EDGE_DETECT2_GPIO_13_FALLING, 9), + PALMAS_IRQ(GPIO_14_IRQ, INT5_STATUS_GPIO_14, 4, + PALMAS_INT5_EDGE_DETECT2_GPIO_14_RISING, + PALMAS_INT5_EDGE_DETECT2_GPIO_14_FALLING, 9), + PALMAS_IRQ(GPIO_15_IRQ, INT5_STATUS_GPIO_15, 4, + PALMAS_INT5_EDGE_DETECT2_GPIO_15_RISING, + PALMAS_INT5_EDGE_DETECT2_GPIO_15_FALLING, 9), }; struct palmas_irq_chip_data { @@ -481,9 +507,16 @@ static int palmas_add_irq_chip(struct palmas *palmas, int irq, int irq_flags, d->irq_regs = &palmas_irq_regs; d->irqs = palmas_irqs; + d->num_mask_regs = PALMAS_MAX_INTERRUPT_MASK_REG; + d->num_edge_regs = PALMAS_MAX_INTERRUPT_EDGE_REG; + + if (palmas->id != TPS80036) { + d->num_mask_regs = 4; + d->num_edge_regs = 8; + num_irqs = num_irqs - 8; + } + d->num_irqs = num_irqs; - d->num_mask_regs = 4; - d->num_edge_regs = 8; d->wake_count = 0; *data = d; |