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| author | Alex Frid <afrid@nvidia.com> | 2011-10-10 20:32:49 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:49:24 -0800 |
| commit | 9bfcca7af6db9bbaa9496d453168c384ca768eb5 (patch) | |
| tree | d79f2cbe28a71f6a386964e2fb76e704eea6ecd3 /drivers/misc/nct1008.c | |
| parent | 86ff7b4c0fe36fe06df6386aee577fd660471b39 (diff) | |
ARM: tegra: power: Force FW bit when SMP is enabled.
Set FW bit in CP15 auxiliary control register after LP=>G CPU mode
switch if SMP bit in the same register is set. On Tegra3 in LP mode
FW bit is always zero, even though SMP bit is retained. Hence, this
change recovers FW bit on return from LP to G-mode.
Change-Id: I9f0021ab90866cb8686d73eb6ad5bbedbb2ceb90
Reviewed-on: http://git-master/r/57203
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R37dbe2079eafcfb47babaf41b53818a9130d2bbe
Diffstat (limited to 'drivers/misc/nct1008.c')
0 files changed, 0 insertions, 0 deletions