diff options
| author | Diwakar Tundlam <dtundlam@nvidia.com> | 2014-05-05 16:55:11 -0700 |
|---|---|---|
| committer | Mandar Padmawar <mpadmawar@nvidia.com> | 2014-05-13 03:05:58 -0700 |
| commit | 90dedded03dd4d98bb47d285cc8d861a8afd399d (patch) | |
| tree | c6612af5820a0e6482adf33bd21a64fefe3c8a79 /drivers/misc | |
| parent | 82de4e40a59cff30bb504954d11b4aeed396699f (diff) | |
arm: tegra: thermal: new ATE rev and margins
Added check for new ATE rev (0.9+).
Added WAR for ATE revs 0.9-0.11 - continue to use PLL-TSOSC for thermals.
Updated thermal thresholds and CPU and GPU EDP margins per thermal
margins spreadsheet.
Bug 1429685
Bug 1510809
Bug 1511626
Change-Id: I78528be0ed6b01625dd464054fbbf39c810c8873
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/407793
Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'drivers/misc')
| -rw-r--r-- | drivers/misc/tegra-fuse/tegra12x_fuse_offsets.h | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/drivers/misc/tegra-fuse/tegra12x_fuse_offsets.h b/drivers/misc/tegra-fuse/tegra12x_fuse_offsets.h index 432a6d26d35c..c6e7e4bb0a31 100644 --- a/drivers/misc/tegra-fuse/tegra12x_fuse_offsets.h +++ b/drivers/misc/tegra-fuse/tegra12x_fuse_offsets.h @@ -128,10 +128,12 @@ DEVICE_ATTR(odm_lock, 0440, tegra_fuse_show, tegra_fuse_store); /* * Check CP fuse revision. Return value (depending on chip) is as below: * Any: ERROR: -ve: Negative return value - * T12x: CP/FT: 1: Old style CP/FT fuse - * T12x: CP1/CP2: 0: New style CP1/CP2 fuse (default for t12x) - * T13x: Old pattern: 1: Old ATE pattern CP1/CP2 fuse - * T13x: New pattern: 0: New ATE pattern CP1/CP2 fuse (default for t13x) + * T12x: CP/FT: 1: T124: Old style CP/FT fuse + * T12x: CP1/CP2: 0: T124: New style CP1/CP2 fuse (default) + * + * T13x: Old pattern: 2: T132: Old ATE CP1/CP2 fuse (rev upto 0.8) + * T13x: Mid pattern: 1: T132: Mid ATE CP1/CP2 fuse (rev 0.9 - 0.11) + * T13x: New pattern: 0: T132: New ATE CP1/CP2 fuse (rev 0.12 onwards) */ static inline int fuse_cp_rev_check(void) { @@ -148,8 +150,11 @@ static inline int fuse_cp_rev_check(void) /* T13x: all CP rev are valid */ if (chip_id == TEGRA_CHIPID_TEGRA13) { - /* CP rev < 00.9 is old ATE pattern */ - if ((rev_major == 0) && (rev_minor < 9)) + /* CP rev <= 00.8 is old ATE pattern */ + if ((rev_major == 0) && (rev_minor <= 8)) + return 2; + /* CP 00.8 > rev >= 00.11 is mid ATE pattern */ + if ((rev_major == 0) && (rev_minor <= 11)) return 1; return 0; /* default new ATE pattern */ } |