diff options
| author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2012-06-27 16:58:10 +0530 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-07-19 00:52:55 -0700 |
| commit | 61c10696751004b4a6ceda1eb6acd247800a0eff (patch) | |
| tree | 94b17026e81c65d0b214ebc12d2ec0cddb40f9e9 /drivers/mmc/host/sdhci-tegra.c | |
| parent | 4c93dd529897db120a5b8151e04598ebc864f0d2 (diff) | |
mmc: tegra: Fix SDR50 clock rate configuration
The host clock configuration in SDR50 mode is
incorrectly grouped with DDR50 mode due to which
DDR50 mode clock limits are wrongly applied even
in SDR50 mode.
Bug 965298
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/111566
(cherry picked from commit 2ad290d477e8198bace22d2623856555f07b9bf9)
Change-Id: I5d3a446e39a349209e5842d385c1b728bfb7012e
Reviewed-on: http://git-master/r/116428
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Diffstat (limited to 'drivers/mmc/host/sdhci-tegra.c')
| -rw-r--r-- | drivers/mmc/host/sdhci-tegra.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index bec338fef3b4..9329cb57c548 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -372,14 +372,7 @@ static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci, unsigned int clk_rate; unsigned int emc_clk; - /* - * In SDR50 mode, run the sdmmc controller at freq greater than - * 104MHz to ensure the core voltage is at 1.2V. If the core voltage - * is below 1.2V, CRC errors would occur during data transfers. - */ - if (sdhci->mmc->card && - (mmc_card_ddr_mode(sdhci->mmc->card) || - (sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50))) { + if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_DDR50) { /* * In ddr mode, tegra sdmmc controller clock frequency * should be double the card clock frequency. @@ -394,6 +387,13 @@ static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci, } else { clk_rate = clock * 2; } + } else if (sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50) { + /* + * In SDR50 mode, run the sdmmc controller at freq greater than + * 104MHz to ensure the core voltage is at 1.2V. If the core voltage + * is below 1.2V, CRC errors would occur during data transfers. + */ + clk_rate = clock * 2; } else { if (clock <= tegra_sdhost_min_freq) clk_rate = tegra_sdhost_min_freq; |