diff options
| author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2012-05-09 18:14:51 +0530 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-05-11 14:11:49 -0700 |
| commit | 881cc68b78cb8b188222ecb29205f5b601a8b2e5 (patch) | |
| tree | 494ed60d461fe79f1a009d4cba185af115ed683b /drivers/mmc/host/sdhci-tegra.c | |
| parent | 6ef470d530c3ce43151b61de1b32d73d2a60b3a6 (diff) | |
mmc: tegra: Fix SDR50 mode clock rate setting
In SDR50 mode, set the controller clock to double
the requested clock to ensure that the core voltage
is maintained at a min of 1.2V.
Bug 965298
Change-Id: I557a07de97efd6b44f812a11da657e03d3ddefd0
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/101522
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Diffstat (limited to 'drivers/mmc/host/sdhci-tegra.c')
| -rw-r--r-- | drivers/mmc/host/sdhci-tegra.c | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index d6ed03d4f22a..a294de18205f 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -367,8 +367,14 @@ static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci, struct tegra_sdhci_host *tegra_host = pltfm_host->priv; unsigned int clk_rate; + /* + * In SDR50 mode, run the sdmmc controller at freq greater than + * 104MHz to ensure the core voltage is at 1.2V. If the core voltage + * is below 1.2V, CRC errors would occur during data transfers. + */ if (sdhci->mmc->card && - mmc_card_ddr_mode(sdhci->mmc->card)) { + (mmc_card_ddr_mode(sdhci->mmc->card) || + (sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50))) { /* * In ddr mode, tegra sdmmc controller clock frequency * should be double the card clock frequency. @@ -381,15 +387,6 @@ static void tegra_sdhci_set_clk_rate(struct sdhci_host *sdhci, clk_rate = tegra_sdhost_std_freq; else clk_rate = clock; - - /* - * In SDR50 mode, run the sdmmc controller at 208MHz to ensure - * the core voltage is at 1.2V. If the core voltage is below 1.2V, CRC - * errors would occur during data transfers. - */ - if ((sdhci->mmc->ios.timing == MMC_TIMING_UHS_SDR50) && - (clk_rate == tegra_sdhost_std_freq)) - clk_rate <<= 1; } if (tegra_host->max_clk_limit && |