diff options
| author | Pavan Kunapuli <pkunapuli@nvidia.com> | 2012-01-10 19:25:47 +0530 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-01-16 09:05:35 -0800 |
| commit | e09bd7a46f7df0ce9e5c1d3c44c542e5e696dd53 (patch) | |
| tree | a517a569609b1929f8baa15ec318d07bac51cf39 /drivers/mmc/host/sdhci-tegra.c | |
| parent | 09187d2fc72797af9aff43db0942711744b88756 (diff) | |
mmc: tegra: Set PADPIPE_CLKEN_OVERRIDE by default
If PADPIPE_CLKEN_OVERRIDE is not set, CMD end bit
errors are observed due to timing issues on some
micro SD UHS cards.
Bug 921412
Bug 914182
Bug 905519
Change-Id: Ie926843010e3082bf3469913c1f2ced0bfb008d2
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/74315
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/75150
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'drivers/mmc/host/sdhci-tegra.c')
| -rw-r--r-- | drivers/mmc/host/sdhci-tegra.c | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 1cca7cfe9bc0..5b6b2ddd9ef7 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -171,6 +171,7 @@ static void tegra3_sdhci_post_reset_init(struct sdhci_host *sdhci) vendor_ctrl &= ~(0xFF << SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT); vendor_ctrl |= (tegra3_sdhost_max_clk[tegra_host->instance] / 1000000) << SDHCI_VENDOR_CLOCK_CNTRL_BASE_CLK_FREQ_SHIFT; + vendor_ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE; /* Set tap delay */ if (plat->tap_delay) { vendor_ctrl &= ~(0xFF << @@ -367,17 +368,11 @@ static void tegra_3x_sdhci_set_card_clock(struct sdhci_host *sdhci, unsigned int /* * Tegra3 sdmmc controller internal clock will not be stabilized when * we use a clock divider value greater than 4. The WAR is as follows. - * - Enable PADPIPE_CLK_OVERRIDE in the vendr clk cntrl register. * - Enable internal clock. * - Wait for 5 usec and do a dummy write. - * - Poll for clk stable and disable PADPIPE_CLK_OVERRIDE. + * - Poll for clk stable. */ set_clk: - /* Enable PADPIPE clk override */ - ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL); - ctrl |= SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE; - sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL); - clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) << SDHCI_DIVIDER_HI_SHIFT; @@ -404,11 +399,6 @@ set_clk: mdelay(1); } - /* Disable PADPIPE clk override */ - ctrl = sdhci_readb(sdhci, SDHCI_VENDOR_CLOCK_CNTRL); - ctrl &= ~SDHCI_VENDOR_CLOCK_CNTRL_PADPIPE_CLKEN_OVERRIDE; - sdhci_writeb(sdhci, ctrl, SDHCI_VENDOR_CLOCK_CNTRL); - clk |= SDHCI_CLOCK_CARD_EN; sdhci_writew(sdhci, clk, SDHCI_CLOCK_CONTROL); out: |