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authorDong Aisheng <b29396@freescale.com>2013-09-04 20:25:47 +0800
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 08:05:36 -0500
commit13994e723107e71180c69031e0ff501542e6488c (patch)
tree365911c10e7602a6e9a0765bfb357d4956e283de /drivers/mmc/host
parent09b1f7cdae66fc2650981c565624711dc49c4a56 (diff)
ENGR00278646-8 mmc: sdhci-esdhc: correct pre_div for imx6q
According to spec, the pre_div for imx6q should be 1, or the biggest clock rate we can get is a half of host clock rate. This may cause we can not get the proper clock rate as we want. e.g. if the desired clock is 200Mhz, however, the host clock is 200Mhz too, then it causes the actual clock we get is 100Mhz due to pre_div is 2. Signed-off-by: Dong Aisheng <b29396@freescale.com>
Diffstat (limited to 'drivers/mmc/host')
-rw-r--r--drivers/mmc/host/sdhci-esdhc-imx.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index c594a3cc5289..aac9f834f236 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -495,6 +495,9 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
goto out;
}
+ if (is_imx6q_usdhc(imx_data))
+ pre_div = 1;
+
temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
| ESDHC_CLOCK_MASK);