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authorAdrian Hunter <adrian.hunter@intel.com>2014-10-06 15:23:07 +0300
committerUlf Hansson <ulf.hansson@linaro.org>2014-10-06 15:08:14 +0200
commit8024379e0ae43b1154978c2291ce20f772cbb3bd (patch)
tree4bb43883f5e8f845a87bacb25702dd357670b95a /drivers/mmc
parent7dafca835a459ab31792d9def69ed30cf6dc08ab (diff)
mmc: sdhci-acpi: Fix Braswell eMMC timeout clock frequency
Braswell eMMC host controller specifies an incorrect timeout clock frequncy in the capabilities registers. The correct value is 1 MHz. A similar fix was done for sdhci-pci, however in the sdhci-acpi case the HID/UID is not unique so the capabilities register values are matched also. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sdhci-acpi.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c
index 7548261221b5..9cccc0e89b04 100644
--- a/drivers/mmc/host/sdhci-acpi.c
+++ b/drivers/mmc/host/sdhci-acpi.c
@@ -137,6 +137,11 @@ static int sdhci_acpi_emmc_probe_slot(struct platform_device *pdev,
/* Platform specific code during emmc proble slot goes here */
+ if (hid && uid && !strcmp(hid, "80860F14") && !strcmp(uid, "1") &&
+ sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 &&
+ sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807)
+ host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
+
return 0;
}