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authorMatt Reimer <mreimer@vpop.net>2008-11-18 10:47:42 -0800
committerDavid Woodhouse <David.Woodhouse@intel.com>2009-01-05 13:02:42 +0100
commit7f9938d0fd6c778bd0ce296a3e3b50266de2b892 (patch)
tree25425680b8a1c53d12e6995aac6b9afb8b579ee6 /drivers/mtd/nand/pxa3xx_nand.c
parenta5cce42f357b3106fb0eacd85edec5ae31288956 (diff)
[MTD] [NAND] pxa3xx: fix non-page-aligned reads
Reads from non-page-aligned addresses were broken because while the address to read from was correctly written to NDCB*, a full page was always read. Fix this by ignoring the column and only using the page address. I suspect this whole-page behavior is due to the controller's need to read the entire page in order to generate correct ECC. In the non-ECC case this could be optimized to use the column address, and to set the read length to what is being requested rather than the length of an entire page. Signed-off-by: Matt Reimer <mreimer@vpop.net> Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Diffstat (limited to 'drivers/mtd/nand/pxa3xx_nand.c')
-rw-r--r--drivers/mtd/nand/pxa3xx_nand.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index fc4144495610..7582581aefe3 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -368,14 +368,14 @@ static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
/* large block, 2 cycles for column address
* row address starts from 3rd cycle
*/
- info->ndcb1 |= (page_addr << 16) | (column & 0xffff);
+ info->ndcb1 |= page_addr << 16;
if (info->row_addr_cycles == 3)
info->ndcb2 = (page_addr >> 16) & 0xff;
} else
/* small block, 1 cycles for column address
* row address starts from 2nd cycle
*/
- info->ndcb1 = (page_addr << 8) | (column & 0xff);
+ info->ndcb1 = page_addr << 8;
if (cmd == cmdset->program)
info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;