diff options
| author | Han Xu <b45815@freescale.com> | 2015-06-05 12:26:28 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-09-17 09:23:33 -0500 |
| commit | 1bc7c434510dd5bef050c830d77395030fdb6e51 (patch) | |
| tree | 473ad109ab8373ab0fceb9c6f4a227116153f905 /drivers/mtd | |
| parent | 9b6e444dd1f899011ca1fb8f67a6f0c573fa8e13 (diff) | |
MLK-11060: Revert "MLK-10766: mtd: qspi: disable DDR_EN bit before SW reset"
This reverts commit cc2500bb20a620e191cbb20c346660d260d1e7d7.
This QSPI ddr setting was changed on i.MX6UL and i.MX7D, refer to the
below commit
commit e168ff92f780b8ef74cf7e50ad5cb9d50b1b8007
Author: Peng Fan <Peng.Fan@freescale.com>
Date: Fri May 29 09:12:22 2015 +0800
imx: qspi fix ddr delay setting
For i.MX6UL and i.MX7D, ddr delay logic enable bit is changed from
i.MX6SX.
If want to enable qspi ddr mode, ddr delay logic should be enabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Han Xu <b45815@freescale.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi-nor/fsl-quadspi.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index 6cc4822a0a73..7a5e25262199 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -780,11 +780,6 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q) if (ret) return ret; - /* clear the DDR_EN bit */ - reg = readl(base + QUADSPI_MCR); - writel(~(QUADSPI_MCR_DDR_EN_MASK) & reg, base + QUADSPI_MCR); - udelay(1); - /* Reset the module */ writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, base + QUADSPI_MCR); |