diff options
| author | Peng Fan <Peng.Fan@freescale.com> | 2015-05-29 09:12:22 +0800 |
|---|---|---|
| committer | Leonard Crestez <leonard.crestez@nxp.com> | 2018-08-24 12:20:42 +0300 |
| commit | f0706aaf1f46c29117527b870514a4c25bfe1de4 (patch) | |
| tree | fab8bcbecf287acae8e8df853c24c9f72c42c671 /drivers/mtd | |
| parent | 986bfd96919ef4daf4454e183842342ce895f3f5 (diff) | |
MLK-10996 imx: qspi fix ddr delay setting
For i.MX6UL and i.MX7D, ddr delay logic enable bit is changed from i.MX6SX.
If want to enable qspi ddr mode, ddr delay logic should be enabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked and merge from commit f28986825a7be1cbf2b5103ea110db28c96e74c7)
Signed-off-by: Han Xu <b45815@freescale.com>
Conflicts:
drivers/mtd/spi-nor/fsl-quadspi.c
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi-nor/fsl-quadspi.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index d80fdb23c9cc..e3e476d976cb 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -64,6 +64,11 @@ #define QUADSPI_MCR_SWRSTSD_SHIFT 0 #define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT) +#define QUADSPI_FLSHCR 0x0c +#define QUADSPI_FLSHCR_TDH_SHIFT 16 +#define QUADSPI_FLSHCR_TDH_MASK (3 << QUADSPI_FLSHCR_TDH_SHIFT) +#define QUADSPI_FLSHCR_TDH_DDR_EN (1 << QUADSPI_FLSHCR_TDH_SHIFT) + #define QUADSPI_IPCR 0x08 #define QUADSPI_IPCR_SEQID_SHIFT 24 #define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT) @@ -766,6 +771,14 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) reg |= MX6SX_QUADSPI_MCR_TX_DDR_DELAY_EN_MASK; qspi_writel(q, reg, q->iobase + QUADSPI_MCR); + + if ((q->devtype_data->devtype == FSL_QUADSPI_IMX6UL) || + (q->devtype_data->devtype == FSL_QUADSPI_IMX7D)) { + reg = readl(q->iobase + QUADSPI_FLSHCR); + reg &= ~QUADSPI_FLSHCR_TDH_MASK; + reg |= QUADSPI_FLSHCR_TDH_DDR_EN; + qspi_writel(q, reg, q->iobase + QUADSPI_FLSHCR); + } } } |