diff options
| author | Joe Schultz <jschultz@xes-inc.com> | 2014-04-07 11:58:18 -0500 |
|---|---|---|
| committer | Brian Norris <computersforpeace@gmail.com> | 2014-05-20 17:36:34 -0700 |
| commit | 2170480487e3dee8a74204ce346b1b1096a13fd0 (patch) | |
| tree | 12075dbaf7acb4a16d76c84c771c43eccdaaecef /drivers/mtd | |
| parent | 4454406e378722d09431aca194103aa3075c6468 (diff) | |
mtd: fsl_ifc_nand: Workaround bogus WP on 16-bit NAND
A workaround was already in place that set the WP bit in the
IFC_CSPR0 register after a STATUS command, however it used an 8-bit
write method. As a result, the WP bit was never set on 16-bit devices,
and these devices would eventually be incorrectly marked as
write-protected.
This patch checks the chip options for a 16-bit device and uses the
appropriate write method to set the WP bit after a STATUS command.
Signed-off-by: Joe Schultz <jschultz@xes-inc.com>
Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/nand/fsl_ifc_nand.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 8ed0ee1cfee1..2338124dd05f 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -591,7 +591,10 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, * The chip always seems to report that it is * write-protected, even when it is not. */ - setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP); + if (chip->options & NAND_BUSWIDTH_16) + setbits16(ifc_nand_ctrl->addr, NAND_STATUS_WP); + else + setbits8(ifc_nand_ctrl->addr, NAND_STATUS_WP); return; case NAND_CMD_RESET: |