diff options
| author | Han Xu <b45815@freescale.com> | 2015-05-08 13:33:57 -0500 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-09-17 09:22:59 -0500 |
| commit | ad7c13035dea8f298e3cca7aee459b384bb268d6 (patch) | |
| tree | 04d008752a60e51ce6829d697e67be0ee2ec95c4 /drivers/mtd | |
| parent | 427c99e5348dc5a6f1a9c49faf04df367866f8f7 (diff) | |
MLK-10766: mtd: qspi: disable DDR_EN bit before SW reset
i.MX7D QSPI does not work if SW reset SWRSTHD and SWRSTSD bit in MCR
register with DDR_EN bit enabled. Disable DDR_EN before any SW reset as
a workaround to solve the issue TKT264660.
Signed-off-by: Han Xu <b45815@freescale.com>
Diffstat (limited to 'drivers/mtd')
| -rw-r--r-- | drivers/mtd/spi-nor/fsl-quadspi.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c index ccdcab7ccf6f..5423389c5a90 100644 --- a/drivers/mtd/spi-nor/fsl-quadspi.c +++ b/drivers/mtd/spi-nor/fsl-quadspi.c @@ -766,6 +766,11 @@ static int fsl_qspi_nor_setup(struct fsl_qspi *q) if (ret) return ret; + /* clear the DDR_EN bit */ + reg = readl(base + QUADSPI_MCR); + writel(~(QUADSPI_MCR_DDR_EN_MASK) & reg, base + QUADSPI_MCR); + udelay(1); + /* Reset the module */ writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, base + QUADSPI_MCR); |