diff options
| author | Even Xu <Feng.Xu@freescale.com> | 2012-01-09 16:44:31 +0800 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-01-19 12:41:23 +0800 |
| commit | 19be3d2ec3d146c4cc33d5f246ac7d8062483858 (patch) | |
| tree | 3de668438c86e16addd176336c8e2f12436fbf7f /drivers/mxc | |
| parent | 539d3f47ae0c4a148bfcf0d0b1bc9b79af5c34a7 (diff) | |
ENGR00171564-3 MX6Q ARM2: Enable TVIN based on AutoBoard
- Add adv7180 driver to ARM2 support
- Add adv7180 configure
- Chenge CSI configure for BT656 support
Signed-off-by: Even Xu <b21019@freescale.com>
Diffstat (limited to 'drivers/mxc')
| -rw-r--r-- | drivers/mxc/ipu3/ipu_capture.c | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/drivers/mxc/ipu3/ipu_capture.c b/drivers/mxc/ipu3/ipu_capture.c index 7ed2e7df991d..2b818a0276a0 100644 --- a/drivers/mxc/ipu3/ipu_capture.c +++ b/drivers/mxc/ipu3/ipu_capture.c @@ -144,28 +144,29 @@ ipu_csi_init_interface(struct ipu_soc *ipu, uint16_t width, uint16_t height, if (width == 720 && height == 625) { /* PAL case */ /* - * Field0BlankEnd = 0x6, Field0BlankStart = 0x2, - * Field0ActiveEnd = 0x4, Field0ActiveStart = 0 + * Field0BlankEnd = 0x7, Field0BlankStart = 0x3, + * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1 */ - ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_1); + ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_1); /* - * Field1BlankEnd = 0x7, Field1BlankStart = 0x3, - * Field1ActiveEnd = 0x5, Field1ActiveStart = 0x1 + * Field1BlankEnd = 0x6, Field1BlankStart = 0x2, + * Field1ActiveEnd = 0x4, Field1ActiveStart = 0 */ - ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_2); + ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_2); ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3); + } else if (width == 720 && height == 525) { /* NTSC case */ /* - * Field0BlankEnd = 0x7, Field0BlankStart = 0x3, - * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1 - */ - ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_1); - /* * Field1BlankEnd = 0x6, Field1BlankStart = 0x2, * Field1ActiveEnd = 0x4, Field1ActiveStart = 0 */ - ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_2); + ipu_csi_write(ipu, csi, 0x40596, CSI_CCIR_CODE_1); + /* + * Field0BlankEnd = 0x7, Field0BlankStart = 0x3, + * Field0ActiveEnd = 0x5, Field0ActiveStart = 0x1 + */ + ipu_csi_write(ipu, csi, 0xD07DF, CSI_CCIR_CODE_2); ipu_csi_write(ipu, csi, 0xFF0000, CSI_CCIR_CODE_3); } else { dev_err(ipu->dev, "Unsupported CCIR656 interlaced " |