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authorWayne Zou <b36644@freescale.com>2012-04-13 08:19:46 +0800
committerFrank Li <Frank.Li@freescale.com>2012-04-13 18:56:36 +0800
commit4d5c8d7aa0d5137d337048dd82c71c77c3954fa5 (patch)
tree8e9548191bddbe1e087fcfeb87e739f7db7740b8 /drivers/mxc
parent256588d1074c4f168b7391e7962502b95a46de49 (diff)
ENGR00179513-2 IPU: Add TILED_NV12_FRAME_SIZE macro for consistency
VPU needs 4K align buffer address for tiled format data output. Use this macro for IPU/V4L2/Apps to calculate the frame/field size. Signed-off-by: Wayne Zou <b36644@freescale.com>
Diffstat (limited to 'drivers/mxc')
-rw-r--r--drivers/mxc/ipu3/ipu_device.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/drivers/mxc/ipu3/ipu_device.c b/drivers/mxc/ipu3/ipu_device.c
index c7d37df019ed..46a9645fcf25 100644
--- a/drivers/mxc/ipu3/ipu_device.c
+++ b/drivers/mxc/ipu3/ipu_device.c
@@ -371,13 +371,10 @@ static bool deinterlace_3_field(struct ipu_task_entry *t)
static u32 tiled_filed_size(struct ipu_task_entry *t)
{
- u32 y_size;
u32 field_size;
/* note: page_align is required by VPU hw ouput buffer */
- y_size = t->input.width * t->input.height/2;
- field_size = ALIGN(y_size, SZ_4K) + ALIGN(y_size/2, SZ_4K);
-
+ field_size = TILED_NV12_FRAME_SIZE(t->input.width, t->input.height/2);
return field_size;
}