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authorYanir Lubetkin <yanirx.lubetkin@intel.com>2015-06-02 17:05:38 +0300
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2015-06-03 03:38:01 -0700
commitff9174291eddb3f42a1e9429f8b919bebc33533b (patch)
treeaa5ae0f8e278b587bb931ad1005175864871804d /drivers/net/ethernet/intel/e1000e/e1000.h
parent95f0d950467f1228d4e326c11150e1750a6dd1ef (diff)
e1000e: fix flush_desc_ring implementation
The indication that a descriptor ring flush is required was read from FEXTNVM7 by mistake. It should be read from the PCI config space. Signed-off-by: Yanir Lubetkin <yanirx.lubetkin@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/e1000e/e1000.h')
-rw-r--r--drivers/net/ethernet/intel/e1000e/e1000.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/e1000.h b/drivers/net/ethernet/intel/e1000e/e1000.h
index 0abc942c966e..e78487ab18da 100644
--- a/drivers/net/ethernet/intel/e1000e/e1000.h
+++ b/drivers/net/ethernet/intel/e1000e/e1000.h
@@ -98,6 +98,8 @@ struct e1000_info;
#define DEFAULT_RADV 8
#define BURST_RDTR 0x20
#define BURST_RADV 0x20
+#define PCICFG_DESC_RING_STATUS 0xe4
+#define FLUSH_DESC_REQUIRED 0x100
/* in the case of WTHRESH, it appears at least the 82571/2 hardware
* writes back 4 descriptors when WTHRESH=5, and 3 descriptors when