diff options
| author | Raanan Avargil <raanan.avargil@intel.com> | 2015-12-22 15:35:02 +0200 |
|---|---|---|
| committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2016-02-24 14:44:01 -0800 |
| commit | 74f31299a41e729226d60426087592b6790f22b7 (patch) | |
| tree | ecc3fea1a86ee7434af79efb8c1400ec5083143b /drivers/net/ethernet/intel/e1000e/ich8lan.h | |
| parent | 6721e9d568741ced04b1fe6eed42f2ddf585eac4 (diff) | |
e1000e: Increase PHY PLL clock gate timing
Several packet loss issues were reported for which the root cause for
them was an incorrect configuration of internal HW PHY clock gating
mechanism by SW.
This patch provides the correct mechanism.
Signed-off-by: Raanan Avargil <raanan.avargil@intel.com>
Tested-by: Aaron Brown <aaron.f.brown@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net/ethernet/intel/e1000e/ich8lan.h')
| -rw-r--r-- | drivers/net/ethernet/intel/e1000e/ich8lan.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.h b/drivers/net/ethernet/intel/e1000e/ich8lan.h index 34c551e322eb..7d85f002c3d2 100644 --- a/drivers/net/ethernet/intel/e1000e/ich8lan.h +++ b/drivers/net/ethernet/intel/e1000e/ich8lan.h @@ -226,6 +226,9 @@ #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 #define HV_PM_CTRL_K1_ENABLE 0x4000 +#define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28) +#define I217_PLL_CLOCK_GATE_MASK 0x07FF + #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ /* Inband Control */ |