diff options
| author | Eugene Surovegin <ebs@ebshome.net> | 2005-10-29 12:43:14 -0700 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@pobox.com> | 2005-10-29 18:06:54 -0400 |
| commit | 7ad8a89c2e8a930a902cb0622956b27796c027e5 (patch) | |
| tree | c1241696b8fc5ab55d389f9accd80f399e3d9d86 /drivers/net/ibm_emac/ibm_emac_core.c | |
| parent | be15cd72d256e5eb3261a781b8507fac83ab33f6 (diff) | |
[PATCH] PPC 44x EMAC driver: add 440SPe support
For some reason, the hardware designers made the polarity of one bit
in the 440SPe's PHY interface register the opposite of all other PPC
440 chips. To handle this, abstract our access to this bit and do the
right thing based on the configured CPU type.
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Signed-off-by: Eugene Surovegin <ebs@ebshome.net>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Diffstat (limited to 'drivers/net/ibm_emac/ibm_emac_core.c')
| -rw-r--r-- | drivers/net/ibm_emac/ibm_emac_core.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/net/ibm_emac/ibm_emac_core.c b/drivers/net/ibm_emac/ibm_emac_core.c index 943fbd1546ff..48239e17d351 100644 --- a/drivers/net/ibm_emac/ibm_emac_core.c +++ b/drivers/net/ibm_emac/ibm_emac_core.c @@ -546,7 +546,7 @@ static int __emac_mdio_read(struct ocp_enet_private *dev, u8 id, u8 reg) /* Wait for management interface to become idle */ n = 10; - while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) { + while (!emac_phy_done(in_be32(&p->stacr))) { udelay(1); if (!--n) goto to; @@ -556,11 +556,12 @@ static int __emac_mdio_read(struct ocp_enet_private *dev, u8 id, u8 reg) out_be32(&p->stacr, EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_READ | (reg & EMAC_STACR_PRA_MASK) - | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT)); + | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) + | EMAC_STACR_START); /* Wait for read to complete */ n = 100; - while (!((r = in_be32(&p->stacr)) & EMAC_STACR_OC)) { + while (!emac_phy_done(r = in_be32(&p->stacr))) { udelay(1); if (!--n) goto to; @@ -594,7 +595,7 @@ static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg, /* Wait for management interface to be idle */ n = 10; - while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) { + while (!emac_phy_done(in_be32(&p->stacr))) { udelay(1); if (!--n) goto to; @@ -605,11 +606,11 @@ static void __emac_mdio_write(struct ocp_enet_private *dev, u8 id, u8 reg, EMAC_STACR_BASE(emac_opb_mhz()) | EMAC_STACR_STAC_WRITE | (reg & EMAC_STACR_PRA_MASK) | ((id & EMAC_STACR_PCDA_MASK) << EMAC_STACR_PCDA_SHIFT) | - (val << EMAC_STACR_PHYD_SHIFT)); + (val << EMAC_STACR_PHYD_SHIFT) | EMAC_STACR_START); /* Wait for write to complete */ n = 100; - while (!(in_be32(&p->stacr) & EMAC_STACR_OC)) { + while (!emac_phy_done(in_be32(&p->stacr))) { udelay(1); if (!--n) goto to; |