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authorAlexander Duyck <alexander.h.duyck@intel.com>2009-09-14 08:22:54 +0000
committerDavid S. Miller <davem@davemloft.net>2009-09-14 17:03:49 -0700
commit2fb02a26bda1cbc3553164a8358c303d936255c5 (patch)
treeedbe01441d2136b6a3f9a07e374cb9850cf6d751 /drivers/net/igb/e1000_defines.h
parent6b1be1990d2f7d1a3b1f25bf3e6444600665764a (diff)
igb: reset sgmii phy at start of init
Our SGMII phy code was incomplete in that it was not actually placing the phy in SGMII mode and as a result the PHY was not able to establish a link when connected to a non serdes link partner. This patch updates the code to combine the SGMII/serdes PCS init and to add the necessary reset. Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/igb/e1000_defines.h')
-rw-r--r--drivers/net/igb/e1000_defines.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
index c85829355d50..cb916833f303 100644
--- a/drivers/net/igb/e1000_defines.h
+++ b/drivers/net/igb/e1000_defines.h
@@ -44,7 +44,7 @@
#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
/* Extended Device Control */
-#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
+#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */
/* Physical Func Reset Done Indication */
#define E1000_CTRL_EXT_PFRSTD 0x00004000
#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000