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authorDavid Dillow <dave@thedillows.org>2010-03-03 16:33:10 +0000
committerDavid S. Miller <davem@davemloft.net>2010-03-04 00:53:53 -0800
commit4c020a961a812ffae9846b917304cea504c3a733 (patch)
treec2cae6ab8a1d9b62452b26ea865fdf51573464f3 /drivers/net/r8169.c
parentd0021b252eaf65ca07ed14f0d66425dd9ccab9a6 (diff)
r8169: use correct barrier between cacheable and non-cacheable memory
r8169 needs certain writes to be visible to other CPUs or the NIC before touching the hardware, but was using smp_wmb() which is only required to order cacheable memory access. Switch to wmb() which is required to order both cacheable and non-cacheable memory. Noticed by Catalin Marinas and Paul Mackerras. Signed-off-by: David Dillow <dave@thedillows.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/r8169.c')
-rw-r--r--drivers/net/r8169.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index dfc3573c91bb..9d3ebf3e975e 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -4270,7 +4270,7 @@ static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
tp->cur_tx += frags + 1;
- smp_wmb();
+ wmb();
RTL_W8(TxPoll, NPQ); /* set polling bit */
@@ -4621,7 +4621,7 @@ static int rtl8169_poll(struct napi_struct *napi, int budget)
* until it does.
*/
tp->intr_mask = 0xffff;
- smp_wmb();
+ wmb();
RTL_W16(IntrMask, tp->intr_event);
}