diff options
| author | Jianzheng Zhou <jianzheng.zhou@freescale.com> | 2013-10-15 17:32:51 +0800 |
|---|---|---|
| committer | Jianzheng Zhou <jianzheng.zhou@freescale.com> | 2013-10-15 17:59:49 +0800 |
| commit | 5be7e0e0b0f4f1039ecf07aeef7346fe2285e053 (patch) | |
| tree | 9eabd020f0549cfc67a3c8e0c666c0cd01714c89 /drivers/net/wireless/rtl8723as/hal/rtl8723a | |
| parent | e47c5c2627d3b7e0cb429a512842843f0a781e3b (diff) | |
ENGR00275869 wifi: update new rtl8723as wifi driver
Base on rtl8723as driver(v4.1.8_9180.20130927_BTCOEX20130528_ver3.3_beta)
still do the following changes for imx6:
1.add imx6 in Makefile.
2.fix suspend/resume issue.Just refactor runtime_pm in suspend.
Signed-off-by: Jianzheng Zhou <jianzheng.zhou@freescale.com>
Diffstat (limited to 'drivers/net/wireless/rtl8723as/hal/rtl8723a')
20 files changed, 8613 insertions, 8294 deletions
diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/Hal8723PwrSeq.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/Hal8723PwrSeq.c index 4f801cbc3e2a..97255cd3bc88 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/Hal8723PwrSeq.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/Hal8723PwrSeq.c @@ -1,91 +1,91 @@ -/*++ -Copyright (c) Realtek Semiconductor Corp. All rights reserved. - -Module Name: - Hal8723PwrSeq.c - -Abstract: - This file includes all kinds of Power Action event for RTL8188E and corresponding hardware configurtions which are released from HW SD. - -Major Change History: - When Who What - ---------- --------------- ------------------------------- - 2011-08-08 Roger Create. - ---*/ -#include "Hal8723PwrSeq.h" - - -/* - drivers should parse below arrays and do the corresponding actions -*/ -//3 Power on Array -WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS]= -{ - RTL8723A_TRANS_CARDEMU_TO_ACT - RTL8723A_TRANS_END -}; - -//3 Radio off GPIO Array -WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS]= -{ - RTL8723A_TRANS_ACT_TO_CARDEMU - RTL8723A_TRANS_END -}; - -//3 Card Disable Array -WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS]= -{ - RTL8723A_TRANS_ACT_TO_CARDEMU - RTL8723A_TRANS_CARDEMU_TO_CARDDIS - RTL8723A_TRANS_END -}; - -//3 Card Enable Array -WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS]= -{ - RTL8723A_TRANS_CARDDIS_TO_CARDEMU - RTL8723A_TRANS_CARDEMU_TO_ACT - RTL8723A_TRANS_END -}; - -//3 Suspend Array -WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS]= -{ - RTL8723A_TRANS_ACT_TO_CARDEMU - RTL8723A_TRANS_CARDEMU_TO_SUS - RTL8723A_TRANS_END -}; - -//3 Resume Array -WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS]= -{ - RTL8723A_TRANS_SUS_TO_CARDEMU - RTL8723A_TRANS_CARDEMU_TO_ACT - RTL8723A_TRANS_END -}; - -//3 HWPDN Array -WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS]= -{ - RTL8723A_TRANS_ACT_TO_CARDEMU - RTL8723A_TRANS_CARDEMU_TO_PDN - RTL8723A_TRANS_END -}; - -//3 Enter LPS -WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS]= -{ - //FW behavior - RTL8723A_TRANS_ACT_TO_LPS - RTL8723A_TRANS_END -}; - -//3 Leave LPS -WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS]= -{ - //FW behavior - RTL8723A_TRANS_LPS_TO_ACT - RTL8723A_TRANS_END -}; - +/*++
+Copyright (c) Realtek Semiconductor Corp. All rights reserved.
+
+Module Name:
+ Hal8723PwrSeq.c
+
+Abstract:
+ This file includes all kinds of Power Action event for RTL8188E and corresponding hardware configurtions which are released from HW SD.
+
+Major Change History:
+ When Who What
+ ---------- --------------- -------------------------------
+ 2011-08-08 Roger Create.
+
+--*/
+#include "Hal8723PwrSeq.h"
+
+
+/*
+ drivers should parse below arrays and do the corresponding actions
+*/
+//3 Power on Array
+WLAN_PWR_CFG rtl8723A_power_on_flow[RTL8723A_TRANS_CARDEMU_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS]=
+{
+ RTL8723A_TRANS_CARDEMU_TO_ACT
+ RTL8723A_TRANS_END
+};
+
+//3 Radio off GPIO Array
+WLAN_PWR_CFG rtl8723A_radio_off_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_END_STEPS]=
+{
+ RTL8723A_TRANS_ACT_TO_CARDEMU
+ RTL8723A_TRANS_END
+};
+
+//3 Card Disable Array
+WLAN_PWR_CFG rtl8723A_card_disable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS]=
+{
+ RTL8723A_TRANS_ACT_TO_CARDEMU
+ RTL8723A_TRANS_CARDEMU_TO_CARDDIS
+ RTL8723A_TRANS_END
+};
+
+//3 Card Enable Array
+WLAN_PWR_CFG rtl8723A_card_enable_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS]=
+{
+ RTL8723A_TRANS_CARDDIS_TO_CARDEMU
+ RTL8723A_TRANS_CARDEMU_TO_ACT
+ RTL8723A_TRANS_END
+};
+
+//3 Suspend Array
+WLAN_PWR_CFG rtl8723A_suspend_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS]=
+{
+ RTL8723A_TRANS_ACT_TO_CARDEMU
+ RTL8723A_TRANS_CARDEMU_TO_SUS
+ RTL8723A_TRANS_END
+};
+
+//3 Resume Array
+WLAN_PWR_CFG rtl8723A_resume_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_SUS_STEPS+RTL8723A_TRANS_END_STEPS]=
+{
+ RTL8723A_TRANS_SUS_TO_CARDEMU
+ RTL8723A_TRANS_CARDEMU_TO_ACT
+ RTL8723A_TRANS_END
+};
+
+//3 HWPDN Array
+WLAN_PWR_CFG rtl8723A_hwpdn_flow[RTL8723A_TRANS_ACT_TO_CARDEMU_STEPS+RTL8723A_TRANS_CARDEMU_TO_PDN_STEPS+RTL8723A_TRANS_END_STEPS]=
+{
+ RTL8723A_TRANS_ACT_TO_CARDEMU
+ RTL8723A_TRANS_CARDEMU_TO_PDN
+ RTL8723A_TRANS_END
+};
+
+//3 Enter LPS
+WLAN_PWR_CFG rtl8723A_enter_lps_flow[RTL8723A_TRANS_ACT_TO_LPS_STEPS+RTL8723A_TRANS_END_STEPS]=
+{
+ //FW behavior
+ RTL8723A_TRANS_ACT_TO_LPS
+ RTL8723A_TRANS_END
+};
+
+//3 Leave LPS
+WLAN_PWR_CFG rtl8723A_leave_lps_flow[RTL8723A_TRANS_LPS_TO_ACT_STEPS+RTL8723A_TRANS_END_STEPS]=
+{
+ //FW behavior
+ RTL8723A_TRANS_LPS_TO_ACT
+ RTL8723A_TRANS_END
+};
+
diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_bt-coexist.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_bt-coexist.c index 34025b0bb50e..4ac0a4a6bd64 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_bt-coexist.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_bt-coexist.c @@ -27,7 +27,7 @@ //#define BT_DEBUG -#define CHECK_BT_EXIST_FROM_REG +//#define CHECK_BT_EXIST_FROM_REG #define DIS_PS_RX_BCN //#define BTCOEX_DECREASE_WIFI_POWER //#define BTCOEX_CMCC_TEST @@ -144,7 +144,7 @@ static u8 PlatformCancelTimer(PADAPTER a, _timer *ptimer) #define PlatformScheduleWorkItem(pwork) _set_workitem(pwork) #if 0 #define GET_UNDECORATED_AVERAGE_RSSI(padapter) \ - (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE) ? \ + (BTDM_CheckFWState(padapter, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE) ? \ (GET_HAL_DATA(padapter)->dmpriv.EntryMinUndecoratedSmoothedPWDB): \ (GET_HAL_DATA(padapter)->dmpriv.UndecoratedSmoothedPWDB) #else @@ -216,6 +216,14 @@ void BT_SignalCompensation(PADAPTER padapter, u8 *rssi_wifi, u8 *rssi_bt) void BT_WifiScanNotify(PADAPTER padapter, u8 scanType) { +#if defined(CONFIG_CONCURRENT_MODE) + if (padapter->adapter_type != PRIMARY_ADAPTER) + { + RTPRINT(FBT, BT_TRACE, ("[DM][BT], CONFIG_CONCURRENT_MODE and padapter->adapter_type != PRIMARY_ADAPTER in %s!!\n", __FUNCTION__)); + return; + } +#endif + BTHCI_WifiScanNotify(padapter, scanType); BTDM_CheckAntSelMode(padapter); BTDM_WifiScanNotify(padapter, scanType); @@ -223,6 +231,14 @@ void BT_WifiScanNotify(PADAPTER padapter, u8 scanType) void BT_WifiAssociateNotify(PADAPTER padapter, u8 action) { +#if defined(CONFIG_CONCURRENT_MODE) + if (padapter->adapter_type != PRIMARY_ADAPTER) + { + RTPRINT(FBT, BT_TRACE, ("[DM][BT], CONFIG_CONCURRENT_MODE and padapter->adapter_type != PRIMARY_ADAPTER in %s!!\n", __FUNCTION__)); + return; + } +#endif + // action : // TRUE = associate start // FALSE = associate finished @@ -234,11 +250,27 @@ void BT_WifiAssociateNotify(PADAPTER padapter, u8 action) void BT_WifiMediaStatusNotify(PADAPTER padapter, RT_MEDIA_STATUS mstatus) { +#if defined(CONFIG_CONCURRENT_MODE) + if (padapter->adapter_type != PRIMARY_ADAPTER) + { + RTPRINT(FBT, BT_TRACE, ("[DM][BT], CONFIG_CONCURRENT_MODE and padapter->adapter_type != PRIMARY_ADAPTER in %s!!\n", __FUNCTION__)); + return; + } +#endif + BTDM_MediaStatusNotify(padapter, mstatus); } void BT_SpecialPacketNotify(PADAPTER padapter) { +#if defined(CONFIG_CONCURRENT_MODE) + if (padapter->adapter_type != PRIMARY_ADAPTER) + { + RTPRINT(FBT, BT_TRACE, ("[DM][BT], CONFIG_CONCURRENT_MODE and padapter->adapter_type != PRIMARY_ADAPTER in %s!!\n", __FUNCTION__)); + return; + } +#endif + BTDM_ForDhcp(padapter); } @@ -295,7 +327,7 @@ void BTPKT_WPAAuthINITIALIZE(PADAPTER padapter, u8 EntryNum) if (pHalData->bBTMode) { // if (padapter->MgntInfo.OpMode == RT_OP_MODE_IBSS) - if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE) + if (BTDM_CheckFWState(padapter, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE) { pBtSec->bUsedHwEncrypt = _FALSE; } @@ -745,7 +777,7 @@ void bthci_DecideBTChannel(PADAPTER padapter, u8 EntryNum) IsAPModeExist(padapter)|| BTHCI_HsConnectionEstablished(padapter))) #else - if (!(check_fwstate(pmlmepriv, WIFI_ASOC_STATE|WIFI_ADHOC_STATE|WIFI_AP_STATE) == _TRUE || + if (!(BTDM_CheckFWState(padapter, WIFI_ASOC_STATE|WIFI_ADHOC_STATE|WIFI_AP_STATE) == _TRUE || BTHCI_HsConnectionEstablished(padapter))) #endif { @@ -1462,7 +1494,7 @@ bthci_AssocPreferredChannelList( pMgntInfo->mIbss || IsExtAPModeExist(padapter)) || #else - (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE) == _TRUE) || + (BTDM_CheckFWState(padapter, WIFI_ASOC_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE) == _TRUE) || #endif BTHCI_HsConnectionEstablished(padapter)) { @@ -1591,7 +1623,7 @@ u8 bthci_CheckRfStateBeforeConnect(PADAPTER padapter) pBTInfo = GET_BT_INFO(padapter); // rtw_hal_get_hwreg(padapter, HW_VAR_RF_STATE, (u8*)(&RfState)); - RfState = padapter->pwrctrlpriv.rf_pwrstate; + RfState = adapter_to_pwrctl(padapter)->rf_pwrstate; if (RfState != rf_on) { @@ -4249,7 +4281,7 @@ bthci_CmdReadLocalAMPInfo( { // PMGNT_INFO pMgntInfo = &padapter->MgntInfo; - struct pwrctrl_priv *ppwrctrl = &padapter->pwrctrlpriv; + struct pwrctrl_priv *ppwrctrl = adapter_to_pwrctl(padapter); u8 localBuf[TmpLocalBufSize] = ""; u8 *pRetPar; u8 len = 0; @@ -5353,15 +5385,15 @@ bthci_CmdWIFIConnectionStatus( } } #else - if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) { + if (BTDM_CheckFWState(padapter, WIFI_AP_STATE) == _TRUE) { if (padapter->stapriv.asoc_sta_count >= 3) connectStatus = HCI_WIFI_CONNECTED; else connectStatus = HCI_WIFI_NOT_CONNECTED; } - else if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_ASOC_STATE) == _TRUE) + else if (BTDM_CheckFWState(padapter, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_ASOC_STATE) == _TRUE) connectStatus = HCI_WIFI_CONNECTED; - else if (check_fwstate(&padapter->mlmepriv, WIFI_UNDER_LINKING) == _TRUE) + else if (BTDM_CheckFWState(padapter, WIFI_UNDER_LINKING) == _TRUE) connectStatus = HCI_WIFI_CONNECT_IN_PROGRESS; else connectStatus = HCI_WIFI_NOT_CONNECTED; @@ -6526,7 +6558,7 @@ bthci_StateDisconnected( (MgntIsLinkInProgress(pMgntInfo))|| (MgntScanInProgress(pMgntInfo))) #else - while (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE|WIFI_SITE_MONITOR) == _TRUE) + while (BTDM_CheckFWState(padapter, WIFI_ASOC_STATE|WIFI_SITE_MONITOR) == _TRUE) #endif { RTPRINT(FIOCTL, IOCTL_STATE, ("Scan/Roaming/Wifi Link is in Progress, wait 200 ms\n")); @@ -6959,7 +6991,7 @@ u8 bthci_WaitForRfReady(PADAPTER padapter) u8 bRet = _FALSE; // PRT_POWER_SAVE_CONTROL pPSC = GET_POWER_SAVE_CONTROL(&(padapter->MgntInfo)); - struct pwrctrl_priv *ppwrctrl = &padapter->pwrctrlpriv; + struct pwrctrl_priv *ppwrctrl = adapter_to_pwrctl(padapter); rt_rf_power_state RfState; u32 waitcnt = 0; @@ -7070,7 +7102,7 @@ u8 BTHCI_GetCurrentEntryNumByMAC(PADAPTER padapter, u8 *SA) void BTHCI_StatusWatchdog(PADAPTER padapter) { // PMGNT_INFO pMgntInfo = &padapter->MgntInfo; - struct pwrctrl_priv *ppwrctrl = &padapter->pwrctrlpriv; + struct pwrctrl_priv *ppwrctrl = adapter_to_pwrctl(padapter); PBT30Info pBTInfo = GET_BT_INFO(padapter); PBT_MGNT pBtMgnt = &pBTInfo->BtMgnt; PBT_TRAFFIC pBtTraffic = &pBTInfo->BtTraffic; @@ -7113,7 +7145,7 @@ void BTHCI_StatusWatchdog(PADAPTER padapter) !MgntIsLinkInProgress(pMgntInfo) && !MgntScanInProgress(pMgntInfo) && #else - if ((check_fwstate(&padapter->mlmepriv, WIFI_REASOC_STATE|WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) && + if ((BTDM_CheckFWState(padapter, WIFI_REASOC_STATE|WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _FALSE) && #endif !bRfOff) { @@ -7166,7 +7198,7 @@ BTHCI_NotifyRFState( PMGNT_INFO pMgntInfo = &padapter->MgntInfo; RT_RF_CHANGE_SOURCE RfOffReason = pMgntInfo->RfOffReason; #else - struct pwrctrl_priv *ppwrctrl = &padapter->pwrctrlpriv; + struct pwrctrl_priv *ppwrctrl = adapter_to_pwrctl(padapter); RT_RF_CHANGE_SOURCE RfOffReason = ppwrctrl->rfoff_reason; #endif @@ -8104,7 +8136,7 @@ void btdm_1AntSetPSMode(PADAPTER padapter, u8 enable, u8 smartps, u8 mode) RTPRINT(FBT, BT_TRACE, ("[BTCoex], Current LPS(%s, %d), smartps=%d\n", enable==_TRUE?"ON":"OFF", mode, smartps)); - pwrctrl = &padapter->pwrctrlpriv; + pwrctrl = adapter_to_pwrctl(padapter); if (enable == _TRUE) { rtw_set_ps_mode(padapter, PS_MODE_MIN, smartps, mode); @@ -8147,6 +8179,41 @@ u8 btdm_Is1AntPsTdmaStateChange(PADAPTER padapter) } } +void btdm_1AntSetBTCoexTable(PADAPTER padapter, u8 coexCase) +{ + switch (coexCase) + { + case 0: + rtw_write32(padapter, REG_BT_COEX_TABLE_1, 0x55555555); + rtw_write32(padapter, REG_BT_COEX_TABLE_2, 0x55555555); + break; + case 1: + rtw_write32(padapter, REG_BT_COEX_TABLE_1, 0x55555555); + rtw_write32(padapter, REG_BT_COEX_TABLE_2, 0x5afa5afa); + break; + case 2: + rtw_write32(padapter, REG_BT_COEX_TABLE_1, 0x5a5a5a5a); + rtw_write32(padapter, REG_BT_COEX_TABLE_2, 0x5a5a5a5a); + break; + case 3: + rtw_write32(padapter, REG_BT_COEX_TABLE_1, 0xaaaaaaaa); + rtw_write32(padapter, REG_BT_COEX_TABLE_2, 0xaaaaaaaa); + break; + case 4: + rtw_write32(padapter, REG_BT_COEX_TABLE_1, 0xffffffff); + rtw_write32(padapter, REG_BT_COEX_TABLE_2, 0xffffffff); + break; + case 5: + rtw_write32(padapter, REG_BT_COEX_TABLE_1, 0x5fff5fff); + rtw_write32(padapter, REG_BT_COEX_TABLE_2, 0x5fff5fff); + break; + case 6: + rtw_write32(padapter, REG_BT_COEX_TABLE_1, 0x55ff55ff); + rtw_write32(padapter, REG_BT_COEX_TABLE_2, 0x5a5a5a5a); + break; + } +} + // Before enter TDMA, make sure Power Saving is enable! void btdm_1AntPsTdma( @@ -8171,22 +8238,24 @@ btdm_1AntPsTdma( if (btdm_Is1AntPsTdmaStateChange(padapter)) { // wide duration for WiFi - BTDM_SetFw3a(padapter, 0xd3, 0x1a, 0x1a, 0x0, 0x58); + BTDM_SetFw3a(padapter, 0xd3, 0x1a, 0x1a, 0x0, 0x50); + btdm_1AntSetBTCoexTable(padapter, 6); } break; case 2: // A2DP Level-2 if (btdm_Is1AntPsTdmaStateChange(padapter)) { // normal duration for WiFi - BTDM_SetFw3a(padapter, 0xd3, 0x12, 0x12, 0x0, 0x58); + BTDM_SetFw3a(padapter, 0xd3, 0x12, 0x12, 0x0, 0x50); + btdm_1AntSetBTCoexTable(padapter, 6); } break; case 3: // BT FTP/OPP if (btdm_Is1AntPsTdmaStateChange(padapter)) { // normal duration for WiFi - BTDM_SetFw3a(padapter, 0xd3, 0x30, 0x03, 0x10, 0x58); - + BTDM_SetFw3a(padapter, 0x53, 0x30, 0x03, 0x10, 0x50); + btdm_1AntSetBTCoexTable(padapter, 6); } break; case 4: // for wifi scan & BT is connected @@ -8194,13 +8263,15 @@ btdm_1AntPsTdma( { // protect 3 beacons in 3-beacon period & no Tx pause at BT slot BTDM_SetFw3a(padapter, 0x93, 0x15, 0x03, 0x14, 0x0); + btdm_1AntSetBTCoexTable(padapter, 1); } break; case 5: // for WiFi connected-busy & BT is Non-Connected-Idle if (btdm_Is1AntPsTdmaStateChange(padapter)) { // SCO mode, Ant fixed at WiFi, WLAN_Act toggle - BTDM_SetFw3a(padapter, 0x61, 0x15, 0x03, 0x31, 0x00); + BTDM_SetFw3a(padapter, 0x61, 0x15, 0x03, 0x31, 0x10); + btdm_1AntSetBTCoexTable(padapter, 2); } break; case 9: // ACL high-retry type - 2 @@ -8208,19 +8279,22 @@ btdm_1AntPsTdma( { // narrow duration for WiFi BTDM_SetFw3a(padapter, 0xd3, 0xa, 0xa, 0x0, 0x58); //narrow duration for WiFi + btdm_1AntSetBTCoexTable(padapter, 6); } break; case 10: // for WiFi connect idle & BT ACL busy or WiFi Connected-Busy & BT is Inquiry if (btdm_Is1AntPsTdmaStateChange(padapter)) { BTDM_SetFw3a(padapter, 0x13, 0xa, 0xa, 0x0, 0x40); + btdm_1AntSetBTCoexTable(padapter, 2); } break; case 11: // ACL high-retry type - 3 if (btdm_Is1AntPsTdmaStateChange(padapter)) { // narrow duration for WiFi - BTDM_SetFw3a(padapter, 0xd3, 0x05, 0x05, 0x00, 0x58); + BTDM_SetFw3a(padapter, 0x53, 0x10, 0x03, 0x10, 0x50); + btdm_1AntSetBTCoexTable(padapter, 6); } break; case 12: // for WiFi Connected-Busy & BT is Connected-Idle @@ -8228,68 +8302,91 @@ btdm_1AntPsTdma( { // Allow High-Pri BT BTDM_SetFw3a(padapter, 0xeb, 0x0a, 0x03, 0x31, 0x18); + btdm_1AntSetBTCoexTable(padapter, 2); } break; case 20: // WiFi only busy ,TDMA mode for power saving if (btdm_Is1AntPsTdmaStateChange(padapter)) { BTDM_SetFw3a(padapter, 0x13, 0x25, 0x25, 0x00, 0x00); + btdm_1AntSetBTCoexTable(padapter, 2); } break; case 27: // WiFi DHCP/Site Survey & BT SCO busy if (btdm_Is1AntPsTdmaStateChange(padapter)) { BTDM_SetFw3a(padapter, 0xa3, 0x25, 0x03, 0x31, 0x98); + btdm_1AntSetBTCoexTable(padapter, 2); } break; case 28: // WiFi DHCP/Site Survey & BT idle if (btdm_Is1AntPsTdmaStateChange(padapter)) { BTDM_SetFw3a(padapter, 0x69, 0x25, 0x03, 0x31, 0x00); + btdm_1AntSetBTCoexTable(padapter, 2); } break; case 29: // WiFi DHCP/Site Survey & BT ACL busy if (btdm_Is1AntPsTdmaStateChange(padapter)) { BTDM_SetFw3a(padapter, 0xeb, 0x1a, 0x1a, 0x01, 0x18); - rtw_write32(padapter, 0x6c0, 0x5afa5afa); - rtw_write32(padapter, 0x6c4, 0x5afa5afa); + btdm_1AntSetBTCoexTable(padapter, 1); } break; case 30: // WiFi idle & BT Inquiry if (btdm_Is1AntPsTdmaStateChange(padapter)) { BTDM_SetFw3a(padapter, 0x93, 0x15, 0x03, 0x14, 0x00); + btdm_1AntSetBTCoexTable(padapter, 0); } break; case 31: // BT HID if (btdm_Is1AntPsTdmaStateChange(padapter)) { - BTDM_SetFw3a(padapter, 0xd3, 0x1a, 0x1a, 0x00, 0x58); + BTDM_SetFw3a(padapter, 0x53, 0x12, 0x12, 0x00, 0x50); + btdm_1AntSetBTCoexTable(padapter, 6); } break; case 32: // BT SCO & Inquiry if (btdm_Is1AntPsTdmaStateChange(padapter)) { - BTDM_SetFw3a(padapter, 0xab, 0x0a, 0x03, 0x11, 0x98); + BTDM_SetFw3a(padapter, 0xa3, 0x0a, 0x03, 0x14, 0x00); + btdm_1AntSetBTCoexTable(padapter, 0); } break; case 33: // BT SCO & WiFi site survey if (btdm_Is1AntPsTdmaStateChange(padapter)) { BTDM_SetFw3a(padapter, 0xa3, 0x25, 0x03, 0x30, 0x98); + btdm_1AntSetBTCoexTable(padapter, 2); } break; case 34: // BT HID & WiFi site survey if (btdm_Is1AntPsTdmaStateChange(padapter)) { - BTDM_SetFw3a(padapter, 0xd3, 0x1a, 0x1a, 0x00, 0x18); + BTDM_SetFw3a(padapter, 0xd3, 0x1a, 0x1a, 0x00, 0x10); + btdm_1AntSetBTCoexTable(padapter, 1); } break; case 35: // BT HID & WiFi Connecting if (btdm_Is1AntPsTdmaStateChange(padapter)) { - BTDM_SetFw3a(padapter, 0xe3, 0x1a, 0x1a, 0x00, 0x18); + BTDM_SetFw3a(padapter, 0xe3, 0x1a, 0x1a, 0x00, 0x10); + btdm_1AntSetBTCoexTable(padapter, 1); + } + break; + case 36: // BT A2DP/FTP/A2DP+HID/FTP+A2DP & WiFi LPS + if (btdm_Is1AntPsTdmaStateChange(padapter)) + { + BTDM_SetFw3a(padapter, 0x23, 0x20, 0x00, 0x10, 0x24); + btdm_1AntSetBTCoexTable(padapter, 2); + } + break; + case 37: + if (btdm_Is1AntPsTdmaStateChange(padapter)) + { + BTDM_SetFw3a(padapter, 0x53, 0x10, 0x03, 0x10, 0x10); + btdm_1AntSetBTCoexTable(padapter, 6); } break; } @@ -8326,6 +8423,7 @@ btdm_1AntPsTdma( RTPRINT(FBT, BT_TRACE, ("[BTCoex], 0x860=0x110, Switch Antenna to WiFi\n")); break; } + btdm_1AntSetBTCoexTable(padapter, 2); } RTPRINT(FBT, BT_TRACE, ("[BTCoex], Current TDMA(%s, %d)\n", @@ -8345,7 +8443,7 @@ void _btdm_1AntSetPSTDMA(PADAPTER padapter, u8 bPSEn, u8 smartps, u8 psOption, u u8 bSwitchPS; - if ((check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _FALSE) && + if ((BTDM_CheckFWState(padapter, WIFI_STATION_STATE) == _FALSE) && (get_fwstate(&padapter->mlmepriv) != WIFI_NULL_STATE)) { btdm_1AntPsTdma(padapter, bTDMAOn, tdmaType); @@ -8361,7 +8459,7 @@ void _btdm_1AntSetPSTDMA(PADAPTER padapter, u8 bPSEn, u8 smartps, u8 psOption, u bPSEn==_TRUE?"ON":"OFF", psOption, bTDMAOn==_TRUE?"ON":"OFF", tdmaType)); - pwrctrl = &padapter->pwrctrlpriv; + pwrctrl = adapter_to_pwrctl(padapter); pHalData = GET_HAL_DATA(padapter); pBtdm8723 = &pHalData->bt_coexist.halCoex8723.btdm1Ant; @@ -8606,7 +8704,12 @@ void btdm_1AntTdmaDurationAdjustForACL(PADAPTER padapter) if (pBtdm8723->psTdmaMonitorCnt == 0) { // RTPRINT(FBT, BT_TRACE, ("[BTCoex], 1AntTdmaAdjACL, first time execute!!\n")); - btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 2); + btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 9); + if(pHalData->bt_coexist.halCoex8723.btInfoExt){ + pBtdm8723->psTdmaDuAdjType = 9; + RTPRINT(FBT, BT_TRACE, ("[BTCoex], 1AntTdmaAdjACL, limit to type9 \n")); + } + else pBtdm8723->psTdmaDuAdjType = 2; } else @@ -8666,7 +8769,7 @@ void btdm_1AntTdmaDurationAdjustForACL(PADAPTER padapter) } else if (pBtdm8723->curPsTdma == 9) { - if (pHalData->bt_coexist.halCoex8723.btInfoExt){ + if ((pHalData->bt_coexist.halCoex8723.btInfoExt) || (pHalData->bt_coexist.halCoex8723.btRssi <= 32)){ pBtdm8723->psTdmaDuAdjType = 9; // RTPRINT(FBT, BT_TRACE, ("[BTCoex], 1AntTdmaAdjACL, limit to type9 \n")); } @@ -8676,7 +8779,7 @@ void btdm_1AntTdmaDurationAdjustForACL(PADAPTER padapter) } else if (pBtdm8723->curPsTdma == 2) { - if (pHalData->bt_coexist.halCoex8723.btInfoExt){ + if ((pHalData->bt_coexist.halCoex8723.btInfoExt) || (pHalData->bt_coexist.halCoex8723.btRssi <=32)){ pBtdm8723->psTdmaDuAdjType = 9; // RTPRINT(FBT, BT_TRACE, ("[BTCoex], 1AntTdmaAdjACL, limit to type9 \n")); } @@ -8855,9 +8958,9 @@ void btdm_1AntCoexProcessForWifiConnect(PADAPTER padapter) RTPRINT(FBT, BT_TRACE, ("[BTCoex], WiFi is %s\n", BTDM_IsWifiBusy(padapter)?"Busy":"IDLE")); RTPRINT(FBT, BT_TRACE, ("[BTCoex], BT is %s\n", BtStateString[BtState])); - padapter->pwrctrlpriv.btcoex_rfon = _FALSE; + adapter_to_pwrctl(padapter)->btcoex_rfon = _FALSE; - if ((!BTDM_IsWifiBusy(padapter)) &&(check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) != _TRUE)&& + if ((!BTDM_IsWifiBusy(padapter)) &&(BTDM_CheckFWState(padapter, WIFI_AP_STATE) != _TRUE)&& ((BtState == BT_INFO_STATE_NO_CONNECTION) || (BtState == BT_INFO_STATE_CONNECT_IDLE))) { switch (BtState) @@ -8866,7 +8969,7 @@ void btdm_1AntCoexProcessForWifiConnect(PADAPTER padapter) _btdm_1AntSetPSTDMA(padapter, _TRUE, 2, 0x26, _FALSE, 9); break; case BT_INFO_STATE_CONNECT_IDLE: - _btdm_1AntSetPSTDMA(padapter, _TRUE, 2, 0x26, _FALSE, 0); + _btdm_1AntSetPSTDMA(padapter, _TRUE, 2, 0x26, _FALSE, 9); break; } } @@ -8898,13 +9001,11 @@ void btdm_1AntCoexProcessForWifiConnect(PADAPTER padapter) case BT_INFO_STATE_CONNECT_IDLE: // WiFi is Busy btdm_1AntSetPSTDMA(padapter, _FALSE, 0, _TRUE, 5); - rtw_write32(padapter, 0x6c0, 0x5a5a5a5a); - rtw_write32(padapter, 0x6c4, 0x5a5a5a5a); break; case BT_INFO_STATE_ACL_INQ_OR_PAG: RTPRINT(FBT, BT_TRACE, ("[BTCoex], BT PROFILE is BT_INFO_STATE_ACL_INQ_OR_PAG\n")); case BT_INFO_STATE_INQ_OR_PAG: - padapter->pwrctrlpriv.btcoex_rfon = _TRUE; + adapter_to_pwrctl(padapter)->btcoex_rfon = _TRUE; btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 30); break; case BT_INFO_STATE_SCO_ONLY_BUSY: @@ -8917,14 +9018,17 @@ void btdm_1AntCoexProcessForWifiConnect(PADAPTER padapter) btdm_1AntSetPSTDMA(padapter, _FALSE, 0, _TRUE, 23); #else // !BTCOEX_CMCC_TEST btdm_1AntSetPSTDMA(padapter, _FALSE, 0, _FALSE, 8); - rtw_write32(padapter, 0x6c0, 0x5a5a5a5a); - rtw_write32(padapter, 0x6c4, 0x5a5a5a5a); #endif // !BTCOEX_CMCC_TEST } break; case BT_INFO_STATE_ACL_ONLY_BUSY: - padapter->pwrctrlpriv.btcoex_rfon = _TRUE; - if (pBtCoex->c2hBtProfile == BT_INFO_HID) + adapter_to_pwrctl(padapter)->btcoex_rfon = _TRUE; + if (!BTDM_IsWifiBusy(padapter)) { + //WiFi LPS + btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 37); + + } + else if (pBtCoex->c2hBtProfile == BT_INFO_HID) { RTPRINT(FBT, BT_TRACE, ("[BTCoex], BT PROFILE is HID\n")); btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 31); @@ -8939,17 +9043,37 @@ void btdm_1AntCoexProcessForWifiConnect(PADAPTER padapter) RTPRINT(FBT, BT_TRACE, ("[BTCoex], BT PROFILE is A2DP_FTP\n")); btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 11); } + else if (pBtCoex->c2hBtProfile == (BT_INFO_A2DP|BT_INFO_HID)) + { + RTPRINT(FBT, BT_TRACE, ("[BTCoex], BT PROFILE is A2DP_HID\n")); + btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 11); + } + else if (pBtCoex->c2hBtProfile == (BT_INFO_FTP|BT_INFO_HID)) + { + RTPRINT(FBT, BT_TRACE, ("[BTCoex], BT PROFILE is FTP_HID\n")); + btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 11); + } else { if (pBtCoex->c2hBtProfile == BT_INFO_A2DP) { RTPRINT(FBT, BT_TRACE, ("[BTCoex], BT PROFILE is A2DP\n")); + RTPRINT(FBT, BT_TRACE, ("[BTCoex], BT PROFILE is A2DP pBtCoex->AclTp=0x%x lowPriorityTx=%d\n",pBtCoex->AclTp,pHalData->bt_coexist.halCoex8723.lowPriorityTx)); + if(pBtCoex->AclTp > 0x3000 ||pHalData->bt_coexist.halCoex8723.lowPriorityTx >1000) + { + RTPRINT(FBT, BT_TRACE, ("[BTCoex], BT PROFILE is A2DP change to A2DP+OPP, pBtCoex->AclTp=0x%x lowPriorityTx=%d\n",pBtCoex->AclTp,pHalData->bt_coexist.halCoex8723.lowPriorityTx)); + btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 11); + } + else{ + btdm_1AntTdmaDurationAdjustForACL(padapter); + } } else { RTPRINT(FBT, BT_TRACE, ("[BTCoex], BT PROFILE is UNKNOWN(0x%02X)! Use A2DP Profile\n", pBtCoex->c2hBtProfile)); + btdm_1AntTdmaDurationAdjustForACL(padapter); } - btdm_1AntTdmaDurationAdjustForACL(padapter); + } break; } @@ -9114,7 +9238,7 @@ void btdm_1AntBTStateChangeHandler(PADAPTER padapter, BT_STATE_1ANT oldState, BT btdm_SetFwIgnoreWlanAct(padapter, _FALSE); } - if ((check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) && + if ((BTDM_CheckFWState(padapter, WIFI_STATION_STATE) == _TRUE) && (BTDM_IsWifiConnectionExist(padapter) == _TRUE)) { if ((newState == BT_INFO_STATE_SCO_ONLY_BUSY) || @@ -9185,7 +9309,7 @@ void btdm_1AntBtCoexistHandler(PADAPTER padapter) pHalData = GET_HAL_DATA(padapter); pBtCoex8723 = &pHalData->bt_coexist.halCoex8723; pBtdm8723 = &pBtCoex8723->btdm1Ant; - padapter->pwrctrlpriv.btcoex_rfon = _FALSE; + adapter_to_pwrctl(padapter)->btcoex_rfon = _FALSE; if (BT_IsBtDisabled(padapter) == _TRUE) { RTPRINT(FBT, BT_TRACE, ("[BTCoex], BT is disabled\n")); @@ -9403,8 +9527,6 @@ void BTDM_1AntWifiAssociateNotify(PADAPTER padapter, u8 type) (BtState == BT_INFO_STATE_ACL_SCO_BUSY)) { btdm_1AntSetPSTDMA(padapter, _FALSE, 0, _FALSE, 8); - rtw_write32(padapter, 0x6c0, 0x5a5a5a5a); - rtw_write32(padapter, 0x6c4, 0x5a5a5a5a); } else if ((BtState == BT_INFO_STATE_ACL_ONLY_BUSY) || (BtState == BT_INFO_STATE_ACL_INQ_OR_PAG)) @@ -9445,7 +9567,7 @@ void BTDM_1AntMediaStatusNotify(PADAPTER padapter, RT_MEDIA_STATUS mstatus) if (RT_MEDIA_CONNECT == mstatus) { - if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) + if (BTDM_CheckFWState(padapter, WIFI_STATION_STATE) == _TRUE) { if ((pBtCoex->c2hBtInfo == BT_INFO_STATE_SCO_ONLY_BUSY) || (pBtCoex->c2hBtInfo == BT_INFO_STATE_ACL_SCO_BUSY)) @@ -9454,7 +9576,7 @@ void BTDM_1AntMediaStatusNotify(PADAPTER padapter, RT_MEDIA_STATUS mstatus) } } - padapter->pwrctrlpriv.DelayLPSLastTimeStamp = rtw_get_current_time(); + adapter_to_pwrctl(padapter)->DelayLPSLastTimeStamp = rtw_get_current_time(); BTDM_1AntForDhcp(padapter); } else @@ -9486,7 +9608,8 @@ void BTDM_1AntForDhcp(PADAPTER padapter) #if 1 - BTDM_1AntWifiAssociateNotify(padapter, _TRUE); + //BTDM_1AntWifiAssociateNotify(padapter, _TRUE); + RTPRINT(FBT, BT_TRACE, ("\n[BTCoex], 1Ant for DHCP SKIP~~~~~\n")); #else @@ -9509,7 +9632,7 @@ void BTDM_1AntForDhcp(PADAPTER padapter) } else if (BtState == BT_INFO_STATE_ACL_ONLY_BUSY) { - padapter->pwrctrlpriv.btcoex_rfon = _TRUE; + adapter_to_pwrctl(padapter)->btcoex_rfon = _TRUE; if(padapter->securitypriv.ndisencryptstatus != Ndis802_11EncryptionDisabled) { btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 18); @@ -9579,18 +9702,18 @@ void BTDM_1AntWifiScanNotify(PADAPTER padapter, u8 scanType) btdm_1AntSetPSTDMA(padapter, _FALSE, 0, _TRUE, 32); else { - padapter->pwrctrlpriv.btcoex_rfon = _TRUE; + adapter_to_pwrctl(padapter)->btcoex_rfon = _TRUE; btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 33); } } else if (_TRUE == pBtCoex->bC2hBtInquiryPage) { - padapter->pwrctrlpriv.btcoex_rfon = _TRUE; + adapter_to_pwrctl(padapter)->btcoex_rfon = _TRUE; btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 30); } else if (BtState == BT_INFO_STATE_ACL_ONLY_BUSY) { - padapter->pwrctrlpriv.btcoex_rfon = _TRUE; + adapter_to_pwrctl(padapter)->btcoex_rfon = _TRUE; if (pBtCoex->c2hBtProfile == BT_INFO_HID) btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 34); else @@ -9598,7 +9721,7 @@ void BTDM_1AntWifiScanNotify(PADAPTER padapter, u8 scanType) } else { - padapter->pwrctrlpriv.btcoex_rfon = _TRUE; + adapter_to_pwrctl(padapter)->btcoex_rfon = _TRUE; btdm_1AntSetPSTDMA(padapter, _TRUE, 0, _TRUE, 5); } } @@ -9655,6 +9778,10 @@ void BTDM_1AntFwC2hBtInfo8723A(PADAPTER padapter) if (btState == 0x1) { pBtCoex->c2hBtInfo = BT_INFO_STATE_CONNECT_IDLE; + if (pBtCoex->c2hBtProfile) + { + pBtCoex->c2hBtInfo = BT_INFO_STATE_ACL_ONLY_BUSY; + } } else if (btState == 0x9) { @@ -9692,28 +9819,26 @@ void BTDM_1AntFwC2hBtInfo8723A(PADAPTER padapter) RTPRINT(FBT, BT_TRACE, ("[BTC2H], %s(%d)\n", BtStateString[pBtCoex->c2hBtInfo], pBtCoex->c2hBtInfo)); - if(pBtCoex->c2hBtProfile != BT_INFO_HID) - pBtCoex->c2hBtProfile &= ~BT_INFO_HID; +// if(pBtCoex->c2hBtProfile != BT_INFO_HID) +// pBtCoex->c2hBtProfile &= ~BT_INFO_HID; } void BTDM_1AntBtCoexist8723A(PADAPTER padapter) { - struct mlme_priv *pmlmepriv; PHAL_DATA_TYPE pHalData; u32 curr_time, delta_time; - pmlmepriv = &padapter->mlmepriv; pHalData = GET_HAL_DATA(padapter); - if (check_fwstate(pmlmepriv, WIFI_SITE_MONITOR) == _TRUE) + if (BTDM_CheckFWState(padapter, WIFI_SITE_MONITOR) == _TRUE) { // already done in BTDM_1AntForScan() RTPRINT(FBT, BT_TRACE, ("[BTCoex], wifi is under scan progress!!\n")); return; } - if (check_fwstate(pmlmepriv, WIFI_UNDER_LINKING) == _TRUE) + if (BTDM_CheckFWState(padapter, WIFI_UNDER_LINKING) == _TRUE) { RTPRINT(FBT, BT_TRACE, ("[BTCoex], wifi is under link progress!!\n")); return; @@ -9721,7 +9846,7 @@ void BTDM_1AntBtCoexist8723A(PADAPTER padapter) // under DHCP(Special packet) curr_time = rtw_get_current_time(); - delta_time = curr_time - padapter->pwrctrlpriv.DelayLPSLastTimeStamp; + delta_time = curr_time - adapter_to_pwrctl(padapter)->DelayLPSLastTimeStamp; delta_time = rtw_systime_to_ms(delta_time); if (delta_time < 500) // 500ms { @@ -10321,8 +10446,8 @@ void btdm_2AntCoexTable( PADAPTER padapter,u32 val0x6c0,u32 val0x6c8,u8 val0x6cc PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); PBTDM_8723A_2ANT pBtdm8723 = &pHalData->bt_coexist.halCoex8723.btdm2Ant; - RTPRINT(FBT, BT_TRACE, ("[BTCoex], write Coex Table 0x6c0=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", - val0x6c0, val0x6c8, val0x6cc)); +// RTPRINT(FBT, BT_TRACE, ("[BTCoex], write Coex Table 0x6c0=0x%x, 0x6c8=0x%x, 0x6cc=0x%x\n", +// val0x6c0, val0x6c8, val0x6cc)); pBtdm8723->curVal0x6c0 = val0x6c0; pBtdm8723->curVal0x6c8 = val0x6c8; pBtdm8723->curVal0x6cc = val0x6cc; @@ -10361,6 +10486,33 @@ void btdm_2AntIgnoreWlanAct(PADAPTER padapter,u8 bEnable) btdm_SetFwIgnoreWlanAct(padapter,bEnable); pBtdm8723->bPreIgnoreWlanAct = pBtdm8723->bCurIgnoreWlanAct; } +void btdm_2AntSetTable(PADAPTER padapter,u8 byte){ + u8 value; + u32 val0x6c0,val0x6c4; + value =(byte&(BIT4|BIT3))>>3; + + switch(value){ + case 0: + val0x6c0=0x55555555; + val0x6c4=0x55555555; + break; + case 1: + val0x6c0=0x55555555; + val0x6c4=0x5afa5afa; + break; + case 2: + val0x6c0=0x55ff55ff; + val0x6c4=0x5a5a5a5a; + break; + case 3: + val0x6c0=0x55ff55ff; + val0x6c4=0x5afa5afa; + break; + } + RTPRINT(FBT, BT_TRACE, ("set coex table, set 0x6c0=0x%x 0x6c4=0x%x\n", val0x6c0, val0x6c4)); + rtw_write32(padapter, 0x6c0, val0x6c0); + rtw_write32(padapter, 0x6c4, val0x6c4); +} void btdm_2AntSetFw3a(PADAPTER padapter,u8 byte1,u8 byte2,u8 byte3,u8 byte4,u8 byte5) { @@ -10391,6 +10543,7 @@ void btdm_2AntSetFw3a(PADAPTER padapter,u8 byte1,u8 byte2,u8 byte3,u8 byte4,u8 H2C_Parameter[1]<<24|H2C_Parameter[2]<<16|H2C_Parameter[3]<<8|H2C_Parameter[4])); FillH2CCmd(padapter, 0x3a, 5, H2C_Parameter); + btdm_2AntSetTable(padapter,byte5); // Driver need to set the Coex Table value after FW version 35. } void btdm_2AntPsTdma(PADAPTER padapter,u8 bTurnOn,u8 type) @@ -10434,64 +10587,64 @@ void btdm_2AntPsTdma(PADAPTER padapter,u8 bTurnOn,u8 type) { case 1: default: - btdm_2AntSetFw3a(padapter, 0xe3, 0x1a, 0x1a, 0xa1, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x1a, 0x1a, 0xe1, 0x98); break; case 2: - btdm_2AntSetFw3a(padapter, 0xe3, 0x12, 0x12, 0xa1, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x12, 0x12, 0xe1, 0x98); break; case 3: - btdm_2AntSetFw3a(padapter, 0xe3, 0xa, 0xa, 0xa1, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0xa, 0xa, 0xe1, 0x98); break; case 4: - btdm_2AntSetFw3a(padapter, 0xa3, 0x5, 0x5, 0xa1, 0x80); + btdm_2AntSetFw3a(padapter, 0xa3, 0x5, 0x5, 0xe1, 0x80); break; case 5: - btdm_2AntSetFw3a(padapter, 0xe3, 0x1a, 0x1a, 0x20, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x1a, 0x1a, 0x60, 0x98); break; case 6: - btdm_2AntSetFw3a(padapter, 0xe3, 0x12, 0x12, 0x20, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x12, 0x12, 0x60, 0x98); break; case 7: - btdm_2AntSetFw3a(padapter, 0xe3, 0xa, 0xa, 0x20, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0xa, 0xa, 0x60, 0x98); break; case 8: - btdm_2AntSetFw3a(padapter, 0xa3, 0x5, 0x5, 0x20, 0x80); + btdm_2AntSetFw3a(padapter, 0xa3, 0x5, 0x5, 0x60, 0x80); break; case 9: - btdm_2AntSetFw3a(padapter, 0xe3, 0x1a, 0x1a, 0xa1, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x1a, 0x1a, 0xe1, 0x98); break; case 10: - btdm_2AntSetFw3a(padapter, 0xe3, 0x12, 0x12, 0xa1, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x12, 0x12, 0xe1, 0x98); break; case 11: - btdm_2AntSetFw3a(padapter, 0xe3, 0xa, 0xa, 0xa1, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0xa, 0xa, 0xe1, 0x98); break; case 12: - btdm_2AntSetFw3a(padapter, 0xe3, 0x5, 0x5, 0xa1, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x5, 0x5, 0xe1, 0x98); break; case 13: - btdm_2AntSetFw3a(padapter, 0xe3, 0x1a, 0x1a, 0x20, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x1a, 0x1a, 0x60, 0x98); break; case 14: - btdm_2AntSetFw3a(padapter, 0xe3, 0x12, 0x12, 0x20, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x12, 0x12, 0x60, 0x98); break; case 15: - btdm_2AntSetFw3a(padapter, 0xe3, 0xa, 0xa, 0x20, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0xa, 0xa, 0x60, 0x98); break; case 16: - btdm_2AntSetFw3a(padapter, 0xe3, 0x5, 0x5, 0x20, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x5, 0x5, 0x60, 0x98); break; case 17: - btdm_2AntSetFw3a(padapter, 0xa3, 0x2f, 0x2f, 0x20, 0x80); + btdm_2AntSetFw3a(padapter, 0xa3, 0x2f, 0x2f, 0x60, 0x80); break; case 18: - btdm_2AntSetFw3a(padapter, 0xe3, 0x5, 0x5, 0xa1, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x5, 0x5, 0xe1, 0x98); break; case 19: - btdm_2AntSetFw3a(padapter, 0xe3, 0x25, 0x25, 0xa1, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x25, 0x25, 0xe1, 0x98); break; case 20: - btdm_2AntSetFw3a(padapter, 0xe3, 0x25, 0x25, 0x20, 0x98); + btdm_2AntSetFw3a(padapter, 0xe3, 0x25, 0x25, 0x60, 0x98); break; } } @@ -10572,11 +10725,11 @@ u8 btdm_Is2Ant8723ACommonAction(PADAPTER padapter) PBTDM_8723A_2ANT pBtdm8723 = &pHalData->bt_coexist.halCoex8723.btdm2Ant; u8 bCommon=_FALSE; - RTPRINT(FBT, BT_TRACE, ("%s :BTDM_IsWifiConnectionExist =%x check_fwstate=%x pmlmepriv->fw_state=0x%x\n",__func__,BTDM_IsWifiConnectionExist(padapter),check_fwstate(&padapter->mlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING)),padapter->mlmepriv.fw_state)); + RTPRINT(FBT, BT_TRACE, ("%s :BTDM_IsWifiConnectionExist =%x BTDM_CheckFWState=%x pmlmepriv->fw_state=0x%x\n",__func__,BTDM_IsWifiConnectionExist(padapter),BTDM_CheckFWState(padapter, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING)),padapter->mlmepriv.fw_state)); // if(!BTDM_IsWifiBusy(padapter) && - if((BTDM_IsWifiConnectionExist(padapter) == _FALSE)&&(check_fwstate(&padapter->mlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _FALSE)&& + if((BTDM_IsWifiConnectionExist(padapter) == _FALSE)&&(BTDM_CheckFWState(padapter, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _FALSE)&& (BT_2ANT_BT_STATUS_IDLE == pBtdm8723->btStatus) ) { RTPRINT(FBT, BT_TRACE, ("Wifi idle + Bt idle!!\n")); @@ -10597,7 +10750,7 @@ u8 btdm_Is2Ant8723ACommonAction(PADAPTER padapter) bCommon = _TRUE; } // else if( BTDM_IsWifiBusy(padapter) && - else if(((BTDM_IsWifiConnectionExist(padapter) == _TRUE)||(check_fwstate(&padapter->mlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _TRUE))&& + else if(((BTDM_IsWifiConnectionExist(padapter) == _TRUE)||(BTDM_CheckFWState(padapter, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _TRUE))&& (BT_2ANT_BT_STATUS_IDLE == pBtdm8723->btStatus) ) { RTPRINT(FBT, BT_TRACE, ("Wifi non-idle + BT idle!!\n")); @@ -10618,7 +10771,7 @@ u8 btdm_Is2Ant8723ACommonAction(PADAPTER padapter) bCommon = _TRUE; } // else if(!BTDM_IsWifiBusy(padapter) && - else if((BTDM_IsWifiConnectionExist(padapter) == _FALSE)&&(check_fwstate(&padapter->mlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _FALSE)&& + else if((BTDM_IsWifiConnectionExist(padapter) == _FALSE)&&(BTDM_CheckFWState(padapter, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _FALSE)&& (BT_2ANT_BT_STATUS_CONNECTED_IDLE == pBtdm8723->btStatus) ) { RTPRINT(FBT, BT_TRACE, ("Wifi idle + Bt connected idle!!\n")); @@ -10639,7 +10792,7 @@ u8 btdm_Is2Ant8723ACommonAction(PADAPTER padapter) bCommon = _TRUE; } // else if(BTDM_IsWifiBusy(padapter) && - else if(((BTDM_IsWifiConnectionExist(padapter) == _TRUE)||(check_fwstate(&padapter->mlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _TRUE))&& + else if(((BTDM_IsWifiConnectionExist(padapter) == _TRUE)||(BTDM_CheckFWState(padapter, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _TRUE))&& (BT_2ANT_BT_STATUS_CONNECTED_IDLE == pBtdm8723->btStatus) ) { RTPRINT(FBT, BT_TRACE, ("Wifi non-idle + Bt connected idle!!\n")); @@ -10660,7 +10813,7 @@ u8 btdm_Is2Ant8723ACommonAction(PADAPTER padapter) bCommon = _TRUE; } // else if(!BTDM_IsWifiBusy(padapter) && - else if((BTDM_IsWifiConnectionExist(padapter) == _FALSE)&&(check_fwstate(&padapter->mlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _FALSE)&& + else if((BTDM_IsWifiConnectionExist(padapter) == _FALSE)&&(BTDM_CheckFWState(padapter, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _FALSE)&& (BT_2ANT_BT_STATUS_NON_IDLE == pBtdm8723->btStatus) ) { RTPRINT(FBT, BT_TRACE, ("Wifi idle + BT non-idle!!\n")); @@ -11573,7 +11726,7 @@ void btdm_2AntTdmaDurationAdjust(PADAPTER padapter,u8 bScoHid,u8 bTxPause,u8 RTPRINT(FBT, BT_TRACE, ("[BTCoex], PsTdma type dismatch!!!, curPsTdma=%d, recordPsTdma=%d\n", pBtdm8723->curPsTdma, pBtdm8723->psTdmaDuAdjType)); - if( check_fwstate(&padapter->mlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _FALSE ) + if( BTDM_CheckFWState(padapter, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _FALSE ) { btdm_2AntPsTdma(padapter, _TRUE, pBtdm8723->psTdmaDuAdjType); } @@ -13362,6 +13515,22 @@ u8 btdm_BtWifiAntNum(PADAPTER padapter) return Ant_x2; } +u8 btdm_GetBtState(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PBT_COEXIST_8723A pBtCoex = &pHalData->bt_coexist.halCoex8723; + + return pBtCoex->c2hBtInfo; +} + +u8 btdm_IsBtInquiryPage(PADAPTER padapter) +{ + PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); + PBT_COEXIST_8723A pBtCoex = &pHalData->bt_coexist.halCoex8723; + + return pBtCoex->bC2hBtInquiryPage; +} + void btdm_BtHwCountersMonitor(PADAPTER padapter) { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); @@ -13580,7 +13749,7 @@ void BTDM_SetFwChnlInfo(PADAPTER padapter, RT_MEDIA_STATUS mstatus) H2C_Parameter[0] = 0x1; // 0: disconnected, 1:connected } - if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) + if (BTDM_CheckFWState(padapter, WIFI_ASOC_STATE) == _TRUE) { // channel chnl = pmlmeext->cur_channel; @@ -13619,7 +13788,10 @@ void BTDM_SetFwChnlInfo(PADAPTER padapter, RT_MEDIA_STATUS mstatus) // RTPRINT(FBT, BT_TRACE, ("[BTCoex], FW write 0x19=0x%x\n", // H2C_Parameter[0]<<16|H2C_Parameter[1]<<8|H2C_Parameter[2])); - FillH2CCmd(padapter, 0x19, 3, H2C_Parameter); + if (btdm_BtWifiAntNum(padapter) == Ant_x2) + { + FillH2CCmd(padapter, 0x19, 3, H2C_Parameter); + } } u8 BTDM_IsWifiConnectionExist(PADAPTER padapter) @@ -13630,8 +13802,21 @@ u8 BTDM_IsWifiConnectionExist(PADAPTER padapter) if (BTHCI_HsConnectionEstablished(padapter)) bRet = _TRUE; - if (check_fwstate(&padapter->mlmepriv, WIFI_ASOC_STATE) == _TRUE) +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->pbuddy_adapter != NULL) + { + if ((BTDM_CheckFWState(padapter, WIFI_ASOC_STATE) == _TRUE) || (BTDM_CheckFWState(padapter->pbuddy_adapter, WIFI_ASOC_STATE) == _TRUE)) + bRet = _TRUE; + } + else + { + if (BTDM_CheckFWState(padapter, WIFI_ASOC_STATE) == _TRUE) + bRet = _TRUE; + } +#else + if (BTDM_CheckFWState(padapter, WIFI_ASOC_STATE) == _TRUE) bRet = _TRUE; +#endif return bRet; } @@ -13649,7 +13834,7 @@ void BTDM_SetFw3a( if (BTDM_1Ant8723A(padapter) == _TRUE) { - if ((check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == _FALSE) && + if ((BTDM_CheckFWState(padapter, WIFI_STATION_STATE) == _FALSE) && (get_fwstate(&padapter->mlmepriv) != WIFI_NULL_STATE)) // for softap mode { PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); @@ -13859,6 +14044,7 @@ void BTDM_FwC2hBtInfo8723A(PADAPTER padapter, u8 *tmpBuf, u8 length) RTPRINT(FBT, BT_TRACE, ("[BTC2H], BT info[%d]=[", length)); pBtCoex->btRetryCnt = 0; + pBtCoex->AclTp=0; for (i=0; i<length; i++) { switch (i) @@ -13873,8 +14059,14 @@ void BTDM_FwC2hBtInfo8723A(PADAPTER padapter, u8 *tmpBuf, u8 length) BTDM_FwC2hBtRssi8723A(padapter, &tmpBuf[i]); break; case 3: - pBtCoex->btInfoExt=tmpBuf[i]&BIT(0); + pBtCoex->btInfoExt=tmpBuf[i]&BIT(0); //EDR_BR break; + case 4: + pBtCoex->AclTp=tmpBuf[i]; + break; + case 5: + pBtCoex->AclTp |=(tmpBuf[i]<<8); + break; } if (i == length-1) @@ -14328,6 +14520,16 @@ void BTDM_BTCoexist8723A(PADAPTER padapter) BTDM_QueryBtInformation(padapter); } +u8 BTDM_GetBtState8723A(PADAPTER padapter) +{ + return btdm_GetBtState(padapter); +} + +u8 BTDM_IsBtInquiryPage8723A(PADAPTER padapter) +{ + return btdm_IsBtInquiryPage(padapter); +} + // ===== End of sync from SD7 driver HAL/BTCoexist/HalBtc8723.c ===== #endif @@ -15239,7 +15441,7 @@ void BTDM_CheckBTIdleChange1Ant(PADAPTER padapter) MgntIsLinkInProgress(pMgntInfo) || MgntScanInProgress(pMgntInfo)) #else - if (check_fwstate(&padapter->mlmepriv, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _TRUE) + if (BTDM_CheckFWState(padapter, WIFI_UNDER_LINKING|WIFI_SITE_MONITOR) == _TRUE) #endif { BTDM_SetAntenna(padapter, BTDM_ANT_WIFI); @@ -18164,16 +18366,14 @@ void BTDM_CheckWiFiState(PADAPTER padapter) s32 BTDM_GetRxSS(PADAPTER padapter) { // PMGNT_INFO pMgntInfo = &padapter->MgntInfo; - struct mlme_priv *pmlmepriv; PHAL_DATA_TYPE pHalData; s32 UndecoratedSmoothedPWDB = 0; - pmlmepriv = &padapter->mlmepriv; pHalData = GET_HAL_DATA(padapter); // if (pMgntInfo->bMediaConnect) // Default port - if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + if (BTDM_CheckFWState(padapter, _FW_LINKED) == _TRUE) { UndecoratedSmoothedPWDB = GET_UNDECORATED_AVERAGE_RSSI(padapter); } @@ -18189,16 +18389,14 @@ s32 BTDM_GetRxSS(PADAPTER padapter) s32 BTDM_GetRxBeaconSS(PADAPTER padapter) { // PMGNT_INFO pMgntInfo = &padapter->MgntInfo; - struct mlme_priv *pmlmepriv; PHAL_DATA_TYPE pHalData; s32 pwdbBeacon = 0; - pmlmepriv = &padapter->mlmepriv; pHalData = GET_HAL_DATA(padapter); // if (pMgntInfo->bMediaConnect) // Default port - if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) + if (BTDM_CheckFWState(padapter, _FW_LINKED) == _TRUE) { //pwdbBeacon = pHalData->dmpriv.UndecoratedSmoothedBeacon; pwdbBeacon= pHalData->dmpriv.EntryMinUndecoratedSmoothedPWDB; @@ -18666,7 +18864,7 @@ u8 BTDM_DisableEDCATurbo(PADAPTER padapter) if ((pHalData->bt_coexist.last_aggr_num != aggr_num) || !pHalData->bt_coexist.bEDCAInitialized) { RTPRINT(FBT, BT_TRACE, ("BT write AGGR NUM = 0x%x\n", aggr_num)); - rtw_write16(padapter, REG_MAX_AGGR_NUM, aggr_num); + rtw_write8(padapter, REG_MAX_AGGR_NUM, aggr_num); pHalData->bt_coexist.last_aggr_num = aggr_num; } } @@ -18893,7 +19091,7 @@ void BTDM_TurnOffBtCoexistBeforeEnterLPS(PADAPTER padapter) PBT_MGNT pBtMgnt = &pBTInfo->BtMgnt; PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); // PRT_POWER_SAVE_CONTROL pPSC = GET_POWER_SAVE_CONTROL(pMgntInfo); - struct pwrctrl_priv *ppwrctrl = &padapter->pwrctrlpriv; + struct pwrctrl_priv *ppwrctrl = adapter_to_pwrctl(padapter); // Add temporarily. @@ -18928,7 +19126,7 @@ void BTDM_TurnOffBtCoexistBeforeEnterIPS(PADAPTER padapter) PBT_MGNT pBtMgnt = &pBTInfo->BtMgnt; PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); // PRT_POWER_SAVE_CONTROL pPSC = GET_POWER_SAVE_CONTROL(pMgntInfo); - struct pwrctrl_priv *ppwrctrl = &padapter->pwrctrlpriv; + struct pwrctrl_priv *ppwrctrl = adapter_to_pwrctl(padapter); if (!pHalData->bt_coexist.BluetoothCoexist) return; @@ -19008,6 +19206,9 @@ void dm_CheckBTState(_adapter *pAdapter) rtw_write8(pAdapter, 0xf6, value); rtw_write8(pAdapter, 0x3A, 0x31); } + else{ + return; + } regvalue32 = rtw_read32(pAdapter, 0xc0); //DBG_871X("Get 0xc0 = 0x%x\n",regvalue32); @@ -19016,6 +19217,9 @@ void dm_CheckBTState(_adapter *pAdapter) value |= 0x4; rtw_write8(pAdapter, 0xcc, value); } + else{ + return; + } regValue8 = rtw_read8(pAdapter, 0x6b); //0x6b[28] //DBG_871X("Get 0x6b = 0x%x\n",regValue8); @@ -19042,6 +19246,7 @@ void check_bt_status_work(void *data) { struct delayed_work *dwork; PADAPTER padapter; + struct pwrctrl_priv *pwrpriv ; dwork = container_of(data, struct delayed_work, work); padapter = container_of(dwork, struct _ADAPTER, checkbt_work); @@ -19051,7 +19256,9 @@ void check_bt_status_work(void *data) return; }; - dm_CheckBTState(padapter); + pwrpriv = adapter_to_pwrctl(padapter); + if (pwrpriv->bInSuspend == _FALSE) + dm_CheckBTState(padapter); } #endif void BTDM_Coexist(PADAPTER padapter) @@ -19261,8 +19468,33 @@ u8 BTDM_IsWifiBusy(PADAPTER padapter) PBT30Info pBTInfo = GET_BT_INFO(padapter); PBT_TRAFFIC pBtTraffic = &pBTInfo->BtTraffic; +#ifdef CONFIG_CONCURRENT_MODE + struct mlme_priv *pbuddy_mlmepriv; + + if (padapter->pbuddy_adapter != NULL) + { + pbuddy_mlmepriv = &(padapter->pbuddy_adapter->mlmepriv); + +#if 1 + if ((btdm_BtWifiAntNum(padapter) == Ant_x1) && ((BT_IsBtDisabled(padapter) == _TRUE) || ((BT_IsBtDisabled(padapter) == _FALSE && (BT_GetBtState(padapter) <= BT_INFO_STATE_CONNECT_IDLE))))) + { + if (((padapter->iface_type == IFACE_PORT0) && (check_fwstate(pbuddy_mlmepriv, _FW_LINKED) == _TRUE)) || + ((padapter->iface_type == IFACE_PORT1) && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE))) + return _TRUE; + } +#endif + + if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > WIFI_BUSY_TRAFFIC_TH ||pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > WIFI_BUSY_TRAFFIC_TH || + pbuddy_mlmepriv->LinkDetectInfo.NumRxOkInPeriod > WIFI_BUSY_TRAFFIC_TH || pbuddy_mlmepriv->LinkDetectInfo.NumTxOkInPeriod > WIFI_BUSY_TRAFFIC_TH || + pBtTraffic->Bt30TrafficStatistics.bTxBusyTraffic || + pBtTraffic->Bt30TrafficStatistics.bRxBusyTraffic) + return _TRUE; + else + return _FALSE; + } +#endif - if (pmlmepriv->LinkDetectInfo.bBusyTraffic || + if (pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > WIFI_BUSY_TRAFFIC_TH ||pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > WIFI_BUSY_TRAFFIC_TH || pBtTraffic->Bt30TrafficStatistics.bTxBusyTraffic || pBtTraffic->Bt30TrafficStatistics.bRxBusyTraffic) return _TRUE; @@ -19707,6 +19939,25 @@ u8 BTDM_IsBtDisabled(PADAPTER padapter) return _FALSE; } +sint BTDM_CheckFWState(PADAPTER padapter, sint state) +{ + if (check_fwstate(&padapter->mlmepriv, state) == _FALSE) + { +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->pbuddy_adapter != NULL) + { + if (check_fwstate(&padapter->pbuddy_adapter->mlmepriv, state) == _TRUE) + { + return _TRUE; + } + } +#endif + return _FALSE; + } + + return _TRUE; +} + //============================================ // Started with "WA_" means this is a work around function. // Because fw need to count bt HW counters diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_cmd.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_cmd.c index ce088bc86590..47e8c631f46f 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_cmd.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_cmd.c @@ -1,1159 +1,1185 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#define _RTL8723A_CMD_C_ - -#include <drv_conf.h> -#include <osdep_service.h> -#include <drv_types.h> -#include <recv_osdep.h> -#include <cmd_osdep.h> -#include <mlme_osdep.h> -#include <rtw_byteorder.h> -#include <circ_buf.h> -#include <rtw_ioctl_set.h> - -#include <rtl8723a_hal.h> - - -#define RTL92C_MAX_H2C_BOX_NUMS 4 -#define RTL92C_MAX_CMD_LEN 5 -#define MESSAGE_BOX_SIZE 4 -#define EX_MESSAGE_BOX_SIZE 2 - - -static u8 _is_fw_read_cmd_down(_adapter* padapter, u8 msgbox_num) -{ - u8 read_down = _FALSE; - int retry_cnts = 100; - - u8 valid; - - //DBG_8192C(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num); - - do{ - valid = rtw_read8(padapter,REG_HMETFR) & BIT(msgbox_num); - if(0 == valid ){ - read_down = _TRUE; - } - }while( (!read_down) && (retry_cnts--)); - - return read_down; - -} - - -/***************************************** -* H2C Msg format : -*| 31 - 8 |7 | 6 - 0 | -*| h2c_msg |Ext_bit |CMD_ID | -* -******************************************/ -s32 FillH2CCmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer) -{ - u8 bcmd_down = _FALSE; - s32 retry_cnts = 100; - u8 h2c_box_num; - u32 msgbox_addr; - u32 msgbox_ex_addr; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - u32 h2c_cmd = 0; - u16 h2c_cmd_ex = 0; - s32 ret = _FAIL; - -_func_enter_; - - padapter = GET_PRIMARY_ADAPTER(padapter); - pHalData = GET_HAL_DATA(padapter); - - _enter_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL); - - if (!pCmdBuffer) { - goto exit; - } - if (CmdLen > RTL92C_MAX_CMD_LEN) { - goto exit; - } - if (padapter->bSurpriseRemoved == _TRUE) - goto exit; - - //pay attention to if race condition happened in H2C cmd setting. - do{ - h2c_box_num = pHalData->LastHMEBoxNum; - - if(!_is_fw_read_cmd_down(padapter, h2c_box_num)){ - DBG_8192C(" fw read cmd failed...\n"); - goto exit; - } - - if(CmdLen<=3) - { - _rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer, CmdLen ); - } - else{ - _rtw_memcpy((u8*)(&h2c_cmd_ex), pCmdBuffer, EX_MESSAGE_BOX_SIZE); - _rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer+2,( CmdLen-EX_MESSAGE_BOX_SIZE)); - *(u8*)(&h2c_cmd) |= BIT(7); - } - - *(u8*)(&h2c_cmd) |= ElementID; - - if(h2c_cmd & BIT(7)){ - msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num *EX_MESSAGE_BOX_SIZE); - h2c_cmd_ex = le16_to_cpu( h2c_cmd_ex ); - rtw_write16(padapter, msgbox_ex_addr, h2c_cmd_ex); - } - msgbox_addr =REG_HMEBOX_0 + (h2c_box_num *MESSAGE_BOX_SIZE); - h2c_cmd = le32_to_cpu( h2c_cmd ); - rtw_write32(padapter,msgbox_addr, h2c_cmd); - - bcmd_down = _TRUE; - - // DBG_8192C("MSG_BOX:%d,CmdLen(%d), reg:0x%x =>h2c_cmd:0x%x, reg:0x%x =>h2c_cmd_ex:0x%x ..\n" - // ,pHalData->LastHMEBoxNum ,CmdLen,msgbox_addr,h2c_cmd,msgbox_ex_addr,h2c_cmd_ex); - - pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL92C_MAX_H2C_BOX_NUMS; - - }while((!bcmd_down) && (retry_cnts--)); - - ret = _SUCCESS; - -exit: - - _exit_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL); - -_func_exit_; - - return ret; -} - -u8 rtl8192c_h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf) -{ - u8 ElementID, CmdLen; - u8 *pCmdBuffer; - struct cmd_msg_parm *pcmdmsg; - - if(!pbuf) - return H2C_PARAMETERS_ERROR; - - pcmdmsg = (struct cmd_msg_parm*)pbuf; - ElementID = pcmdmsg->eid; - CmdLen = pcmdmsg->sz; - pCmdBuffer = pcmdmsg->buf; - - FillH2CCmd(padapter, ElementID, CmdLen, pCmdBuffer); - - return H2C_SUCCESS; -} - -#if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED) -u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter *padapter ,u8 bfwpoll, u16 period) -{ - u8 res=_SUCCESS; - struct H2C_SS_RFOFF_PARAM param; - DBG_8192C("==>%s bfwpoll(%x)\n",__FUNCTION__,bfwpoll); - param.gpio_period = period;//Polling GPIO_11 period time - param.ROFOn = (_TRUE == bfwpoll)?1:0; - FillH2CCmd(padapter, SELECTIVE_SUSPEND_ROF_CMD, sizeof(param), (u8*)(¶m)); - return res; -} -#endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED - -u8 rtl8192c_set_rssi_cmd(_adapter*padapter, u8 *param) -{ - u8 res=_SUCCESS; - -_func_enter_; - - *((u32*) param ) = cpu_to_le32( *((u32*) param ) ); - - FillH2CCmd(padapter, RSSI_SETTING_EID, 3, param); - -_func_exit_; - - return res; -} - -u8 rtl8192c_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg) -{ - u8 buf[5]; - u8 res=_SUCCESS; - -_func_enter_; - - _rtw_memset(buf, 0, 5); - mask = cpu_to_le32( mask ); - _rtw_memcpy(buf, &mask, 4); - buf[4] = arg; - - FillH2CCmd(padapter, MACID_CONFIG_EID, 5, buf); - -_func_exit_; - - return res; - -} - -//bitmap[0:27] = tx_rate_bitmap -//bitmap[28:31]= Rate Adaptive id -//arg[0:4] = macid -//arg[5] = Short GI -void rtl8192c_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 rssi_level) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - u8 macid = arg&0x1f; - -#ifdef CONFIG_ODM_REFRESH_RAMASK - u8 raid = (bitmap>>28) & 0x0f; - -#ifdef CONFIG_CONCURRENT_MODE - if(rtw_buddy_adapter_up(pAdapter) && pAdapter->adapter_type > PRIMARY_ADAPTER) - pHalData = GET_HAL_DATA(pAdapter->pbuddy_adapter); -#endif //CONFIG_CONCURRENT_MODE - - bitmap &=0x0fffffff; - if(rssi_level != DM_RATR_STA_INIT) - bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, macid, bitmap, rssi_level); - - bitmap |= ((raid<<28)&0xf0000000); -#endif //CONFIG_ODM_REFRESH_RAMASK - - - if(pHalData->fw_ractrl == _TRUE) - { - rtl8192c_set_raid_cmd(pAdapter, bitmap, arg); - } - else - { - u8 init_rate, shortGIrate=_FALSE; - - init_rate = get_highest_rate_idx(bitmap&0x0fffffff)&0x3f; - - - shortGIrate = (arg&BIT(5)) ? _TRUE:_FALSE; - - if (shortGIrate==_TRUE) - init_rate |= BIT(6); - - rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate); - } - -} - -void rtl8723a_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode) -{ - SETPWRMODE_PARM H2CSetPwrMode; - struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; - -_func_enter_; - - DBG_871X("%s: Mode=%d SmartPS=%d UAPSD=%d BcnMode=0x%02x\n", __FUNCTION__, - Mode, pwrpriv->smart_ps, padapter->registrypriv.uapsd_enable, pwrpriv->bcn_ant_mode); - - H2CSetPwrMode.Mode = Mode; - H2CSetPwrMode.SmartPS = pwrpriv->smart_ps; - H2CSetPwrMode.AwakeInterval = 1; - H2CSetPwrMode.bAllQueueUAPSD = padapter->registrypriv.uapsd_enable; - H2CSetPwrMode.BcnAntMode = pwrpriv->bcn_ant_mode; - - FillH2CCmd(padapter, SET_PWRMODE_EID, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode); - -_func_exit_; -} - -void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u32 rate_len, pktlen; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; - - - //DBG_871X("%s\n", __FUNCTION__); - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - - _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); - - SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); - //pmlmeext->mgnt_seq++; - SetFrameSubType(pframe, WIFI_BEACON); - - pframe += sizeof(struct rtw_ieee80211_hdr_3addr); - pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); - - //timestamp will be inserted by hardware - pframe += 8; - pktlen += 8; - - // beacon interval: 2 bytes - _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); - - pframe += 2; - pktlen += 2; - - // capability info: 2 bytes - _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); - - pframe += 2; - pktlen += 2; - - if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) - { - //DBG_871X("ie len=%d\n", cur_network->IELength); - pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs); - _rtw_memcpy(pframe, cur_network->IEs+sizeof(NDIS_802_11_FIXED_IEs), pktlen); - - goto _ConstructBeacon; - } - - //below for ad-hoc mode - - // SSID - pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen); - - // supported rates... - rate_len = rtw_get_rateset_len(cur_network->SupportedRates); - pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pktlen); - - // DS parameter set - pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen); - - if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) - { - u32 ATIMWindow; - // IBSS Parameter Set... - //ATIMWindow = cur->Configuration.ATIMWindow; - ATIMWindow = 0; - pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen); - } - - - //todo: ERP IE - - - // EXTERNDED SUPPORTED RATE - if (rate_len > 8) - { - pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); - } - - - //todo:HT for adhoc - -_ConstructBeacon: - - if ((pktlen + TXDESC_SIZE) > 512) - { - DBG_871X("beacon frame too large\n"); - return; - } - - *pLength = pktlen; - - //DBG_871X("%s bcn_sz=%d\n", __FUNCTION__, pktlen); - -} - -void ConstructPSPoll(_adapter *padapter, u8 *pframe, u32 *pLength) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u32 pktlen; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - //DBG_871X("%s\n", __FUNCTION__); - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - // Frame control. - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - SetPwrMgt(fctrl); - SetFrameSubType(pframe, WIFI_PSPOLL); - - // AID. - SetDuration(pframe, (pmlmeinfo->aid | 0xc000)); - - // BSSID. - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - - // TA. - _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); - - *pLength = 16; -} - -void ConstructNullFunctionData( - PADAPTER padapter, - u8 *pframe, - u32 *pLength, - u8 *StaAddr, - u8 bQoS, - u8 AC, - u8 bEosp, - u8 bForcePowerSave) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u32 pktlen; - struct mlme_priv *pmlmepriv = &padapter->mlmepriv; - struct wlan_network *cur_network = &pmlmepriv->cur_network; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - - - //DBG_871X("%s:%d\n", __FUNCTION__, bForcePowerSave); - - pwlanhdr = (struct rtw_ieee80211_hdr*)pframe; - - fctrl = &pwlanhdr->frame_ctl; - *(fctrl) = 0; - if (bForcePowerSave) - { - SetPwrMgt(fctrl); - } - - switch(cur_network->network.InfrastructureMode) - { - case Ndis802_11Infrastructure: - SetToDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN); - break; - case Ndis802_11APMode: - SetFrDs(fctrl); - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); - break; - case Ndis802_11IBSS: - default: - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); - break; - } - - SetSeqNum(pwlanhdr, 0); - - if (bQoS == _TRUE) { - struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr; - - SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); - - pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos*)pframe; - SetPriority(&pwlanqoshdr->qc, AC); - SetEOSP(&pwlanqoshdr->qc, bEosp); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); - } else { - SetFrameSubType(pframe, WIFI_DATA_NULL); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - } - - *pLength = pktlen; -} - -void ConstructProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *StaAddr, BOOLEAN bHideSSID) -{ - struct rtw_ieee80211_hdr *pwlanhdr; - u16 *fctrl; - u8 *mac, *bssid; - u32 pktlen; - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); - - - //DBG_871X("%s\n", __FUNCTION__); - - pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; - - mac = myid(&(padapter->eeprompriv)); - bssid = cur_network->MacAddress; - - fctrl = &(pwlanhdr->frame_ctl); - *(fctrl) = 0; - _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); - _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); - - SetSeqNum(pwlanhdr, 0); - SetFrameSubType(fctrl, WIFI_PROBERSP); - - pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); - pframe += pktlen; - - if(cur_network->IELength>MAX_IE_SZ) - return; - - _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); - pframe += cur_network->IELength; - pktlen += cur_network->IELength; - - *pLength = pktlen; -} - -// To check if reserved page content is destroyed by beacon beacuse beacon is too large. -// 2010.06.23. Added by tynli. -VOID -CheckFwRsvdPageContent( - IN PADAPTER Adapter -) -{ - HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter); - u32 MaxBcnPageNum; - - if(pHalData->FwRsvdPageStartOffset != 0) - { - /*MaxBcnPageNum = PageNum_128(pMgntInfo->MaxBeaconSize); - RT_ASSERT((MaxBcnPageNum <= pHalData->FwRsvdPageStartOffset), - ("CheckFwRsvdPageContent(): The reserved page content has been"\ - "destroyed by beacon!!! MaxBcnPageNum(%d) FwRsvdPageStartOffset(%d)\n!", - MaxBcnPageNum, pHalData->FwRsvdPageStartOffset));*/ - } -} - -// -// Description: Fill the reserved packets that FW will use to RSVD page. -// Now we just send 4 types packet to rsvd page. -// (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. -// Input: -// bDLFinished - FALSE: At the first time we will send all the packets as a large packet to Hw, -// so we need to set the packet length to total lengh. -// TRUE: At the second time, we should send the first packet (default:beacon) -// to Hw again and set the lengh in descriptor to the real beacon lengh. -// 2009.10.15 by tynli. -static void SetFwRsvdPagePkt(PADAPTER padapter, BOOLEAN bDLFinished) -{ - PHAL_DATA_TYPE pHalData; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - struct xmit_priv *pxmitpriv; - struct mlme_ext_priv *pmlmeext; - struct mlme_ext_info *pmlmeinfo; - u32 BeaconLength, ProbeRspLength, PSPollLength; - u32 NullDataLength, QosNullLength, BTQosNullLength; - u8 *ReservedPagePacket; - u8 PageNum, PageNeed, TxDescLen; - u16 BufIndex; - u32 TotalPacketLen; - RSVDPAGE_LOC RsvdPageLoc; - - - DBG_871X("%s\n", __FUNCTION__); - - ReservedPagePacket = (u8*)rtw_zmalloc(1000); - if (ReservedPagePacket == NULL) { - DBG_871X("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); - return; - } - - pHalData = GET_HAL_DATA(padapter); - pxmitpriv = &padapter->xmitpriv; - pmlmeext = &padapter->mlmeextpriv; - pmlmeinfo = &pmlmeext->mlmext_info; - - TxDescLen = TXDESC_SIZE; - PageNum = 0; - - //3 (1) beacon - BufIndex = TXDESC_OFFSET; - ConstructBeacon(padapter, &ReservedPagePacket[BufIndex], &BeaconLength); - - // When we count the first page size, we need to reserve description size for the RSVD - // packet, it will be filled in front of the packet in TXPKTBUF. - PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength); - // To reserved 2 pages for beacon buffer. 2010.06.24. - if (PageNeed == 1) - PageNeed += 1; - PageNum += PageNeed; - pHalData->FwRsvdPageStartOffset = PageNum; - - BufIndex += PageNeed*128; - - //3 (2) ps-poll - RsvdPageLoc.LocPsPoll = PageNum; - ConstructPSPoll(padapter, &ReservedPagePacket[BufIndex], &PSPollLength); - rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, _TRUE, _FALSE); - - PageNeed = (u8)PageNum_128(TxDescLen + PSPollLength); - PageNum += PageNeed; - - BufIndex += PageNeed*128; - - //3 (3) null data - RsvdPageLoc.LocNullData = PageNum; - ConstructNullFunctionData( - padapter, - &ReservedPagePacket[BufIndex], - &NullDataLength, - get_my_bssid(&pmlmeinfo->network), - _FALSE, 0, 0, _FALSE); - rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], NullDataLength, _FALSE, _FALSE); - - PageNeed = (u8)PageNum_128(TxDescLen + NullDataLength); - PageNum += PageNeed; - - BufIndex += PageNeed*128; - - //3 (4) probe response - RsvdPageLoc.LocProbeRsp = PageNum; - ConstructProbeRsp( - padapter, - &ReservedPagePacket[BufIndex], - &ProbeRspLength, - get_my_bssid(&pmlmeinfo->network), - _FALSE); - rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], ProbeRspLength, _FALSE, _FALSE); - - PageNeed = (u8)PageNum_128(TxDescLen + ProbeRspLength); - PageNum += PageNeed; - - BufIndex += PageNeed*128; - - //3 (5) Qos null data - RsvdPageLoc.LocQosNull = PageNum; - ConstructNullFunctionData( - padapter, - &ReservedPagePacket[BufIndex], - &QosNullLength, - get_my_bssid(&pmlmeinfo->network), - _TRUE, 0, 0, _FALSE); - rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], QosNullLength, _FALSE, _FALSE); - - PageNeed = (u8)PageNum_128(TxDescLen + QosNullLength); - PageNum += PageNeed; - - BufIndex += PageNeed*128; - - //3 (6) BT Qos null data - RsvdPageLoc.LocBTQosNull = PageNum; - ConstructNullFunctionData( - padapter, - &ReservedPagePacket[BufIndex], - &BTQosNullLength, - get_my_bssid(&pmlmeinfo->network), - _TRUE, 0, 0, _FALSE); - rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], BTQosNullLength, _FALSE, _TRUE); - - TotalPacketLen = BufIndex + BTQosNullLength; - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - goto exit; - - // update attribute - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - pattrib->qsel = 0x10; - pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TXDESC_OFFSET; - _rtw_memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen); - - rtw_hal_mgnt_xmit(padapter, pmgntframe); - - DBG_871X("%s: Set RSVD page location to Fw\n", __FUNCTION__); - FillH2CCmd(padapter, RSVD_PAGE_EID, sizeof(RsvdPageLoc), (u8*)&RsvdPageLoc); - -exit: - rtw_mfree(ReservedPagePacket, 1000); -} - -void rtl8723a_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus) -{ - JOINBSSRPT_PARM JoinBssRptParm; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); - struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); - -_func_enter_; - - DBG_871X("%s mstatus(%x)\n", __FUNCTION__,mstatus); - - if(mstatus == 1) - { - BOOLEAN bRecover = _FALSE; - u8 v8; - - // We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. - // Suggested by filen. Added by tynli. - rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid)); - // Do not set TSF again here or vWiFi beacon DMA INT will not work. - //correct_TSF(padapter, pmlmeext); - // Hw sequende enable by dedault. 2010.06.23. by tynli. - //rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF)); - //rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); - - // set REG_CR bit 8 - v8 = rtw_read8(padapter, REG_CR+1); - v8 |= BIT(0); // ENSWBCN - rtw_write8(padapter, REG_CR+1, v8); - - // Disable Hw protection for a time which revserd for Hw sending beacon. - // Fix download reserved page packet fail that access collision with the protection time. - // 2010.05.11. Added by tynli. -// SetBcnCtrlReg(padapter, 0, BIT(3)); -// SetBcnCtrlReg(padapter, BIT(4), 0); - SetBcnCtrlReg(padapter, BIT(4), BIT(3)); - - // Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. - if (pHalData->RegFwHwTxQCtrl & BIT(6)) - bRecover = _TRUE; - - // To tell Hw the packet is not a real beacon frame. - //U1bTmp = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2); - rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl & ~BIT(6)); - pHalData->RegFwHwTxQCtrl &= ~BIT(6); - SetFwRsvdPagePkt(padapter, 0); - - // 2010.05.11. Added by tynli. -// SetBcnCtrlReg(padapter, BIT3, 0); -// SetBcnCtrlReg(padapter, 0, BIT4); - SetBcnCtrlReg(padapter, BIT(3), BIT(4)); - - // To make sure that if there exists an adapter which would like to send beacon. - // If exists, the origianl value of 0x422[6] will be 1, we should check this to - // prevent from setting 0x422[6] to 0 after download reserved page, or it will cause - // the beacon cannot be sent by HW. - // 2010.06.23. Added by tynli. - if(bRecover) - { - rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl | BIT(6)); - pHalData->RegFwHwTxQCtrl |= BIT(6); - } - - // Clear CR[8] or beacon packet will not be send to TxBuf anymore. - v8 = rtw_read8(padapter, REG_CR+1); - v8 &= ~BIT(0); // ~ENSWBCN - rtw_write8(padapter, REG_CR+1, v8); - } - - JoinBssRptParm.OpMode = mstatus; - - FillH2CCmd(padapter, JOINBSS_RPT_EID, sizeof(JoinBssRptParm), (u8 *)&JoinBssRptParm); - -_func_exit_; -} - -#ifdef CONFIG_BT_COEXIST -static void SetFwRsvdPagePkt_BTCoex(PADAPTER padapter) -{ - PHAL_DATA_TYPE pHalData; - struct xmit_frame *pmgntframe; - struct pkt_attrib *pattrib; - struct xmit_priv *pxmitpriv; - struct mlme_ext_priv *pmlmeext; - struct mlme_ext_info *pmlmeinfo; - u8 fakemac[6]={0x00,0xe0,0x4c,0x00,0x00,0x00}; - u32 BeaconLength, ProbeRspLength, PSPollLength; - u32 NullDataLength, QosNullLength, BTQosNullLength; - u8 *ReservedPagePacket; - u8 PageNum, PageNeed, TxDescLen; - u16 BufIndex; - u32 TotalPacketLen; - RSVDPAGE_LOC RsvdPageLoc; - - - DBG_871X("+%s\n", __FUNCTION__); - - ReservedPagePacket = (u8*)rtw_zmalloc(1024); - if (ReservedPagePacket == NULL) { - DBG_871X("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__); - return; - } - - pHalData = GET_HAL_DATA(padapter); - pxmitpriv = &padapter->xmitpriv; - pmlmeext = &padapter->mlmeextpriv; - pmlmeinfo = &pmlmeext->mlmext_info; - - TxDescLen = TXDESC_SIZE; - PageNum = 0; - - //3 (1) beacon - BufIndex = TXDESC_OFFSET; -#if 0 - ConstructBeacon(padapter, &ReservedPagePacket[BufIndex], &BeaconLength); - - // When we count the first page size, we need to reserve description size for the RSVD - // packet, it will be filled in front of the packet in TXPKTBUF. - PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength); - // To reserved 2 pages for beacon buffer. 2010.06.24. - if (PageNeed == 1) - PageNeed += 1; -#else - // skip Beacon Packet - PageNeed = 3; -#endif - - PageNum += PageNeed; - pHalData->FwRsvdPageStartOffset = PageNum; - - BufIndex += PageNeed*128; - - //3 (2) ps-poll -#if 0 // skip - RsvdPageLoc.LocPsPoll = PageNum; - ConstructPSPoll(padapter, &ReservedPagePacket[BufIndex], &PSPollLength); - rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, _TRUE, _FALSE); - - PageNeed = (u8)PageNum_128(TxDescLen + PSPollLength); - PageNum += PageNeed; - - BufIndex += PageNeed*128; -#endif - - //3 (3) null data - RsvdPageLoc.LocNullData = PageNum; - ConstructNullFunctionData( - padapter, - &ReservedPagePacket[BufIndex], - &NullDataLength, - fakemac, - _FALSE, 0, 0, _FALSE); - rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], NullDataLength, _FALSE, _FALSE); - - PageNeed = (u8)PageNum_128(TxDescLen + NullDataLength); - PageNum += PageNeed; - - BufIndex += PageNeed*128; - - //3 (4) probe response -#if 0 // skip - RsvdPageLoc.LocProbeRsp = PageNum; - ConstructProbeRsp( - padapter, - &ReservedPagePacket[BufIndex], - &ProbeRspLength, - get_my_bssid(&pmlmeinfo->network), - _FALSE); - rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], ProbeRspLength, _FALSE, _FALSE); - - PageNeed = (u8)PageNum_128(TxDescLen + ProbeRspLength); - PageNum += PageNeed; - - BufIndex += PageNeed*128; -#endif - - //3 (5) Qos null data -#if 0 // skip - RsvdPageLoc.LocQosNull = PageNum; - ConstructNullFunctionData( - padapter, - &ReservedPagePacket[BufIndex], - &QosNullLength, - get_my_bssid(&pmlmeinfo->network), - _TRUE, 0, 0, _FALSE); - rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], QosNullLength, _FALSE, _FALSE); - - PageNeed = (u8)PageNum_128(TxDescLen + QosNullLength); - PageNum += PageNeed; - - BufIndex += PageNeed*128; -#endif - - //3 (6) BT Qos null data - RsvdPageLoc.LocBTQosNull = PageNum; - ConstructNullFunctionData( - padapter, - &ReservedPagePacket[BufIndex], - &BTQosNullLength, - fakemac, - _TRUE, 0, 0, _FALSE); - rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], BTQosNullLength, _FALSE, _TRUE); - - TotalPacketLen = BufIndex + BTQosNullLength; - - pmgntframe = alloc_mgtxmitframe(pxmitpriv); - if (pmgntframe == NULL) - goto exit; - - // update attribute - pattrib = &pmgntframe->attrib; - update_mgntframe_attrib(padapter, pattrib); - pattrib->qsel = 0x10; - pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TXDESC_OFFSET; - _rtw_memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen); - - rtw_hal_mgnt_xmit(padapter, pmgntframe); - - DBG_8192C("%s: Set RSVD page location to Fw\n", __FUNCTION__); - FillH2CCmd(padapter, RSVD_PAGE_EID, sizeof(RsvdPageLoc), (u8*)&RsvdPageLoc); - -exit: - rtw_mfree(ReservedPagePacket, 1024); -} - -void rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(PADAPTER padapter) -{ - PHAL_DATA_TYPE pHalData; - u8 bRecover = _FALSE; - - - DBG_8192C("+%s\n", __FUNCTION__); - - pHalData = GET_HAL_DATA(padapter); - - // Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. - if (pHalData->RegFwHwTxQCtrl & BIT(6)) - bRecover = _TRUE; - - // To tell Hw the packet is not a real beacon frame. - pHalData->RegFwHwTxQCtrl &= ~BIT(6); - rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl); - SetFwRsvdPagePkt_BTCoex(padapter); - - // To make sure that if there exists an adapter which would like to send beacon. - // If exists, the origianl value of 0x422[6] will be 1, we should check this to - // prevent from setting 0x422[6] to 0 after download reserved page, or it will cause - // the beacon cannot be sent by HW. - // 2010.06.23. Added by tynli. - if (bRecover) - { - pHalData->RegFwHwTxQCtrl |= BIT(6); - rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl); - } -} -#endif - -#ifdef CONFIG_P2P_PS -void rtl8192c_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; - struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); - struct P2P_PS_Offload_t *p2p_ps_offload = &pHalData->p2p_ps_offload; - u8 i; - -_func_enter_; - - switch(p2p_ps_state) - { - case P2P_PS_DISABLE: - DBG_8192C("P2P_PS_DISABLE \n"); - _rtw_memset(p2p_ps_offload, 0 ,1); - break; - case P2P_PS_ENABLE: - DBG_8192C("P2P_PS_ENABLE \n"); - // update CTWindow value. - if( pwdinfo->ctwindow > 0 ) - { - p2p_ps_offload->CTWindow_En = 1; - rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow); - } - - // hw only support 2 set of NoA - for( i=0 ; i<pwdinfo->noa_num ; i++) - { - // To control the register setting for which NOA - rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4)); - if(i == 0) - p2p_ps_offload->NoA0_En = 1; - else - p2p_ps_offload->NoA1_En = 1; - - // config P2P NoA Descriptor Register - //DBG_8192C("%s(): noa_duration = %x\n",__FUNCTION__,pwdinfo->noa_duration[i]); - rtw_write32(padapter, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]); - - //DBG_8192C("%s(): noa_interval = %x\n",__FUNCTION__,pwdinfo->noa_interval[i]); - rtw_write32(padapter, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]); - - //DBG_8192C("%s(): start_time = %x\n",__FUNCTION__,pwdinfo->noa_start_time[i]); - rtw_write32(padapter, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]); - - //DBG_8192C("%s(): noa_count = %x\n",__FUNCTION__,pwdinfo->noa_count[i]); - rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]); - } - - if( (pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0) ) - { - // rst p2p circuit - rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4)); - - p2p_ps_offload->Offload_En = 1; - - if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) - { - p2p_ps_offload->role= 1; - p2p_ps_offload->AllStaSleep = 0; - } - else - { - p2p_ps_offload->role= 0; - } - - p2p_ps_offload->discovery = 0; - } - break; - case P2P_PS_SCAN: - DBG_8192C("P2P_PS_SCAN \n"); - p2p_ps_offload->discovery = 1; - break; - case P2P_PS_SCAN_DONE: - DBG_8192C("P2P_PS_SCAN_DONE \n"); - p2p_ps_offload->discovery = 0; - pwdinfo->p2p_ps_state = P2P_PS_ENABLE; - break; - default: - break; - } - - FillH2CCmd(padapter, P2P_PS_OFFLOAD_EID, 1, (u8 *)p2p_ps_offload); - -_func_exit_; - -} -#endif //CONFIG_P2P_PS - -#ifdef CONFIG_IOL -#include <rtw_iol.h> -#ifdef CONFIG_USB_HCI -#include <usb_ops.h> -#endif -int rtl8192c_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt) -{ - IO_OFFLOAD_LOC IoOffloadLoc; - u32 start_time = rtw_get_current_time(); - u32 passing_time_ms; - u8 polling_ret; - int ret = _FAIL; - - if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS) - goto exit; -#ifdef CONFIG_USB_HCI - { - struct pkt_attrib *pattrib = &xmit_frame->attrib; - if(rtw_usb_bulk_size_boundary(adapter,TXDESC_SIZE+pattrib->last_txcmdsz)) - { - if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS) - goto exit; - } - } -#endif //CONFIG_USB_HCI - - - dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms); - - IoOffloadLoc.LocCmd = 0; - if(_SUCCESS != FillH2CCmd(adapter, H2C_92C_IO_OFFLOAD, sizeof(IO_OFFLOAD_LOC), (u8 *)&IoOffloadLoc)) - goto exit; - - //polling if the IO offloading is done - while( (passing_time_ms=rtw_get_passing_time_ms(start_time)) <= max_wating_ms) { - #if 0 //C2H - if(0xff == rtw_read8(adapter, REG_C2HEVT_CLEAR)) - break; - #else// 0x1c3 - if(0x00 != (polling_ret=rtw_read8(adapter, 0x1c3))) - break; - #endif - rtw_msleep_os(5); - } - #if 0 //debug - DBG_871X("IOL %s, polling_ret:0x%02x, 0x1c0=0x%08x, 0x1c4=0x%08x, 0x1cc=0x%08x, 0x1e8=0x%08x, 0x130=0x%08x, 0x134=0x%08x\n" - , polling_ret==0xff?"success":"error" - , polling_ret - , rtw_read32(adapter, 0x1c0) - , rtw_read32(adapter, 0x1c4) - , rtw_read32(adapter, 0x1cc) - , rtw_read32(adapter, 0x1e8) - , rtw_read32(adapter, 0x130) - , rtw_read32(adapter, 0x134) - ); - rtw_write32(adapter, 0x1c0, 0x0); - #endif - - if(polling_ret == 0xff) - ret =_SUCCESS; - else { - DBG_871X("IOL %s, polling_ret:0x%02x\n" - //", 0x1c0=0x%08x, 0x1c4=0x%08x, 0x1cc=0x%08x, 0x1e8=0x%08x, 0x130=0x%08x, 0x134=0x%08x\n" - , polling_ret==0xff?"success":"error" - , polling_ret - //, rtw_read32(adapter, 0x1c0) - //, rtw_read32(adapter, 0x1c4) - //, rtw_read32(adapter, 0x1cc) - //, rtw_read32(adapter, 0x1e8) - //, rtw_read32(adapter, 0x130) - //, rtw_read32(adapter, 0x134) - ); - #if 0 //debug - rtw_write16(adapter, 0x1c4, 0x0000); - rtw_msleep_os(10); - DBG_871X("after reset, 0x1c4=0x%08x\n", rtw_read32(adapter, 0x1c4)); - #endif - - } - - { - #if 0 //C2H - u32 c2h_evt; - int i; - c2h_evt = rtw_read32(adapter, REG_C2HEVT_MSG_NORMAL); - DBG_871X("%s io-offloading complete, in %ums: 0x%08x\n", __FUNCTION__, passing_time_ms, c2h_evt); - rtw_write8(adapter, REG_C2HEVT_CLEAR, 0x0); - #else// 0x1c3 - //DBG_871X("%s IOF complete in %ums\n", __FUNCTION__, passing_time_ms); - rtw_write8(adapter, 0x1c3, 0x0); - #endif - } - -exit: - return ret; - -} -#endif //CONFIG_IOL - -#ifdef CONFIG_TSF_RESET_OFFLOAD -/* - ask FW to Reset sync register at Beacon early interrupt -*/ -u8 rtl8723c_reset_tsf(_adapter *padapter, u8 reset_port ) -{ - u8 buf[2]; - u8 res=_SUCCESS; - -_func_enter_; - if (IFACE_PORT0==reset_port) { - buf[0] = 0x1; buf[1] = 0; - - } else{ - buf[0] = 0x0; buf[1] = 0x1; - } - FillH2CCmd(padapter, H2C_RESET_TSF, 2, buf); -_func_exit_; - - return res; -} -#endif // CONFIG_TSF_RESET_OFFLOAD - +/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8723A_CMD_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <recv_osdep.h>
+#include <cmd_osdep.h>
+#include <mlme_osdep.h>
+#include <rtw_byteorder.h>
+#include <circ_buf.h>
+#include <rtw_ioctl_set.h>
+
+#include <rtl8723a_hal.h>
+
+
+#define RTL92C_MAX_H2C_BOX_NUMS 4
+#define RTL92C_MAX_CMD_LEN 5
+#define MESSAGE_BOX_SIZE 4
+#define EX_MESSAGE_BOX_SIZE 2
+
+
+static u8 _is_fw_read_cmd_down(_adapter* padapter, u8 msgbox_num)
+{
+ u8 read_down = _FALSE;
+ int retry_cnts = 100;
+
+ u8 valid;
+
+ //DBG_8192C(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num);
+
+ do{
+ valid = rtw_read8(padapter,REG_HMETFR) & BIT(msgbox_num);
+
+ if(0 == valid ){
+ read_down = _TRUE;
+ }
+ }while( (!read_down) && (retry_cnts--));
+
+ return read_down;
+
+}
+
+
+/*****************************************
+* H2C Msg format :
+*| 31 - 8 |7 | 6 - 0 |
+*| h2c_msg |Ext_bit |CMD_ID |
+*
+******************************************/
+s32 FillH2CCmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer)
+{
+ u8 bcmd_down = _FALSE;
+ s32 retry_cnts = 100;
+ u8 h2c_box_num;
+ u32 msgbox_addr;
+ u32 msgbox_ex_addr;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ u32 h2c_cmd = 0;
+ u16 h2c_cmd_ex = 0;
+ s32 ret = _FAIL;
+
+_func_enter_;
+
+ padapter = GET_PRIMARY_ADAPTER(padapter);
+ pHalData = GET_HAL_DATA(padapter);
+
+ _enter_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);
+
+ if (!pCmdBuffer) {
+ goto exit;
+ }
+ if (CmdLen > RTL92C_MAX_CMD_LEN) {
+ goto exit;
+ }
+ if (padapter->bSurpriseRemoved == _TRUE)
+ goto exit;
+
+ //pay attention to if race condition happened in H2C cmd setting.
+ do{
+ h2c_box_num = pHalData->LastHMEBoxNum;
+
+ if(!_is_fw_read_cmd_down(padapter, h2c_box_num)){
+ DBG_8192C(" fw read cmd failed...\n");
+ goto exit;
+ }
+
+ if(CmdLen<=3)
+ {
+ _rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer, CmdLen );
+ }
+ else{
+ _rtw_memcpy((u8*)(&h2c_cmd_ex), pCmdBuffer, EX_MESSAGE_BOX_SIZE);
+ _rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer+2,( CmdLen-EX_MESSAGE_BOX_SIZE));
+ *(u8*)(&h2c_cmd) |= BIT(7);
+ }
+
+ *(u8*)(&h2c_cmd) |= ElementID;
+
+ if(h2c_cmd & BIT(7)){
+ msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num *EX_MESSAGE_BOX_SIZE);
+ h2c_cmd_ex = le16_to_cpu( h2c_cmd_ex );
+ rtw_write16(padapter, msgbox_ex_addr, h2c_cmd_ex);
+ }
+ msgbox_addr =REG_HMEBOX_0 + (h2c_box_num *MESSAGE_BOX_SIZE);
+ h2c_cmd = le32_to_cpu( h2c_cmd );
+ rtw_write32(padapter,msgbox_addr, h2c_cmd);
+
+ bcmd_down = _TRUE;
+
+ //DBG_8192C("MSG_BOX:%d,CmdLen(%d), reg:0x%x =>h2c_cmd:0x%x, reg:0x%x =>h2c_cmd_ex:0x%x ..\n"
+ // ,pHalData->LastHMEBoxNum ,CmdLen,msgbox_addr,h2c_cmd,msgbox_ex_addr,h2c_cmd_ex);
+
+ pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL92C_MAX_H2C_BOX_NUMS;
+
+ }while((!bcmd_down) && (retry_cnts--));
+
+ ret = _SUCCESS;
+
+exit:
+
+ _exit_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);
+
+_func_exit_;
+
+ return ret;
+}
+
+u8 rtl8192c_h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf)
+{
+ u8 ElementID, CmdLen;
+ u8 *pCmdBuffer;
+ struct cmd_msg_parm *pcmdmsg;
+
+ if(!pbuf)
+ return H2C_PARAMETERS_ERROR;
+
+ pcmdmsg = (struct cmd_msg_parm*)pbuf;
+ ElementID = pcmdmsg->eid;
+ CmdLen = pcmdmsg->sz;
+ pCmdBuffer = pcmdmsg->buf;
+
+ FillH2CCmd(padapter, ElementID, CmdLen, pCmdBuffer);
+
+ return H2C_SUCCESS;
+}
+
+#if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED)
+u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter *padapter ,u8 bfwpoll, u16 period)
+{
+ u8 res=_SUCCESS;
+ struct H2C_SS_RFOFF_PARAM param;
+ DBG_8192C("==>%s bfwpoll(%x)\n",__FUNCTION__,bfwpoll);
+ param.gpio_period = period;//Polling GPIO_11 period time
+ param.ROFOn = (_TRUE == bfwpoll)?1:0;
+ FillH2CCmd(padapter, SELECTIVE_SUSPEND_ROF_CMD, sizeof(param), (u8*)(¶m));
+ return res;
+}
+#endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED
+
+u8 rtl8192c_set_rssi_cmd(_adapter*padapter, u8 *param)
+{
+ u8 res=_SUCCESS;
+
+_func_enter_;
+
+ *((u32*) param ) = cpu_to_le32( *((u32*) param ) );
+
+ FillH2CCmd(padapter, RSSI_SETTING_EID, 3, param);
+
+_func_exit_;
+
+ return res;
+}
+
+u8 rtl8192c_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg)
+{
+ u8 buf[5];
+ u8 res=_SUCCESS;
+
+_func_enter_;
+
+ _rtw_memset(buf, 0, 5);
+ mask = cpu_to_le32( mask );
+ _rtw_memcpy(buf, &mask, 4);
+ buf[4] = arg;
+
+ FillH2CCmd(padapter, MACID_CONFIG_EID, 5, buf);
+
+_func_exit_;
+
+ return res;
+
+}
+
+//bitmap[0:27] = tx_rate_bitmap
+//bitmap[28:31]= Rate Adaptive id
+//arg[0:4] = macid
+//arg[5] = Short GI
+void rtl8192c_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 rssi_level)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+
+ u8 macid = arg&0x1f;
+
+#ifdef CONFIG_ODM_REFRESH_RAMASK
+ u8 raid = (bitmap>>28) & 0x0f;
+ bitmap &=0x0fffffff;
+ if(rssi_level != DM_RATR_STA_INIT)
+ bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, macid, bitmap, rssi_level);
+
+ bitmap |= ((raid<<28)&0xf0000000);
+#endif //CONFIG_ODM_REFRESH_RAMASK
+
+
+ if(pHalData->fw_ractrl == _TRUE)
+ {
+ rtl8192c_set_raid_cmd(pAdapter, bitmap, arg);
+ }
+ else
+ {
+ u8 init_rate, shortGIrate=_FALSE;
+
+ init_rate = get_highest_rate_idx(bitmap&0x0fffffff)&0x3f;
+
+
+ shortGIrate = (arg&BIT(5)) ? _TRUE:_FALSE;
+
+ if (shortGIrate==_TRUE)
+ init_rate |= BIT(6);
+
+ rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate);
+ }
+
+}
+
+void rtl8723a_set_FwPwrMode_cmd(PADAPTER padapter, u8 Mode)
+{
+ SETPWRMODE_PARM H2CSetPwrMode;
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+
+_func_enter_;
+
+ H2CSetPwrMode.Mode = Mode;
+ H2CSetPwrMode.SmartPS = pwrpriv->smart_ps;
+ H2CSetPwrMode.AwakeInterval = 1;
+ H2CSetPwrMode.bAllQueueUAPSD = padapter->registrypriv.uapsd_enable;
+
+ if(0 == Mode)
+ {
+ /* Leave LPS, set BcnAntMode to 0 */
+ H2CSetPwrMode.BcnAntMode = 0;
+ }
+ else
+ {
+ H2CSetPwrMode.BcnAntMode = pwrpriv->bcn_ant_mode;
+ }
+
+ DBG_871X("%s: Mode=%d SmartPS=%d UAPSD=%d BcnMode=0x%02x\n", __FUNCTION__,
+ H2CSetPwrMode.Mode, H2CSetPwrMode.SmartPS, H2CSetPwrMode.bAllQueueUAPSD, H2CSetPwrMode.BcnAntMode);
+
+ FillH2CCmd(padapter, SET_PWRMODE_EID, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode);
+
+_func_exit_;
+}
+
+
+void rtl8723a_set_FwMediaStatus_cmd(PADAPTER padapter, u16 mstatus_rpt )
+{
+ u8 opmode,macid;
+ u16 mst_rpt = cpu_to_le16 (mstatus_rpt);
+ u32 reg_macid_no_link = REG_MACID_NO_LINK;
+ opmode = (u8) mst_rpt;
+ macid = (u8)(mst_rpt >> 8) ;
+ DBG_871X("### %s: MStatus=%x MACID=%d \n", __FUNCTION__,opmode,macid);
+
+ //Delete select macid (MACID 0~63) from queue list.
+ if(opmode == 1)// 1:connect
+ {
+ rtw_write32(padapter,reg_macid_no_link, (rtw_read32(padapter,reg_macid_no_link) & (~BIT(macid))));
+ }
+ else//0: disconnect
+ {
+ rtw_write32(padapter,reg_macid_no_link, (rtw_read32(padapter,reg_macid_no_link)|BIT(macid)));
+ }
+}
+
+
+void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength)
+{
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ u16 *fctrl;
+ u32 rate_len, pktlen;
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
+ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+
+ //DBG_871X("%s\n", __FUNCTION__);
+
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+ fctrl = &(pwlanhdr->frame_ctl);
+ *(fctrl) = 0;
+
+ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN);
+
+ SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/);
+ //pmlmeext->mgnt_seq++;
+ SetFrameSubType(pframe, WIFI_BEACON);
+
+ pframe += sizeof(struct rtw_ieee80211_hdr_3addr);
+ pktlen = sizeof (struct rtw_ieee80211_hdr_3addr);
+
+ //timestamp will be inserted by hardware
+ pframe += 8;
+ pktlen += 8;
+
+ // beacon interval: 2 bytes
+ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2);
+
+ pframe += 2;
+ pktlen += 2;
+
+ // capability info: 2 bytes
+ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2);
+
+ pframe += 2;
+ pktlen += 2;
+
+ if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)
+ {
+ //DBG_871X("ie len=%d\n", cur_network->IELength);
+ pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs);
+ _rtw_memcpy(pframe, cur_network->IEs+sizeof(NDIS_802_11_FIXED_IEs), pktlen);
+
+ goto _ConstructBeacon;
+ }
+
+ //below for ad-hoc mode
+
+ // SSID
+ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen);
+
+ // supported rates...
+ rate_len = rtw_get_rateset_len(cur_network->SupportedRates);
+ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pktlen);
+
+ // DS parameter set
+ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen);
+
+ if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)
+ {
+ u32 ATIMWindow;
+ // IBSS Parameter Set...
+ //ATIMWindow = cur->Configuration.ATIMWindow;
+ ATIMWindow = 0;
+ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen);
+ }
+
+
+ //todo: ERP IE
+
+
+ // EXTERNDED SUPPORTED RATE
+ if (rate_len > 8)
+ {
+ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen);
+ }
+
+
+ //todo:HT for adhoc
+
+_ConstructBeacon:
+
+ if ((pktlen + TXDESC_SIZE) > 512)
+ {
+ DBG_871X("beacon frame too large\n");
+ return;
+ }
+
+ *pLength = pktlen;
+
+ //DBG_871X("%s bcn_sz=%d\n", __FUNCTION__, pktlen);
+
+}
+
+void ConstructPSPoll(_adapter *padapter, u8 *pframe, u32 *pLength)
+{
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ u16 *fctrl;
+ u32 pktlen;
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+
+ //DBG_871X("%s\n", __FUNCTION__);
+
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+ // Frame control.
+ fctrl = &(pwlanhdr->frame_ctl);
+ *(fctrl) = 0;
+ SetPwrMgt(fctrl);
+ SetFrameSubType(pframe, WIFI_PSPOLL);
+
+ // AID.
+ SetDuration(pframe, (pmlmeinfo->aid | 0xc000));
+
+ // BSSID.
+ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+
+ // TA.
+ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
+
+ *pLength = 16;
+}
+
+void ConstructNullFunctionData(
+ PADAPTER padapter,
+ u8 *pframe,
+ u32 *pLength,
+ u8 *StaAddr,
+ u8 bQoS,
+ u8 AC,
+ u8 bEosp,
+ u8 bForcePowerSave)
+{
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ u16 *fctrl;
+ u32 pktlen;
+ struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
+ struct wlan_network *cur_network = &pmlmepriv->cur_network;
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+
+
+ //DBG_871X("%s:%d\n", __FUNCTION__, bForcePowerSave);
+
+ pwlanhdr = (struct rtw_ieee80211_hdr*)pframe;
+
+ fctrl = &pwlanhdr->frame_ctl;
+ *(fctrl) = 0;
+ if (bForcePowerSave)
+ {
+ SetPwrMgt(fctrl);
+ }
+
+ switch(cur_network->network.InfrastructureMode)
+ {
+ case Ndis802_11Infrastructure:
+ SetToDs(fctrl);
+ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN);
+ break;
+ case Ndis802_11APMode:
+ SetFrDs(fctrl);
+ _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN);
+ break;
+ case Ndis802_11IBSS:
+ default:
+ _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN);
+ break;
+ }
+
+ SetSeqNum(pwlanhdr, 0);
+
+ if (bQoS == _TRUE) {
+ struct rtw_ieee80211_hdr_3addr_qos *pwlanqoshdr;
+
+ SetFrameSubType(pframe, WIFI_QOS_DATA_NULL);
+
+ pwlanqoshdr = (struct rtw_ieee80211_hdr_3addr_qos*)pframe;
+ SetPriority(&pwlanqoshdr->qc, AC);
+ SetEOSP(&pwlanqoshdr->qc, bEosp);
+
+ pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos);
+ } else {
+ SetFrameSubType(pframe, WIFI_DATA_NULL);
+
+ pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+ }
+
+ *pLength = pktlen;
+}
+
+void ConstructProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *StaAddr, BOOLEAN bHideSSID)
+{
+ struct rtw_ieee80211_hdr *pwlanhdr;
+ u16 *fctrl;
+ u8 *mac, *bssid;
+ u32 pktlen;
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network);
+
+
+ //DBG_871X("%s\n", __FUNCTION__);
+
+ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe;
+
+ mac = myid(&(padapter->eeprompriv));
+ bssid = cur_network->MacAddress;
+
+ fctrl = &(pwlanhdr->frame_ctl);
+ *(fctrl) = 0;
+ _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN);
+ _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN);
+
+ SetSeqNum(pwlanhdr, 0);
+ SetFrameSubType(fctrl, WIFI_PROBERSP);
+
+ pktlen = sizeof(struct rtw_ieee80211_hdr_3addr);
+ pframe += pktlen;
+
+ if(cur_network->IELength>MAX_IE_SZ)
+ return;
+
+ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength);
+ pframe += cur_network->IELength;
+ pktlen += cur_network->IELength;
+
+ *pLength = pktlen;
+}
+
+// To check if reserved page content is destroyed by beacon beacuse beacon is too large.
+// 2010.06.23. Added by tynli.
+VOID
+CheckFwRsvdPageContent(
+ IN PADAPTER Adapter
+)
+{
+ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter);
+ u32 MaxBcnPageNum;
+
+ if(pHalData->FwRsvdPageStartOffset != 0)
+ {
+ /*MaxBcnPageNum = PageNum_128(pMgntInfo->MaxBeaconSize);
+ RT_ASSERT((MaxBcnPageNum <= pHalData->FwRsvdPageStartOffset),
+ ("CheckFwRsvdPageContent(): The reserved page content has been"\
+ "destroyed by beacon!!! MaxBcnPageNum(%d) FwRsvdPageStartOffset(%d)\n!",
+ MaxBcnPageNum, pHalData->FwRsvdPageStartOffset));*/
+ }
+}
+
+//
+// Description: Fill the reserved packets that FW will use to RSVD page.
+// Now we just send 4 types packet to rsvd page.
+// (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp.
+// Input:
+// bDLFinished - FALSE: At the first time we will send all the packets as a large packet to Hw,
+// so we need to set the packet length to total lengh.
+// TRUE: At the second time, we should send the first packet (default:beacon)
+// to Hw again and set the lengh in descriptor to the real beacon lengh.
+// 2009.10.15 by tynli.
+static void SetFwRsvdPagePkt(PADAPTER padapter, BOOLEAN bDLFinished)
+{
+ PHAL_DATA_TYPE pHalData;
+ struct xmit_frame *pmgntframe;
+ struct pkt_attrib *pattrib;
+ struct xmit_priv *pxmitpriv;
+ struct mlme_ext_priv *pmlmeext;
+ struct mlme_ext_info *pmlmeinfo;
+ u32 BeaconLength, ProbeRspLength, PSPollLength;
+ u32 NullDataLength, QosNullLength, BTQosNullLength;
+ u8 *ReservedPagePacket;
+ u8 PageNum, PageNeed, TxDescLen;
+ u16 BufIndex;
+ u32 TotalPacketLen;
+ RSVDPAGE_LOC RsvdPageLoc;
+
+
+ DBG_871X("%s\n", __FUNCTION__);
+
+ ReservedPagePacket = (u8*)rtw_zmalloc(1000);
+ if (ReservedPagePacket == NULL) {
+ DBG_871X("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
+ return;
+ }
+
+ pHalData = GET_HAL_DATA(padapter);
+ pxmitpriv = &padapter->xmitpriv;
+ pmlmeext = &padapter->mlmeextpriv;
+ pmlmeinfo = &pmlmeext->mlmext_info;
+
+ TxDescLen = TXDESC_SIZE;
+ PageNum = 0;
+
+ //3 (1) beacon
+ BufIndex = TXDESC_OFFSET;
+ ConstructBeacon(padapter, &ReservedPagePacket[BufIndex], &BeaconLength);
+
+ // When we count the first page size, we need to reserve description size for the RSVD
+ // packet, it will be filled in front of the packet in TXPKTBUF.
+ PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength);
+ // To reserved 2 pages for beacon buffer. 2010.06.24.
+ if (PageNeed == 1)
+ PageNeed += 1;
+ PageNum += PageNeed;
+ pHalData->FwRsvdPageStartOffset = PageNum;
+
+ BufIndex += PageNeed*128;
+
+ //3 (2) ps-poll
+ RsvdPageLoc.LocPsPoll = PageNum;
+ ConstructPSPoll(padapter, &ReservedPagePacket[BufIndex], &PSPollLength);
+ rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, _TRUE, _FALSE);
+
+ PageNeed = (u8)PageNum_128(TxDescLen + PSPollLength);
+ PageNum += PageNeed;
+
+ BufIndex += PageNeed*128;
+
+ //3 (3) null data
+ RsvdPageLoc.LocNullData = PageNum;
+ ConstructNullFunctionData(
+ padapter,
+ &ReservedPagePacket[BufIndex],
+ &NullDataLength,
+ get_my_bssid(&pmlmeinfo->network),
+ _FALSE, 0, 0, _FALSE);
+ rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], NullDataLength, _FALSE, _FALSE);
+
+ PageNeed = (u8)PageNum_128(TxDescLen + NullDataLength);
+ PageNum += PageNeed;
+
+ BufIndex += PageNeed*128;
+
+ //3 (4) probe response
+ RsvdPageLoc.LocProbeRsp = PageNum;
+ ConstructProbeRsp(
+ padapter,
+ &ReservedPagePacket[BufIndex],
+ &ProbeRspLength,
+ get_my_bssid(&pmlmeinfo->network),
+ _FALSE);
+ rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], ProbeRspLength, _FALSE, _FALSE);
+
+ PageNeed = (u8)PageNum_128(TxDescLen + ProbeRspLength);
+ PageNum += PageNeed;
+
+ BufIndex += PageNeed*128;
+
+ //3 (5) Qos null data
+ RsvdPageLoc.LocQosNull = PageNum;
+ ConstructNullFunctionData(
+ padapter,
+ &ReservedPagePacket[BufIndex],
+ &QosNullLength,
+ get_my_bssid(&pmlmeinfo->network),
+ _TRUE, 0, 0, _FALSE);
+ rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], QosNullLength, _FALSE, _FALSE);
+
+ PageNeed = (u8)PageNum_128(TxDescLen + QosNullLength);
+ PageNum += PageNeed;
+
+ BufIndex += PageNeed*128;
+
+ //3 (6) BT Qos null data
+ RsvdPageLoc.LocBTQosNull = PageNum;
+ ConstructNullFunctionData(
+ padapter,
+ &ReservedPagePacket[BufIndex],
+ &BTQosNullLength,
+ get_my_bssid(&pmlmeinfo->network),
+ _TRUE, 0, 0, _FALSE);
+ rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], BTQosNullLength, _FALSE, _TRUE);
+
+ TotalPacketLen = BufIndex + BTQosNullLength;
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (pmgntframe == NULL)
+ goto exit;
+
+ // update attribute
+ pattrib = &pmgntframe->attrib;
+ update_mgntframe_attrib(padapter, pattrib);
+ pattrib->qsel = 0x10;
+ pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TXDESC_OFFSET;
+ _rtw_memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen);
+
+ rtw_hal_mgnt_xmit(padapter, pmgntframe);
+
+ DBG_871X("%s: Set RSVD page location to Fw\n", __FUNCTION__);
+ FillH2CCmd(padapter, RSVD_PAGE_EID, sizeof(RsvdPageLoc), (u8*)&RsvdPageLoc);
+
+exit:
+ rtw_mfree(ReservedPagePacket, 1000);
+}
+
+void rtl8723a_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus)
+{
+ JOINBSSRPT_PARM JoinBssRptParm;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
+ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
+
+_func_enter_;
+
+ DBG_871X("%s mstatus(%x)\n", __FUNCTION__,mstatus);
+
+ if(mstatus == 1)
+ {
+ BOOLEAN bRecover = _FALSE;
+ u8 v8;
+
+ // We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C.
+ // Suggested by filen. Added by tynli.
+ rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid));
+ // Do not set TSF again here or vWiFi beacon DMA INT will not work.
+ //correct_TSF(padapter, pmlmeext);
+ // Hw sequende enable by dedault. 2010.06.23. by tynli.
+ //rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF));
+ //rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
+
+ // set REG_CR bit 8
+ v8 = rtw_read8(padapter, REG_CR+1);
+ v8 |= BIT(0); // ENSWBCN
+ rtw_write8(padapter, REG_CR+1, v8);
+
+ // Disable Hw protection for a time which revserd for Hw sending beacon.
+ // Fix download reserved page packet fail that access collision with the protection time.
+ // 2010.05.11. Added by tynli.
+// SetBcnCtrlReg(padapter, 0, BIT(3));
+// SetBcnCtrlReg(padapter, BIT(4), 0);
+ SetBcnCtrlReg(padapter, BIT(4), BIT(3));
+
+ // Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.
+ if (pHalData->RegFwHwTxQCtrl & BIT(6))
+ bRecover = _TRUE;
+
+ // To tell Hw the packet is not a real beacon frame.
+ //U1bTmp = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2);
+ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl & ~BIT(6));
+ pHalData->RegFwHwTxQCtrl &= ~BIT(6);
+ SetFwRsvdPagePkt(padapter, 0);
+
+ // 2010.05.11. Added by tynli.
+// SetBcnCtrlReg(padapter, BIT3, 0);
+// SetBcnCtrlReg(padapter, 0, BIT4);
+ SetBcnCtrlReg(padapter, BIT(3), BIT(4));
+
+ // To make sure that if there exists an adapter which would like to send beacon.
+ // If exists, the origianl value of 0x422[6] will be 1, we should check this to
+ // prevent from setting 0x422[6] to 0 after download reserved page, or it will cause
+ // the beacon cannot be sent by HW.
+ // 2010.06.23. Added by tynli.
+ if(bRecover)
+ {
+ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl | BIT(6));
+ pHalData->RegFwHwTxQCtrl |= BIT(6);
+ }
+
+ // Clear CR[8] or beacon packet will not be send to TxBuf anymore.
+ v8 = rtw_read8(padapter, REG_CR+1);
+ v8 &= ~BIT(0); // ~ENSWBCN
+ rtw_write8(padapter, REG_CR+1, v8);
+ }
+
+ JoinBssRptParm.OpMode = mstatus;
+
+ FillH2CCmd(padapter, JOINBSS_RPT_EID, sizeof(JoinBssRptParm), (u8 *)&JoinBssRptParm);
+
+_func_exit_;
+}
+
+#ifdef CONFIG_BT_COEXIST
+static void SetFwRsvdPagePkt_BTCoex(PADAPTER padapter)
+{
+ PHAL_DATA_TYPE pHalData;
+ struct xmit_frame *pmgntframe;
+ struct pkt_attrib *pattrib;
+ struct xmit_priv *pxmitpriv;
+ struct mlme_ext_priv *pmlmeext;
+ struct mlme_ext_info *pmlmeinfo;
+ u8 fakemac[6]={0x00,0xe0,0x4c,0x00,0x00,0x00};
+ u32 BeaconLength, ProbeRspLength, PSPollLength;
+ u32 NullDataLength, QosNullLength, BTQosNullLength;
+ u8 *ReservedPagePacket;
+ u8 PageNum, PageNeed, TxDescLen;
+ u16 BufIndex;
+ u32 TotalPacketLen;
+ RSVDPAGE_LOC RsvdPageLoc;
+
+
+ DBG_871X("+%s\n", __FUNCTION__);
+
+ ReservedPagePacket = (u8*)rtw_zmalloc(1024);
+ if (ReservedPagePacket == NULL) {
+ DBG_871X("%s: alloc ReservedPagePacket fail!\n", __FUNCTION__);
+ return;
+ }
+
+ pHalData = GET_HAL_DATA(padapter);
+ pxmitpriv = &padapter->xmitpriv;
+ pmlmeext = &padapter->mlmeextpriv;
+ pmlmeinfo = &pmlmeext->mlmext_info;
+
+ TxDescLen = TXDESC_SIZE;
+ PageNum = 0;
+
+ //3 (1) beacon
+ BufIndex = TXDESC_OFFSET;
+#if 0
+ ConstructBeacon(padapter, &ReservedPagePacket[BufIndex], &BeaconLength);
+
+ // When we count the first page size, we need to reserve description size for the RSVD
+ // packet, it will be filled in front of the packet in TXPKTBUF.
+ PageNeed = (u8)PageNum_128(TxDescLen + BeaconLength);
+ // To reserved 2 pages for beacon buffer. 2010.06.24.
+ if (PageNeed == 1)
+ PageNeed += 1;
+#else
+ // skip Beacon Packet
+ PageNeed = 3;
+#endif
+
+ PageNum += PageNeed;
+ pHalData->FwRsvdPageStartOffset = PageNum;
+
+ BufIndex += PageNeed*128;
+
+ //3 (2) ps-poll
+#if 0 // skip
+ RsvdPageLoc.LocPsPoll = PageNum;
+ ConstructPSPoll(padapter, &ReservedPagePacket[BufIndex], &PSPollLength);
+ rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, _TRUE, _FALSE);
+
+ PageNeed = (u8)PageNum_128(TxDescLen + PSPollLength);
+ PageNum += PageNeed;
+
+ BufIndex += PageNeed*128;
+#endif
+
+ //3 (3) null data
+ RsvdPageLoc.LocNullData = PageNum;
+ ConstructNullFunctionData(
+ padapter,
+ &ReservedPagePacket[BufIndex],
+ &NullDataLength,
+ fakemac,
+ _FALSE, 0, 0, _FALSE);
+ rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], NullDataLength, _FALSE, _FALSE);
+
+ PageNeed = (u8)PageNum_128(TxDescLen + NullDataLength);
+ PageNum += PageNeed;
+
+ BufIndex += PageNeed*128;
+
+ //3 (4) probe response
+#if 0 // skip
+ RsvdPageLoc.LocProbeRsp = PageNum;
+ ConstructProbeRsp(
+ padapter,
+ &ReservedPagePacket[BufIndex],
+ &ProbeRspLength,
+ get_my_bssid(&pmlmeinfo->network),
+ _FALSE);
+ rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], ProbeRspLength, _FALSE, _FALSE);
+
+ PageNeed = (u8)PageNum_128(TxDescLen + ProbeRspLength);
+ PageNum += PageNeed;
+
+ BufIndex += PageNeed*128;
+#endif
+
+ //3 (5) Qos null data
+#if 0 // skip
+ RsvdPageLoc.LocQosNull = PageNum;
+ ConstructNullFunctionData(
+ padapter,
+ &ReservedPagePacket[BufIndex],
+ &QosNullLength,
+ get_my_bssid(&pmlmeinfo->network),
+ _TRUE, 0, 0, _FALSE);
+ rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], QosNullLength, _FALSE, _FALSE);
+
+ PageNeed = (u8)PageNum_128(TxDescLen + QosNullLength);
+ PageNum += PageNeed;
+
+ BufIndex += PageNeed*128;
+#endif
+
+ //3 (6) BT Qos null data
+ RsvdPageLoc.LocBTQosNull = PageNum;
+ ConstructNullFunctionData(
+ padapter,
+ &ReservedPagePacket[BufIndex],
+ &BTQosNullLength,
+ fakemac,
+ _TRUE, 0, 0, _FALSE);
+ rtl8723a_fill_fake_txdesc(padapter, &ReservedPagePacket[BufIndex-TxDescLen], BTQosNullLength, _FALSE, _TRUE);
+
+ TotalPacketLen = BufIndex + BTQosNullLength;
+
+ pmgntframe = alloc_mgtxmitframe(pxmitpriv);
+ if (pmgntframe == NULL)
+ goto exit;
+
+ // update attribute
+ pattrib = &pmgntframe->attrib;
+ update_mgntframe_attrib(padapter, pattrib);
+ pattrib->qsel = 0x10;
+ pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TXDESC_OFFSET;
+ _rtw_memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen);
+
+ rtw_hal_mgnt_xmit(padapter, pmgntframe);
+
+ DBG_8192C("%s: Set RSVD page location to Fw\n", __FUNCTION__);
+ FillH2CCmd(padapter, RSVD_PAGE_EID, sizeof(RsvdPageLoc), (u8*)&RsvdPageLoc);
+
+exit:
+ rtw_mfree(ReservedPagePacket, 1024);
+}
+
+void rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(PADAPTER padapter)
+{
+ PHAL_DATA_TYPE pHalData;
+ u8 bRecover = _FALSE;
+
+
+ DBG_8192C("+%s\n", __FUNCTION__);
+
+ pHalData = GET_HAL_DATA(padapter);
+
+ // Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.
+ if (pHalData->RegFwHwTxQCtrl & BIT(6))
+ bRecover = _TRUE;
+
+ // To tell Hw the packet is not a real beacon frame.
+ pHalData->RegFwHwTxQCtrl &= ~BIT(6);
+ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
+ SetFwRsvdPagePkt_BTCoex(padapter);
+
+ // To make sure that if there exists an adapter which would like to send beacon.
+ // If exists, the origianl value of 0x422[6] will be 1, we should check this to
+ // prevent from setting 0x422[6] to 0 after download reserved page, or it will cause
+ // the beacon cannot be sent by HW.
+ // 2010.06.23. Added by tynli.
+ if (bRecover)
+ {
+ pHalData->RegFwHwTxQCtrl |= BIT(6);
+ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl);
+ }
+}
+#endif
+
+#ifdef CONFIG_P2P_PS
+void rtl8192c_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter);
+ struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
+ struct P2P_PS_Offload_t *p2p_ps_offload = &pHalData->p2p_ps_offload;
+ u8 i;
+
+_func_enter_;
+
+ switch(p2p_ps_state)
+ {
+ case P2P_PS_DISABLE:
+ DBG_8192C("P2P_PS_DISABLE \n");
+ _rtw_memset(p2p_ps_offload, 0 ,1);
+ break;
+ case P2P_PS_ENABLE:
+ DBG_8192C("P2P_PS_ENABLE \n");
+ // update CTWindow value.
+ if( pwdinfo->ctwindow > 0 )
+ {
+ p2p_ps_offload->CTWindow_En = 1;
+ rtw_write8(padapter, REG_P2P_CTWIN, pwdinfo->ctwindow);
+ }
+
+ // hw only support 2 set of NoA
+ for( i=0 ; i<pwdinfo->noa_num ; i++)
+ {
+ // To control the register setting for which NOA
+ rtw_write8(padapter, REG_NOA_DESC_SEL, (i << 4));
+ if(i == 0)
+ p2p_ps_offload->NoA0_En = 1;
+ else
+ p2p_ps_offload->NoA1_En = 1;
+
+ // config P2P NoA Descriptor Register
+ //DBG_8192C("%s(): noa_duration = %x\n",__FUNCTION__,pwdinfo->noa_duration[i]);
+ rtw_write32(padapter, REG_NOA_DESC_DURATION, pwdinfo->noa_duration[i]);
+
+ //DBG_8192C("%s(): noa_interval = %x\n",__FUNCTION__,pwdinfo->noa_interval[i]);
+ rtw_write32(padapter, REG_NOA_DESC_INTERVAL, pwdinfo->noa_interval[i]);
+
+ //DBG_8192C("%s(): start_time = %x\n",__FUNCTION__,pwdinfo->noa_start_time[i]);
+ rtw_write32(padapter, REG_NOA_DESC_START, pwdinfo->noa_start_time[i]);
+
+ //DBG_8192C("%s(): noa_count = %x\n",__FUNCTION__,pwdinfo->noa_count[i]);
+ rtw_write8(padapter, REG_NOA_DESC_COUNT, pwdinfo->noa_count[i]);
+ }
+
+ if( (pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0) )
+ {
+ // rst p2p circuit
+ rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4));
+
+ p2p_ps_offload->Offload_En = 1;
+
+ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO))
+ {
+ p2p_ps_offload->role= 1;
+ p2p_ps_offload->AllStaSleep = 0;
+ }
+ else
+ {
+ p2p_ps_offload->role= 0;
+ }
+
+ p2p_ps_offload->discovery = 0;
+ }
+ break;
+ case P2P_PS_SCAN:
+ DBG_8192C("P2P_PS_SCAN \n");
+ p2p_ps_offload->discovery = 1;
+ break;
+ case P2P_PS_SCAN_DONE:
+ DBG_8192C("P2P_PS_SCAN_DONE \n");
+ p2p_ps_offload->discovery = 0;
+ pwdinfo->p2p_ps_state = P2P_PS_ENABLE;
+ break;
+ default:
+ break;
+ }
+
+ FillH2CCmd(padapter, P2P_PS_OFFLOAD_EID, 1, (u8 *)p2p_ps_offload);
+
+_func_exit_;
+
+}
+#endif //CONFIG_P2P_PS
+
+#ifdef CONFIG_IOL
+#include <rtw_iol.h>
+#ifdef CONFIG_USB_HCI
+#include <usb_ops.h>
+#endif
+int rtl8192c_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt)
+{
+ IO_OFFLOAD_LOC IoOffloadLoc;
+ u32 start_time = rtw_get_current_time();
+ u32 passing_time_ms;
+ u8 polling_ret;
+ int ret = _FAIL;
+
+ if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
+ goto exit;
+#ifdef CONFIG_USB_HCI
+ {
+ struct pkt_attrib *pattrib = &xmit_frame->attrib;
+ if(rtw_usb_bulk_size_boundary(adapter,TXDESC_SIZE+pattrib->last_txcmdsz))
+ {
+ if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS)
+ goto exit;
+ }
+ }
+#endif //CONFIG_USB_HCI
+
+
+ dump_mgntframe_and_wait(adapter, xmit_frame, max_wating_ms);
+
+ IoOffloadLoc.LocCmd = 0;
+ if(_SUCCESS != FillH2CCmd(adapter, H2C_92C_IO_OFFLOAD, sizeof(IO_OFFLOAD_LOC), (u8 *)&IoOffloadLoc))
+ goto exit;
+
+ //polling if the IO offloading is done
+ while( (passing_time_ms=rtw_get_passing_time_ms(start_time)) <= max_wating_ms) {
+ #if 0 //C2H
+ if(0xff == rtw_read8(adapter, REG_C2HEVT_CLEAR))
+ break;
+ #else// 0x1c3
+ if(0x00 != (polling_ret=rtw_read8(adapter, 0x1c3)))
+ break;
+ #endif
+ rtw_msleep_os(5);
+ }
+ #if 0 //debug
+ DBG_871X("IOL %s, polling_ret:0x%02x, 0x1c0=0x%08x, 0x1c4=0x%08x, 0x1cc=0x%08x, 0x1e8=0x%08x, 0x130=0x%08x, 0x134=0x%08x\n"
+ , polling_ret==0xff?"success":"error"
+ , polling_ret
+ , rtw_read32(adapter, 0x1c0)
+ , rtw_read32(adapter, 0x1c4)
+ , rtw_read32(adapter, 0x1cc)
+ , rtw_read32(adapter, 0x1e8)
+ , rtw_read32(adapter, 0x130)
+ , rtw_read32(adapter, 0x134)
+ );
+ rtw_write32(adapter, 0x1c0, 0x0);
+ #endif
+
+ if(polling_ret == 0xff)
+ ret =_SUCCESS;
+ else {
+ DBG_871X("IOL %s, polling_ret:0x%02x\n"
+ //", 0x1c0=0x%08x, 0x1c4=0x%08x, 0x1cc=0x%08x, 0x1e8=0x%08x, 0x130=0x%08x, 0x134=0x%08x\n"
+ , polling_ret==0xff?"success":"error"
+ , polling_ret
+ //, rtw_read32(adapter, 0x1c0)
+ //, rtw_read32(adapter, 0x1c4)
+ //, rtw_read32(adapter, 0x1cc)
+ //, rtw_read32(adapter, 0x1e8)
+ //, rtw_read32(adapter, 0x130)
+ //, rtw_read32(adapter, 0x134)
+ );
+ #if 0 //debug
+ rtw_write16(adapter, 0x1c4, 0x0000);
+ rtw_msleep_os(10);
+ DBG_871X("after reset, 0x1c4=0x%08x\n", rtw_read32(adapter, 0x1c4));
+ #endif
+
+ }
+
+ {
+ #if 0 //C2H
+ u32 c2h_evt;
+ int i;
+ c2h_evt = rtw_read32(adapter, REG_C2HEVT_MSG_NORMAL);
+ DBG_871X("%s io-offloading complete, in %ums: 0x%08x\n", __FUNCTION__, passing_time_ms, c2h_evt);
+ rtw_write8(adapter, REG_C2HEVT_CLEAR, 0x0);
+ #else// 0x1c3
+ //DBG_871X("%s IOF complete in %ums\n", __FUNCTION__, passing_time_ms);
+ rtw_write8(adapter, 0x1c3, 0x0);
+ #endif
+ }
+
+exit:
+ return ret;
+
+}
+#endif //CONFIG_IOL
+
+#ifdef CONFIG_TSF_RESET_OFFLOAD
+/*
+ ask FW to Reset sync register at Beacon early interrupt
+*/
+u8 rtl8723c_reset_tsf(_adapter *padapter, u8 reset_port )
+{
+ u8 buf[2];
+ u8 res=_SUCCESS;
+
+_func_enter_;
+ if (IFACE_PORT0==reset_port) {
+ buf[0] = 0x1; buf[1] = 0;
+
+ } else{
+ buf[0] = 0x0; buf[1] = 0x1;
+ }
+ FillH2CCmd(padapter, H2C_RESET_TSF, 2, buf);
+_func_exit_;
+
+ return res;
+}
+#endif // CONFIG_TSF_RESET_OFFLOAD
+
diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_dm.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_dm.c index 6d82a0f7ab9a..bab4925b0959 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_dm.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_dm.c @@ -1,578 +1,581 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -//============================================================ -// Description: -// -// This file is for 92CE/92CU dynamic mechanism only -// -// -//============================================================ -#define _RTL8723A_DM_C_ - -//============================================================ -// include files -//============================================================ -#include <drv_conf.h> -#include <osdep_service.h> -#include <drv_types.h> -#include <rtw_byteorder.h> - -#include <rtl8723a_hal.h> - -//============================================================ -// Global var -//============================================================ - - -static VOID -dm_CheckProtection( - IN PADAPTER Adapter - ) -{ -#if 0 - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - u1Byte CurRate, RateThreshold; - - if(pMgntInfo->pHTInfo->bCurBW40MHz) - RateThreshold = MGN_MCS1; - else - RateThreshold = MGN_MCS3; - - if(Adapter->TxStats.CurrentInitTxRate <= RateThreshold) - { - pMgntInfo->bDmDisableProtect = TRUE; - DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate); - } - else - { - pMgntInfo->bDmDisableProtect = FALSE; - DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate); - } -#endif -} - -static VOID -dm_CheckStatistics( - IN PADAPTER Adapter - ) -{ -#if 0 - if(!Adapter->MgntInfo.bMediaConnect) - return; - - //2008.12.10 tynli Add for getting Current_Tx_Rate_Reg flexibly. - rtw_hal_get_hwreg( Adapter, HW_VAR_INIT_TX_RATE, (pu1Byte)(&Adapter->TxStats.CurrentInitTxRate) ); - - // Calculate current Tx Rate(Successful transmited!!) - - // Calculate current Rx Rate(Successful received!!) - - //for tx tx retry count - rtw_hal_get_hwreg( Adapter, HW_VAR_RETRY_COUNT, (pu1Byte)(&Adapter->TxStats.NumTxRetryCount) ); -#endif -} - -static void dm_CheckPbcGPIO(_adapter *padapter) -{ - u8 tmp1byte; - u8 bPbcPressed = _FALSE; - - if(!padapter->registrypriv.hw_wps_pbc) - return; - -#ifdef CONFIG_USB_HCI - tmp1byte = rtw_read8(padapter, GPIO_IO_SEL); - tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT); - rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as output mode - - tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT); - rtw_write8(padapter, GPIO_IN, tmp1byte); //reset the floating voltage level - - tmp1byte = rtw_read8(padapter, GPIO_IO_SEL); - tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT); - rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as input mode - - tmp1byte =rtw_read8(padapter, GPIO_IN); - - if (tmp1byte == 0xff) - return ; - - if (tmp1byte&HAL_8192C_HW_GPIO_WPS_BIT) - { - bPbcPressed = _TRUE; - } -#else - tmp1byte = rtw_read8(padapter, GPIO_IN); - //RT_TRACE(COMP_IO, DBG_TRACE, ("dm_CheckPbcGPIO - %x\n", tmp1byte)); - - if (tmp1byte == 0xff || padapter->init_adpt_in_progress) - return ; - - if((tmp1byte&HAL_8192C_HW_GPIO_WPS_BIT)==0) - { - bPbcPressed = _TRUE; - } -#endif - - if( _TRUE == bPbcPressed) - { - // Here we only set bPbcPressed to true - // After trigger PBC, the variable will be set to false - DBG_8192C("CheckPbcGPIO - PBC is pressed\n"); - -#ifdef RTK_DMP_PLATFORM -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) - kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC); -#else - kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_NET_PBC); -#endif -#else - - if ( padapter->pid[0] == 0 ) - { // 0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver. - return; - } - -#ifdef PLATFORM_LINUX - rtw_signal_process(padapter->pid[0], SIGUSR1); -#endif -#endif - } -} - -#ifdef CONFIG_PCI_HCI -// -// Description: -// Perform interrupt migration dynamically to reduce CPU utilization. -// -// Assumption: -// 1. Do not enable migration under WIFI test. -// -// Created by Roger, 2010.03.05. -// -VOID -dm_InterruptMigration( - IN PADAPTER Adapter - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); - BOOLEAN bCurrentIntMt, bCurrentACIntDisable; - BOOLEAN IntMtToSet = _FALSE; - BOOLEAN ACIntToSet = _FALSE; - - - // Retrieve current interrupt migration and Tx four ACs IMR settings first. - bCurrentIntMt = pHalData->bInterruptMigration; - bCurrentACIntDisable = pHalData->bDisableTxInt; - - // - // <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics - // when interrupt migration is set before. 2010.03.05. - // - if(!Adapter->registrypriv.wifi_spec && - (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && - pmlmepriv->LinkDetectInfo.bHigherBusyTraffic) - { - IntMtToSet = _TRUE; - - // To check whether we should disable Tx interrupt or not. - if(pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic ) - ACIntToSet = _TRUE; - } - - //Update current settings. - if( bCurrentIntMt != IntMtToSet ){ - DBG_8192C("%s(): Update interrrupt migration(%d)\n",__FUNCTION__,IntMtToSet); - if(IntMtToSet) - { - // - // <Roger_Notes> Set interrrupt migration timer and corresponging Tx/Rx counter. - // timer 25ns*0xfa0=100us for 0xf packets. - // 2010.03.05. - // - rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);// 0x306:Rx, 0x307:Tx - pHalData->bInterruptMigration = IntMtToSet; - } - else - { - // Reset all interrupt migration settings. - rtw_write32(Adapter, REG_INT_MIG, 0); - pHalData->bInterruptMigration = IntMtToSet; - } - } - - /*if( bCurrentACIntDisable != ACIntToSet ){ - DBG_8192C("%s(): Update AC interrrupt(%d)\n",__FUNCTION__,ACIntToSet); - if(ACIntToSet) // Disable four ACs interrupts. - { - // - // <Roger_Notes> Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization. - // When extremely highly Rx OK occurs, we will disable Tx interrupts. - // 2010.03.05. - // - UpdateInterruptMask8192CE( Adapter, 0, RT_AC_INT_MASKS ); - pHalData->bDisableTxInt = ACIntToSet; - } - else// Enable four ACs interrupts. - { - UpdateInterruptMask8192CE( Adapter, RT_AC_INT_MASKS, 0 ); - pHalData->bDisableTxInt = ACIntToSet; - } - }*/ - -} - -#endif - -// -// Initialize GPIO setting registers -// -static void -dm_InitGPIOSetting( - IN PADAPTER Adapter - ) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - - u8 tmp1byte; - - tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG); - tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT); - - rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte); -} -//============================================================ -// functions -//============================================================ -static void Init_ODM_ComInfo_8723a(PADAPTER Adapter) -{ - - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - u8 cut_ver,fab_ver; - - // - // Init Value - // - _rtw_memset(pDM_Odm,0,sizeof(pDM_Odm)); - - pDM_Odm->Adapter = Adapter; - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PLATFORM,ODM_CE); - if(Adapter->interface_type == RTW_GSPI ) - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,ODM_ITRF_SDIO); - else - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);//RTL871X_HCI_TYPE - - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_IC_TYPE,ODM_RTL8723A); - - - if(IS_8723A_A_CUT(pHalData->VersionID)) - { - fab_ver = ODM_UMC; - cut_ver = ODM_CUT_A; - } - else if(IS_8723A_B_CUT(pHalData->VersionID)) - { - fab_ver = ODM_UMC; - cut_ver = ODM_CUT_B; - } - else - { - fab_ver = ODM_TSMC; - cut_ver = ODM_CUT_A; - } - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_FAB_VER,fab_ver); - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_CUT_VER,cut_ver); - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_MP_TEST_CHIP,IS_NORMAL_CHIP(pHalData->VersionID)); - -#ifdef CONFIG_USB_HCI - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BOARD_TYPE,pHalData->BoardType); - - if(pHalData->BoardType == BOARD_USB_High_PA){ - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_LNA,_TRUE); - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_PA,_TRUE); - } -#endif - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PATCH_ID,pHalData->CustomerID); - // ODM_CMNINFO_BINHCT_TEST only for MP Team - ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec); - - - if(pHalData->rf_type == RF_1T1R){ - ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T1R); - } - else if(pHalData->rf_type == RF_2T2R){ - ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_2T2R); - } - else if(pHalData->rf_type == RF_1T2R){ - ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T2R); - } -} -static void Update_ODM_ComInfo_8723a(PADAPTER Adapter) -{ - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; - struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; - struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - int i; - pdmpriv->InitODMFlag = ODM_BB_DIG | -#ifdef CONFIG_ODM_REFRESH_RAMASK - ODM_BB_RA_MASK | -#endif - ODM_BB_DYNAMIC_TXPWR | - ODM_BB_FA_CNT | - ODM_BB_RSSI_MONITOR | - ODM_BB_CCK_PD | - ODM_BB_PWR_SAVE | - ODM_MAC_EDCA_TURBO | - ODM_RF_TX_PWR_TRACK | - ODM_RF_CALIBRATION ; - // - // Pointer reference - // - //ODM_CMNINFO_MAC_PHY_MODE pHalData->MacPhyMode92D - // ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MAC_PHY_MODE,&(pDM_Odm->u1Byte_temp)); - - -#ifdef CONFIG_ANTENNA_DIVERSITY - if(pHalData->AntDivCfg) - pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV; -#endif - -#if (MP_DRIVER==1) - if (Adapter->registrypriv.mp_mode == 1) - { - pdmpriv->InitODMFlag = ODM_RF_CALIBRATION | - ODM_RF_TX_PWR_TRACK; - } -#endif//(MP_DRIVER==1) - - ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag); - - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_TX_UNI,&(Adapter->xmitpriv.tx_bytes)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_RX_UNI,&(Adapter->recvpriv.rx_bytes)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_WM_MODE,&(pmlmeext->cur_wireless_mode)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SEC_CHNL_OFFSET,&(pHalData->nCur40MhzPrimeSC)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SEC_MODE,&(Adapter->securitypriv.dot11PrivacyAlgrthm)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BW,&(pHalData->CurrentChannelBW )); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_CHNL,&( pHalData->CurrentChannel)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_NET_CLOSED,&( Adapter->net_closed)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MP_MODE,&(Adapter->registrypriv.mp_mode)); - - //================= only for 8192D ================= - /* - //pHalData->CurrentBandType92D - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u1Byte_temp)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u1Byte_temp)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BUDDY_ADAPTOR,&(pDM_Odm->PADAPTER_temp)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u1Byte_temp)); - //================= only for 8192D ================= - // driver havn't those variable now - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u1Byte_temp)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u1Byte_temp)); - */ - - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SCAN,&(pmlmepriv->bScanInProcess)); - ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_POWER_SAVING,&(pwrctrlpriv->bpower_saving)); - - - for(i=0; i< NUM_STA; i++) - { - //pDM_Odm->pODM_StaInfo[i] = NULL; - ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS,i,NULL); - } -} - -void -rtl8723a_InitHalDm( - IN PADAPTER Adapter - ) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - - u8 i; - - pdmpriv->DM_Type = DM_Type_ByDriver; - pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE; - -#ifdef CONFIG_BT_COEXIST - pdmpriv->DMFlag |= DYNAMIC_FUNC_BT; -// btdm_InitBtCoexistDM(Adapter); // Move to BT_CoexistMechanism() -#endif - pdmpriv->InitDMFlag = pdmpriv->DMFlag; - - Update_ODM_ComInfo_8723a(Adapter); - ODM_DMInit(pDM_Odm); - // Save REG_INIDATA_RATE_SEL value for TXDESC. - for(i = 0 ; i<32 ; i++) - { - pdmpriv->INIDATA_RATE[i] = rtw_read8(Adapter, REG_INIDATA_RATE_SEL+i) & 0x3f; - } - -} - -VOID -rtl8723a_HalDmWatchDog( - IN PADAPTER Adapter - ) -{ - BOOLEAN bFwCurrentInPSMode = _FALSE; - BOOLEAN bFwPSAwake = _TRUE; - u8 hw_init_completed = _FALSE; - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; -#ifdef CONFIG_CONCURRENT_MODE - PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter; -#endif //CONFIG_CONCURRENT_MODE - - hw_init_completed = Adapter->hw_init_completed; - - if (hw_init_completed == _FALSE) - goto skip_dm; - -#ifdef CONFIG_LPS - #ifdef CONFIG_CONCURRENT_MODE - if (Adapter->iface_type != IFACE_PORT0 && pbuddy_adapter) { - bFwCurrentInPSMode = pbuddy_adapter->pwrctrlpriv.bFwCurrentInPSMode; - rtw_hal_get_hwreg(pbuddy_adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake)); - } else - #endif //CONFIG_CONCURRENT_MODE - { - bFwCurrentInPSMode = Adapter->pwrctrlpriv.bFwCurrentInPSMode; - rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake)); - } -#endif - -#ifdef CONFIG_P2P_PS - // Fw is under p2p powersaving mode, driver should stop dynamic mechanism. - // modifed by thomas. 2011.06.11. - if(Adapter->wdinfo.p2p_ps_mode) - bFwPSAwake = _FALSE; -#endif //CONFIG_P2P_PS - - if( (hw_init_completed == _TRUE) - && ((!bFwCurrentInPSMode) && bFwPSAwake)) - { - // - // Calculate Tx/Rx statistics. - // - dm_CheckStatistics(Adapter); - - -#ifdef CONFIG_CONCURRENT_MODE - if(Adapter->adapter_type > PRIMARY_ADAPTER) - goto _record_initrate; -#endif - - // - // Dynamically switch RTS/CTS protection. - // - //dm_CheckProtection(Adapter); - -#ifdef CONFIG_PCI_HCI - // 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput. - // Tx Migration settings. - //dm_InterruptMigration(Adapter); - - //if(Adapter->HalFunc.TxCheckStuckHandler(Adapter)) - // PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem)); -#endif -_record_initrate: - - // Read REG_INIDATA_RATE_SEL value for TXDESC. - if(check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) - { - pdmpriv->INIDATA_RATE[0] = rtw_read8(Adapter, REG_INIDATA_RATE_SEL) & 0x3f; - } - else - { - u8 i; - for(i=1 ; i < (Adapter->stapriv.asoc_sta_count + 1); i++) - { - pdmpriv->INIDATA_RATE[i] = rtw_read8(Adapter, (REG_INIDATA_RATE_SEL+i)) & 0x3f; - } - } - } - - - //ODM - if (hw_init_completed == _TRUE) - { - u8 bLinked=_FALSE; - - #ifdef CONFIG_DISABLE_ODM - pHalData->odmpriv.SupportAbility = 0; - #endif - - if(rtw_linked_check(Adapter)) - bLinked = _TRUE; - -#ifdef CONFIG_CONCURRENT_MODE - if(pbuddy_adapter && rtw_linked_check(pbuddy_adapter)) - bLinked = _TRUE; -#endif //CONFIG_CONCURRENT_MODE - - ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_LINK, bLinked); - ODM_DMWatchdog(&pHalData->odmpriv); - - } - -skip_dm: - - // Check GPIO to determine current RF on/off and Pbc status. - // Check Hardware Radio ON/OFF or not -#ifdef CONFIG_PCI_HCI - if(pHalData->bGpioHwWpsPbc) -#endif - { - dm_CheckPbcGPIO(Adapter); // Add by hpfan 2008-03-11 - } - -} - -void rtl8723a_init_dm_priv(IN PADAPTER Adapter) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - PDM_ODM_T podmpriv = &pHalData->odmpriv; - _rtw_memset(pdmpriv, 0, sizeof(struct dm_priv)); - Init_ODM_ComInfo_8723a(Adapter); -#ifdef CONFIG_SW_ANTENNA_DIVERSITY - //_init_timer(&(pdmpriv->SwAntennaSwitchTimer), Adapter->pnetdev , odm_SW_AntennaSwitchCallback, Adapter); - ODM_InitAllTimers(podmpriv ); -#endif -} - -void rtl8723a_deinit_dm_priv(IN PADAPTER Adapter) -{ - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - PDM_ODM_T podmpriv = &pHalData->odmpriv; -#ifdef CONFIG_SW_ANTENNA_DIVERSITY - //_cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer); - ODM_CancelAllTimers(podmpriv); -#endif -} - +/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+//============================================================
+// Description:
+//
+// This file is for 92CE/92CU dynamic mechanism only
+//
+//
+//============================================================
+#define _RTL8723A_DM_C_
+
+//============================================================
+// include files
+//============================================================
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtw_byteorder.h>
+
+#include <rtl8723a_hal.h>
+
+//============================================================
+// Global var
+//============================================================
+
+
+static VOID
+dm_CheckProtection(
+ IN PADAPTER Adapter
+ )
+{
+#if 0
+ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
+ u1Byte CurRate, RateThreshold;
+
+ if(pMgntInfo->pHTInfo->bCurBW40MHz)
+ RateThreshold = MGN_MCS1;
+ else
+ RateThreshold = MGN_MCS3;
+
+ if(Adapter->TxStats.CurrentInitTxRate <= RateThreshold)
+ {
+ pMgntInfo->bDmDisableProtect = TRUE;
+ DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
+ }
+ else
+ {
+ pMgntInfo->bDmDisableProtect = FALSE;
+ DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate);
+ }
+#endif
+}
+
+static VOID
+dm_CheckStatistics(
+ IN PADAPTER Adapter
+ )
+{
+#if 0
+ if(!Adapter->MgntInfo.bMediaConnect)
+ return;
+
+ //2008.12.10 tynli Add for getting Current_Tx_Rate_Reg flexibly.
+ rtw_hal_get_hwreg( Adapter, HW_VAR_INIT_TX_RATE, (pu1Byte)(&Adapter->TxStats.CurrentInitTxRate) );
+
+ // Calculate current Tx Rate(Successful transmited!!)
+
+ // Calculate current Rx Rate(Successful received!!)
+
+ //for tx tx retry count
+ rtw_hal_get_hwreg( Adapter, HW_VAR_RETRY_COUNT, (pu1Byte)(&Adapter->TxStats.NumTxRetryCount) );
+#endif
+}
+
+static void dm_CheckPbcGPIO(_adapter *padapter)
+{
+ u8 tmp1byte;
+ u8 bPbcPressed = _FALSE;
+
+ if(!padapter->registrypriv.hw_wps_pbc)
+ return;
+
+#ifdef CONFIG_USB_HCI
+ tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
+ tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT);
+ rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as output mode
+
+ tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
+ rtw_write8(padapter, GPIO_IN, tmp1byte); //reset the floating voltage level
+
+ tmp1byte = rtw_read8(padapter, GPIO_IO_SEL);
+ tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT);
+ rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as input mode
+
+ tmp1byte =rtw_read8(padapter, GPIO_IN);
+
+ if (tmp1byte == 0xff)
+ return ;
+
+ if (tmp1byte&HAL_8192C_HW_GPIO_WPS_BIT)
+ {
+ bPbcPressed = _TRUE;
+ }
+#else
+ tmp1byte = rtw_read8(padapter, GPIO_IN);
+ //RT_TRACE(COMP_IO, DBG_TRACE, ("dm_CheckPbcGPIO - %x\n", tmp1byte));
+
+ if (tmp1byte == 0xff || padapter->init_adpt_in_progress)
+ return ;
+
+ if((tmp1byte&HAL_8192C_HW_GPIO_WPS_BIT)==0)
+ {
+ bPbcPressed = _TRUE;
+ }
+#endif
+
+ if( _TRUE == bPbcPressed)
+ {
+ // Here we only set bPbcPressed to true
+ // After trigger PBC, the variable will be set to false
+ DBG_8192C("CheckPbcGPIO - PBC is pressed\n");
+
+#ifdef RTK_DMP_PLATFORM
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12))
+ kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC);
+#else
+ kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_NET_PBC);
+#endif
+#else
+
+ if ( padapter->pid[0] == 0 )
+ { // 0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver.
+ return;
+ }
+
+#ifdef PLATFORM_LINUX
+ rtw_signal_process(padapter->pid[0], SIGUSR1);
+#endif
+#endif
+ }
+}
+
+#ifdef CONFIG_PCI_HCI
+//
+// Description:
+// Perform interrupt migration dynamically to reduce CPU utilization.
+//
+// Assumption:
+// 1. Do not enable migration under WIFI test.
+//
+// Created by Roger, 2010.03.05.
+//
+VOID
+dm_InterruptMigration(
+ IN PADAPTER Adapter
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv);
+ BOOLEAN bCurrentIntMt, bCurrentACIntDisable;
+ BOOLEAN IntMtToSet = _FALSE;
+ BOOLEAN ACIntToSet = _FALSE;
+
+
+ // Retrieve current interrupt migration and Tx four ACs IMR settings first.
+ bCurrentIntMt = pHalData->bInterruptMigration;
+ bCurrentACIntDisable = pHalData->bDisableTxInt;
+
+ //
+ // <Roger_Notes> Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics
+ // when interrupt migration is set before. 2010.03.05.
+ //
+ if(!Adapter->registrypriv.wifi_spec &&
+ (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) &&
+ pmlmepriv->LinkDetectInfo.bHigherBusyTraffic)
+ {
+ IntMtToSet = _TRUE;
+
+ // To check whether we should disable Tx interrupt or not.
+ if(pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic )
+ ACIntToSet = _TRUE;
+ }
+
+ //Update current settings.
+ if( bCurrentIntMt != IntMtToSet ){
+ DBG_8192C("%s(): Update interrrupt migration(%d)\n",__FUNCTION__,IntMtToSet);
+ if(IntMtToSet)
+ {
+ //
+ // <Roger_Notes> Set interrrupt migration timer and corresponging Tx/Rx counter.
+ // timer 25ns*0xfa0=100us for 0xf packets.
+ // 2010.03.05.
+ //
+ rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);// 0x306:Rx, 0x307:Tx
+ pHalData->bInterruptMigration = IntMtToSet;
+ }
+ else
+ {
+ // Reset all interrupt migration settings.
+ rtw_write32(Adapter, REG_INT_MIG, 0);
+ pHalData->bInterruptMigration = IntMtToSet;
+ }
+ }
+
+ /*if( bCurrentACIntDisable != ACIntToSet ){
+ DBG_8192C("%s(): Update AC interrrupt(%d)\n",__FUNCTION__,ACIntToSet);
+ if(ACIntToSet) // Disable four ACs interrupts.
+ {
+ //
+ // <Roger_Notes> Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization.
+ // When extremely highly Rx OK occurs, we will disable Tx interrupts.
+ // 2010.03.05.
+ //
+ UpdateInterruptMask8192CE( Adapter, 0, RT_AC_INT_MASKS );
+ pHalData->bDisableTxInt = ACIntToSet;
+ }
+ else// Enable four ACs interrupts.
+ {
+ UpdateInterruptMask8192CE( Adapter, RT_AC_INT_MASKS, 0 );
+ pHalData->bDisableTxInt = ACIntToSet;
+ }
+ }*/
+
+}
+
+#endif
+
+//
+// Initialize GPIO setting registers
+//
+static void
+dm_InitGPIOSetting(
+ IN PADAPTER Adapter
+ )
+{
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
+
+ u8 tmp1byte;
+
+ tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG);
+ tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
+
+ rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte);
+}
+//============================================================
+// functions
+//============================================================
+static void Init_ODM_ComInfo_8723a(PADAPTER Adapter)
+{
+
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
+ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+ u8 cut_ver,fab_ver;
+
+ //
+ // Init Value
+ //
+ _rtw_memset(pDM_Odm,0,sizeof(pDM_Odm));
+
+ pDM_Odm->Adapter = Adapter;
+ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PLATFORM,ODM_CE);
+ if(Adapter->interface_type == RTW_GSPI )
+ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,ODM_ITRF_SDIO);
+ else
+ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_INTERFACE,Adapter->interface_type);//RTL871X_HCI_TYPE
+
+ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_IC_TYPE,ODM_RTL8723A);
+
+
+ if(IS_8723A_A_CUT(pHalData->VersionID))
+ {
+ fab_ver = ODM_UMC;
+ cut_ver = ODM_CUT_A;
+ }
+ else if(IS_8723A_B_CUT(pHalData->VersionID))
+ {
+ fab_ver = ODM_UMC;
+ cut_ver = ODM_CUT_B;
+ }
+ else
+ {
+ fab_ver = ODM_TSMC;
+ cut_ver = ODM_CUT_A;
+ }
+ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_FAB_VER,fab_ver);
+ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_CUT_VER,cut_ver);
+ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_MP_TEST_CHIP,IS_NORMAL_CHIP(pHalData->VersionID));
+
+#ifdef CONFIG_USB_HCI
+ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BOARD_TYPE,pHalData->BoardType);
+
+ if(pHalData->BoardType == BOARD_USB_High_PA){
+ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_LNA,_TRUE);
+ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_EXT_PA,_TRUE);
+ }
+#endif
+ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_PATCH_ID,pHalData->CustomerID);
+ // ODM_CMNINFO_BINHCT_TEST only for MP Team
+ ODM_CmnInfoInit(pDM_Odm,ODM_CMNINFO_BWIFI_TEST,Adapter->registrypriv.wifi_spec);
+
+
+ if(pHalData->rf_type == RF_1T1R){
+ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T1R);
+ }
+ else if(pHalData->rf_type == RF_2T2R){
+ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_2T2R);
+ }
+ else if(pHalData->rf_type == RF_1T2R){
+ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_RF_TYPE,ODM_1T2R);
+ }
+}
+static void Update_ODM_ComInfo_8723a(PADAPTER Adapter)
+{
+ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
+ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
+ struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
+ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+ struct dm_priv *pdmpriv = &pHalData->dmpriv;
+ int i;
+
+ pdmpriv->InitODMFlag = 0
+ | ODM_BB_DIG
+#ifdef CONFIG_ODM_REFRESH_RAMASK
+ | ODM_BB_RA_MASK
+#endif
+ | ODM_BB_DYNAMIC_TXPWR
+ | ODM_BB_FA_CNT
+ | ODM_BB_RSSI_MONITOR
+ | ODM_BB_CCK_PD
+ | ODM_BB_PWR_SAVE
+ | ODM_MAC_EDCA_TURBO
+ | ODM_RF_TX_PWR_TRACK
+ | ODM_RF_CALIBRATION
+#ifdef CONFIG_ODM_ADAPTIVITY
+ | ODM_BB_ADAPTIVITY
+#endif
+ ;
+
+#ifdef CONFIG_ANTENNA_DIVERSITY
+ if(pHalData->AntDivCfg)
+ pdmpriv->InitODMFlag |= ODM_BB_ANT_DIV;
+#endif
+
+#if (MP_DRIVER==1)
+ if (Adapter->registrypriv.mp_mode == 1) {
+ pdmpriv->InitODMFlag = 0
+ | ODM_RF_CALIBRATION
+ | ODM_RF_TX_PWR_TRACK
+ ;
+ }
+#endif//(MP_DRIVER==1)
+
+#ifdef CONFIG_DISABLE_ODM
+ pdmpriv->InitODMFlag = 0;
+#endif//CONFIG_DISABLE_ODM
+
+ //
+ // Pointer reference
+ //
+ //ODM_CMNINFO_MAC_PHY_MODE pHalData->MacPhyMode92D
+ // ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MAC_PHY_MODE,&(pDM_Odm->u1Byte_temp));
+
+ ODM_CmnInfoUpdate(pDM_Odm,ODM_CMNINFO_ABILITY,pdmpriv->InitODMFlag);
+
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_TX_UNI,&(Adapter->xmitpriv.tx_bytes));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_RX_UNI,&(Adapter->recvpriv.rx_bytes));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_WM_MODE,&(pmlmeext->cur_wireless_mode));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SEC_CHNL_OFFSET,&(pHalData->nCur40MhzPrimeSC));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SEC_MODE,&(Adapter->securitypriv.dot11PrivacyAlgrthm));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BW,&(pHalData->CurrentChannelBW ));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_CHNL,&( pHalData->CurrentChannel));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_NET_CLOSED,&( Adapter->net_closed));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_MP_MODE,&(Adapter->registrypriv.mp_mode));
+
+ //================= only for 8192D =================
+ /*
+ //pHalData->CurrentBandType92D
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BAND,&(pDM_Odm->u1Byte_temp));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_GET_VALUE,&(pDM_Odm->u1Byte_temp));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BUDDY_ADAPTOR,&(pDM_Odm->PADAPTER_temp));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_DMSP_IS_MASTER,&(pDM_Odm->u1Byte_temp));
+ //================= only for 8192D =================
+ // driver havn't those variable now
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_OPERATION,&(pDM_Odm->u1Byte_temp));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_BT_DISABLE_EDCA,&(pDM_Odm->u1Byte_temp));
+ */
+
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_SCAN,&(pmlmepriv->bScanInProcess));
+ ODM_CmnInfoHook(pDM_Odm,ODM_CMNINFO_POWER_SAVING,&(pwrctrlpriv->bpower_saving));
+
+
+ for(i=0; i< NUM_STA; i++)
+ {
+ //pDM_Odm->pODM_StaInfo[i] = NULL;
+ ODM_CmnInfoPtrArrayHook(pDM_Odm, ODM_CMNINFO_STA_STATUS,i,NULL);
+ }
+}
+
+void
+rtl8723a_InitHalDm(
+ IN PADAPTER Adapter
+ )
+{
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
+ struct dm_priv *pdmpriv = &pHalData->dmpriv;
+ PDM_ODM_T pDM_Odm = &(pHalData->odmpriv);
+
+ u8 i;
+
+ pdmpriv->DM_Type = DM_Type_ByDriver;
+ pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE;
+
+#ifdef CONFIG_BT_COEXIST
+ pdmpriv->DMFlag |= DYNAMIC_FUNC_BT;
+// btdm_InitBtCoexistDM(Adapter); // Move to BT_CoexistMechanism()
+#endif
+ pdmpriv->InitDMFlag = pdmpriv->DMFlag;
+
+ Update_ODM_ComInfo_8723a(Adapter);
+ ODM_DMInit(pDM_Odm);
+ // Save REG_INIDATA_RATE_SEL value for TXDESC.
+ for(i = 0 ; i<32 ; i++)
+ {
+ pdmpriv->INIDATA_RATE[i] = rtw_read8(Adapter, REG_INIDATA_RATE_SEL+i) & 0x3f;
+ }
+
+}
+
+VOID
+rtl8723a_HalDmWatchDog(
+ IN PADAPTER Adapter
+ )
+{
+ BOOLEAN bFwCurrentInPSMode = _FALSE;
+ BOOLEAN bFwPSAwake = _TRUE;
+ u8 hw_init_completed = _FALSE;
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
+ struct dm_priv *pdmpriv = &pHalData->dmpriv;
+#ifdef CONFIG_CONCURRENT_MODE
+ PADAPTER pbuddy_adapter = Adapter->pbuddy_adapter;
+#endif //CONFIG_CONCURRENT_MODE
+
+ hw_init_completed = Adapter->hw_init_completed;
+
+ if (hw_init_completed == _FALSE)
+ goto skip_dm;
+
+#ifdef CONFIG_LPS
+ bFwCurrentInPSMode = adapter_to_pwrctl(Adapter)->bFwCurrentInPSMode;
+ rtw_hal_get_hwreg(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake));
+#endif
+
+#ifdef CONFIG_P2P_PS
+ // Fw is under p2p powersaving mode, driver should stop dynamic mechanism.
+ // modifed by thomas. 2011.06.11.
+ if(Adapter->wdinfo.p2p_ps_mode)
+ bFwPSAwake = _FALSE;
+#endif //CONFIG_P2P_PS
+
+ if( (hw_init_completed == _TRUE)
+ && ((!bFwCurrentInPSMode) && bFwPSAwake))
+ {
+ //
+ // Calculate Tx/Rx statistics.
+ //
+ dm_CheckStatistics(Adapter);
+
+
+#ifdef CONFIG_CONCURRENT_MODE
+ if(Adapter->adapter_type > PRIMARY_ADAPTER)
+ goto _record_initrate;
+#endif
+
+ //
+ // Dynamically switch RTS/CTS protection.
+ //
+ //dm_CheckProtection(Adapter);
+
+#ifdef CONFIG_PCI_HCI
+ // 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput.
+ // Tx Migration settings.
+ //dm_InterruptMigration(Adapter);
+
+ //if(Adapter->HalFunc.TxCheckStuckHandler(Adapter))
+ // PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem));
+#endif
+_record_initrate:
+
+ // Read REG_INIDATA_RATE_SEL value for TXDESC.
+ if(check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE)
+ {
+ pdmpriv->INIDATA_RATE[0] = rtw_read8(Adapter, REG_INIDATA_RATE_SEL) & 0x3f;
+ }
+ else
+ {
+ u8 i;
+ for(i=1 ; i < (Adapter->stapriv.asoc_sta_count + 1); i++)
+ {
+ pdmpriv->INIDATA_RATE[i] = rtw_read8(Adapter, (REG_INIDATA_RATE_SEL+i)) & 0x3f;
+ }
+ }
+ }
+
+
+ //ODM
+ if (hw_init_completed == _TRUE)
+ {
+ u8 bLinked=_FALSE;
+
+ #ifdef CONFIG_DISABLE_ODM
+ pHalData->odmpriv.SupportAbility = 0;
+ #endif
+
+ if(rtw_linked_check(Adapter))
+ bLinked = _TRUE;
+
+#ifdef CONFIG_CONCURRENT_MODE
+ if(pbuddy_adapter && rtw_linked_check(pbuddy_adapter))
+ bLinked = _TRUE;
+#endif //CONFIG_CONCURRENT_MODE
+
+ ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_LINK, bLinked);
+ ODM_DMWatchdog(&pHalData->odmpriv);
+
+ }
+
+skip_dm:
+
+ // Check GPIO to determine current RF on/off and Pbc status.
+ // Check Hardware Radio ON/OFF or not
+#ifdef CONFIG_PCI_HCI
+ if(pHalData->bGpioHwWpsPbc)
+#endif
+ {
+ dm_CheckPbcGPIO(Adapter); // Add by hpfan 2008-03-11
+ }
+
+}
+
+void rtl8723a_init_dm_priv(IN PADAPTER Adapter)
+{
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
+ struct dm_priv *pdmpriv = &pHalData->dmpriv;
+ PDM_ODM_T podmpriv = &pHalData->odmpriv;
+ _rtw_memset(pdmpriv, 0, sizeof(struct dm_priv));
+ Init_ODM_ComInfo_8723a(Adapter);
+#ifdef CONFIG_SW_ANTENNA_DIVERSITY
+ //_init_timer(&(pdmpriv->SwAntennaSwitchTimer), Adapter->pnetdev , odm_SW_AntennaSwitchCallback, Adapter);
+ ODM_InitAllTimers(podmpriv );
+#endif
+}
+
+void rtl8723a_deinit_dm_priv(IN PADAPTER Adapter)
+{
+ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
+ struct dm_priv *pdmpriv = &pHalData->dmpriv;
+ PDM_ODM_T podmpriv = &pHalData->odmpriv;
+#ifdef CONFIG_SW_ANTENNA_DIVERSITY
+ //_cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer);
+ ODM_CancelAllTimers(podmpriv);
+#endif
+}
+
diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_hal_init.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_hal_init.c index 2a002f5e5f7c..aef17c95853c 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_hal_init.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_hal_init.c @@ -37,10 +37,6 @@ _FWDownloadEnable( if(enable) { - // 8051 enable - tmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); - rtw_write8(padapter, REG_SYS_FUNC_EN+1, tmp|0x04); - // MCU firmware download enable. tmp = rtw_read8(padapter, REG_MCUFWDL); rtw_write8(padapter, REG_MCUFWDL, tmp|0x01); @@ -230,6 +226,29 @@ exit: return ret; } +void _8051Reset8723A(PADAPTER padapter) +{ + u8 tmp; + + // Reset 8051 + tmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); + rtw_write8(padapter, REG_SYS_FUNC_EN + 1, tmp & (~BIT2)); + + // Reset wrapper + tmp = rtw_read8(padapter, REG_RSV_CTRL + 1); + rtw_write8(padapter, REG_RSV_CTRL + 1, tmp & (~BIT0)); + + // Enable wrapper + tmp = rtw_read8(padapter, REG_RSV_CTRL + 1); + rtw_write8(padapter, REG_RSV_CTRL + 1, tmp | BIT0); + + // 8051 enable + tmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); + rtw_write8(padapter, REG_SYS_FUNC_EN+1, tmp|BIT2); + + DBG_871X("=====> _8051Reset8723A(): 8051 reset success .\n"); +} + static s32 _FWFreeToGo(PADAPTER padapter) { u32 counter = 0; @@ -242,7 +261,7 @@ static s32 _FWFreeToGo(PADAPTER padapter) } while (counter++ < POLLING_READY_TIMEOUT_COUNT); if (counter >= POLLING_READY_TIMEOUT_COUNT) { - RT_TRACE(_module_hal_init_c_, _drv_err_, ("%s: chksum report fail! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32)); + DBG_871X("%s: chksum report fail! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32); return _FAIL; } RT_TRACE(_module_hal_init_c_, _drv_info_, ("%s: Checksum report OK! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32)); @@ -252,6 +271,8 @@ static s32 _FWFreeToGo(PADAPTER padapter) value32 &= ~WINTINI_RDY; rtw_write32(padapter, REG_MCUFWDL, value32); + _8051Reset8723A(padapter); + // polling for FW ready counter = 0; do { @@ -263,7 +284,7 @@ static s32 _FWFreeToGo(PADAPTER padapter) rtw_udelay_os(5); } while (counter++ < POLLING_READY_TIMEOUT_COUNT); - RT_TRACE(_module_hal_init_c_, _drv_err_, ("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32)); + DBG_871X("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n", __FUNCTION__, value32); return _FAIL; } @@ -412,7 +433,7 @@ int _WriteBTFWtoTxPktBuf8723A( //BT patch is big, we should set 0x209 < 0x40 suggested from Gimmy RT_TRACE(_module_mp_, _drv_info_,("0x209:%x\n", PlatformEFIORead1Byte(Adapter, REG_TDECTRL+1)));//209 < 0x40 -#if 0 +#if 0//def CONFIG_RTL8723A_SDIO PlatformEFIOWrite1Byte(Adapter, REG_TDECTRL+1, 0x30); RT_TRACE(_module_mp_, _drv_info_,("0x209:%x\n", PlatformEFIORead1Byte(Adapter, REG_TDECTRL+1))); @@ -656,6 +677,7 @@ FirmwareDownloadBT(IN PADAPTER Adapter, PRT_FIRMWARE_8723A pFirmware) u1Byte *pBTFirmwareBuf; u4Byte BTFirmwareLen; + u8 i; // // Patch BT Fw. Download BT RAM code to Tx packet buffer. Added by tynli. 2011.10. // Only for 8723AE for Toshiba. Suggested by SD1 Jackie. @@ -667,7 +689,13 @@ FirmwareDownloadBT(IN PADAPTER Adapter, PRT_FIRMWARE_8723A pFirmware) DBG_871X("BT Firmware is ready!!\n"); return _FAIL; }*/ - + PlatformEFIOWrite1Byte(Adapter, 0xCC, 0x2d); + PlatformEFIOWrite4Byte(Adapter, 0x68, 0xa005000c); + rtw_msleep_os(5); + PlatformEFIOWrite4Byte(Adapter, 0x68, 0xb005000c); + PlatformEFIOWrite1Byte(Adapter, 0xCC, 0x29); + for(i=0; i<10; i++) + rtw_msleep_os(100); BTFwImage = (pu1Byte)Rtl8723EFwBTImgArray; BTFwImageLen = Rtl8723EBTImgArrayLength; DBG_871X("BT Firmware is size= %zu!!\n",sizeof(Rtl8723EFwBTImgArray)); @@ -701,33 +729,34 @@ FirmwareDownloadBT(IN PADAPTER Adapter, PRT_FIRMWARE_8723A pFirmware) //for h2c cam here should be set to true Adapter->bFWReady = _TRUE; DBG_871X("FirmwareDownloadBT to _WriteBTFWtoTxPktBuf8723A !\n"); -#if 1 +#ifdef CONFIG_RTL8723A_SDIO + rtStatus = _WriteBTFWtoTxPktBuf8723A(Adapter, pBTFirmwareBuf, BTFirmwareLen, 0); +#else //rtStatus = _WriteBTFWtoTxPktBuf8723A(Adapter, pBTFirmwareBuf, BTFirmwareLen); rtStatus = _WriteBTFWtoTxPktBuf8723A(Adapter, pBTFirmwareBuf+(4096*3), (BTFirmwareLen-(4096*3)), 1); if(rtStatus != _SUCCESS) { - DBG_871X("BT Firmware download to Tx packet buffer first fail!\n"); + DBG_871X("BT Firmware download to Tx packet buffer first fail! \n"); return rtStatus; } rtStatus = _WriteBTFWtoTxPktBuf8723A(Adapter, pBTFirmwareBuf+(4096*2), 4096, 2); if(rtStatus != _SUCCESS) { - DBG_871X("BT Firmware download to Tx packet buffer second fail!\n"); + DBG_871X("BT Firmware download to Tx packet buffer second fail! \n"); return rtStatus; } rtStatus = _WriteBTFWtoTxPktBuf8723A(Adapter, pBTFirmwareBuf+(4096), 4096, 3); if(rtStatus != _SUCCESS) { - DBG_871X("BT Firmware download to Tx packet buffer third fail!\n"); + DBG_871X("BT Firmware download to Tx packet buffer third fail! \n"); return rtStatus; } rtStatus = _WriteBTFWtoTxPktBuf8723A(Adapter, pBTFirmwareBuf, 4096, 4); - - +#endif if(rtStatus != _SUCCESS) { - RT_TRACE(_module_mp_, _drv_info_,("BT Firmware download to Tx packet buffer fail!\n")); - DBG_871X("BT Firmware download to Tx packet buffer fail!\n"); + RT_TRACE(_module_mp_, _drv_info_,("BT Firmware download to Tx packet buffer four fail! \n")); + DBG_871X("BT Firmware download to Tx packet buffer four fail!!\n"); } else { @@ -735,7 +764,7 @@ FirmwareDownloadBT(IN PADAPTER Adapter, PRT_FIRMWARE_8723A pFirmware) SetFwBTFwPatchCmd(Adapter, (u2Byte)BTFirmwareLen); _CheckWLANFwPatchBTFwReady(Adapter); } -#endif + DBG_871X("<===FirmwareDownloadBT(),return %s!\n",rtStatus?"SUCCESS":"FAIL"); return rtStatus; @@ -970,7 +999,7 @@ void rtl8723a_InitializeFirmwareVars(PADAPTER padapter) PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); // Init Fw LPS related. - padapter->pwrctrlpriv.bFwCurrentInPSMode = _FALSE; + adapter_to_pwrctl(padapter)->bFwCurrentInPSMode = _FALSE; // Init H2C counter. by tynli. 2009.12.09. pHalData->LastHMEBoxNum = 0; @@ -982,10 +1011,13 @@ void rtl8723a_InitializeFirmwareVars(PADAPTER padapter) static void rtl8723a_free_hal_data(PADAPTER padapter) { _func_enter_; - if (padapter->HalData) { + + if(padapter->HalData) + { rtw_mfree(padapter->HalData, sizeof(HAL_DATA_TYPE)); padapter->HalData = NULL; } + _func_exit_; } @@ -2589,14 +2621,6 @@ void rtl8723a_SetHalODMVar( case HAL_ODM_STA_INFO: { struct sta_info *psta = (struct sta_info *)pValue1; - #ifdef CONFIG_CONCURRENT_MODE - //get Primary adapter's odmpriv - if(Adapter->adapter_type > PRIMARY_ADAPTER && Adapter->pbuddy_adapter){ - pHalData = GET_HAL_DATA(Adapter->pbuddy_adapter); - podmpriv = &pHalData->odmpriv; - } - #endif - if(bSet){ DBG_8192C("Set STA_(%d) info\n",psta->mac_id); ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS,psta->mac_id,psta); @@ -2721,9 +2745,7 @@ void rtl8723a_set_hal_ops(struct hal_ops *pHalFunc) pHalFunc->SetBeaconRelatedRegistersHandler = &rtl8723a_SetBeaconRelatedRegisters; pHalFunc->Add_RateATid = &rtl8192c_Add_RateATid; -#ifdef CONFIG_CONCURRENT_MODE - pHalFunc->clone_haldata = &rtl8723a_clone_haldata; -#endif + pHalFunc->run_thread= &rtl8723a_start_thread; pHalFunc->cancel_thread= &rtl8723a_stop_thread; @@ -2831,7 +2853,7 @@ void rtl8723a_init_default_value(PADAPTER padapter) // init default value pHalData->fw_ractrl = _FALSE; pHalData->bIQKInitialized = _FALSE; - if (!padapter->pwrctrlpriv.bkeepfwalive) + if (!adapter_to_pwrctl(padapter)->bkeepfwalive) pHalData->LastHMEBoxNum = 0; pHalData->bIQKInitialized = _FALSE; @@ -3905,6 +3927,33 @@ Hal_InitChannelPlan( #endif } +#ifdef CONFIG_RF_GAIN_OFFSET +void Hal_ReadRFGainOffset( + IN PADAPTER Adapter, + IN u8* PROMContent, + IN BOOLEAN AutoloadFail) +{ + // + // BB_RF Gain Offset from EEPROM + // + if(!AutoloadFail ){ + Adapter->eeprompriv.EEPROMRFGainOffset =PROMContent[EEPROM_RF_GAIN_OFFSET]; + DBG_871X("AutoloadFail =%x,\n", AutoloadFail); + Adapter->eeprompriv.EEPROMRFGainVal=EFUSE_Read1Byte(Adapter, EEPROM_RF_GAIN_VAL); + DBG_871X("Adapter->eeprompriv.EEPROMRFGainVal=%x\n", Adapter->eeprompriv.EEPROMRFGainVal); + } + else{ + Adapter->eeprompriv.EEPROMRFGainOffset = 0; + Adapter->eeprompriv.EEPROMRFGainVal=0xFF; + DBG_871X("else AutoloadFail =%x,\n", AutoloadFail); + } + DBG_871X("EEPRORFGainOffset = 0x%02x\n", Adapter->eeprompriv.EEPROMRFGainOffset); +} +#endif //CONFIG_RF_GAIN_OFFSET + + + + void rtl8723a_cal_txdesc_chksum(struct tx_desc *ptxdesc) { u16 *usPtr = (u16*)ptxdesc; @@ -4351,6 +4400,11 @@ static void hw_var_set_opmode(PADAPTER padapter, u8 variable, u8 *val) } // disable atim wnd +#ifdef CONFIG_CONCURRENT_MODE + if (padapter->iface_type == IFACE_PORT1) + val8 = DIS_TSF_UDT|DIS_ATIM; + else +#endif val8 = DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_ATIM; SetBcnCtrlReg(padapter, val8, ~val8); } @@ -4608,8 +4662,8 @@ static void hw_var_set_mlme_disconnect(PADAPTER padapter, u8 variable, u8 *val) // reset TSF1 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(1)); - // disable update TSF1 - SetBcnCtrlReg(padapter, DIS_TSF_UDT, 0); + // disable update TSF1, disble BCN function + SetBcnCtrlReg(padapter, DIS_TSF_UDT, EN_BCN_FUNCTION); } else #endif @@ -5315,7 +5369,7 @@ _func_enter_; #define RW_RELEASE_EN BIT(18) #define RXDMA_IDLE BIT(17) - struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; + struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); u8 trycnt = 100; // pause tx @@ -5353,12 +5407,13 @@ _func_enter_; { u16 v16; u32 i; + #if 0 u8 RetryLimit = 0x01; //rtw_write16(padapter, REG_RL,0x0101); v16 = RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT; rtw_write16(padapter, REG_RL, v16); - + #endif for (i=0; i<1000; i++) { if (rtw_read32(padapter, 0x200) != rtw_read32(padapter, 0x204)) @@ -5372,10 +5427,11 @@ _func_enter_; break; } } - + #if 0 RetryLimit = 0x30; v16 = RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT; rtw_write16(padapter, REG_RL, v16); + #endif } #endif break; @@ -5403,7 +5459,11 @@ _func_enter_; rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper); } break; - + case HW_VAR_H2C_MEDIA_STATUS_RPT: + { + rtl8723a_set_FwMediaStatus_cmd(padapter , (*(u16 *)val)); + } + break; case HW_VAR_BCN_VALID: //BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw rtw_write8(padapter, REG_TDECTRL+2, rtw_read8(padapter, REG_TDECTRL+2) | BIT0); @@ -5447,13 +5507,25 @@ void GetHwReg8723A(PADAPTER padapter, u8 variable, u8 *val) } break; + case HW_VAR_CAM_READ: + { + u32 cmd; + u32 *cam_val = (u32*)val; + + cmd = CAM_POLLINIG | CAM_READ | cam_val[1]; + rtw_write32(padapter, RWCAM, cmd); + + cam_val[0]=rtw_read32(padapter, RCAMO); + } + break; + case HW_VAR_FWLPS_RF_ON: { // When we halt NIC, we should check if FW LPS is leave. u32 valRCR; if ((padapter->bSurpriseRemoved == _TRUE) || - (padapter->pwrctrlpriv.rf_pwrstate == rf_off)) + (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off)) { // If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, // because Fw is unload. @@ -5504,7 +5576,13 @@ void GetHwReg8723A(PADAPTER padapter, u8 variable, u8 *val) break; case HW_VAR_CHK_HI_QUEUE_EMPTY: *val = ((rtw_read32(padapter, REG_HGQ_INFORMATION)&0x0000ff00)==0) ? _TRUE:_FALSE; + break; + case HW_VAR_C2HEVT_CLEAR: + *val = rtw_read8(padapter, REG_C2HEVT_CLEAR); break; + case HW_VAR_C2HEVT_MSG_NORMAL: + *val = rtw_read8(padapter, REG_C2HEVT_MSG_NORMAL); + break; } } @@ -5557,40 +5635,14 @@ void rtl8723a_SingleDualAntennaDetection(PADAPTER padapter) } #endif // CONFIG_BT_COEXIST -void rtl8723a_clone_haldata(_adapter* dst_adapter, _adapter* src_adapter) -{ -#ifdef CONFIG_SDIO_HCI - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(dst_adapter); - //_thread_hdl_ SdioXmitThread; - _sema temp_SdioXmitSema; - _sema temp_SdioXmitTerminateSema; - //u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; - _lock temp_SdioTxFIFOFreePageLock; - - _rtw_memcpy(&temp_SdioXmitSema, &(pHalData->SdioXmitSema), sizeof(_sema)); - _rtw_memcpy(&temp_SdioXmitTerminateSema, &(pHalData->SdioXmitTerminateSema), sizeof(_sema)); - _rtw_memcpy(&temp_SdioTxFIFOFreePageLock, &(pHalData->SdioTxFIFOFreePageLock), sizeof(_lock)); - - _rtw_memcpy(dst_adapter->HalData, src_adapter->HalData, dst_adapter->hal_data_sz); - - _rtw_memcpy(&(pHalData->SdioXmitSema), &temp_SdioXmitSema, sizeof(_sema)); - _rtw_memcpy(&(pHalData->SdioXmitTerminateSema), &temp_SdioXmitTerminateSema, sizeof(_sema)); - _rtw_memcpy(&(pHalData->SdioTxFIFOFreePageLock), &temp_SdioTxFIFOFreePageLock, sizeof(_lock)); - -#else - _rtw_memcpy(dst_adapter->HalData, src_adapter->HalData, dst_adapter->hal_data_sz); -#endif - -} - void rtl8723a_start_thread(_adapter *padapter) { #if (defined CONFIG_SDIO_HCI) || (defined CONFIG_GSPI_HCI) #ifndef CONFIG_SDIO_TX_TASKLET - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct xmit_priv *xmitpriv = &padapter->xmitpriv; - pHalData->SdioXmitThread = kthread_run(rtl8723as_xmit_thread, padapter, "RTWHALXT"); - if (IS_ERR(pHalData->SdioXmitThread)) + xmitpriv->SdioXmitThread = kthread_run(rtl8723as_xmit_thread, padapter, "RTWHALXT"); + if (IS_ERR(xmitpriv->SdioXmitThread)) { RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: start rtl8723as_xmit_thread FAIL!!\n", __FUNCTION__)); } @@ -5602,15 +5654,49 @@ void rtl8723a_stop_thread(_adapter *padapter) { #if (defined CONFIG_SDIO_HCI) || (defined CONFIG_GSPI_HCI) #ifndef CONFIG_SDIO_TX_TASKLET - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); + struct xmit_priv *xmitpriv = &padapter->xmitpriv; // stop xmit_buf_thread - if (pHalData->SdioXmitThread ) { - _rtw_up_sema(&pHalData->SdioXmitSema); - _rtw_down_sema(&pHalData->SdioXmitTerminateSema); - pHalData->SdioXmitThread = 0; + if (xmitpriv->SdioXmitThread ) { + _rtw_up_sema(&xmitpriv->SdioXmitSema); + _rtw_down_sema(&xmitpriv->SdioXmitTerminateSema); + xmitpriv->SdioXmitThread = 0; } #endif #endif } +#if defined(CONFIG_CHECK_BT_HANG) && defined(CONFIG_BT_COEXIST) +extern void check_bt_status_work(void *data); +void rtl8723a_init_checkbthang_workqueue(_adapter * adapter) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) + adapter->priv_checkbt_wq = alloc_workqueue("sdio_wq", 0, 0); +#else + adapter->priv_checkbt_wq = create_workqueue("sdio_wq"); +#endif + INIT_DELAYED_WORK(&adapter->checkbt_work, (void*)check_bt_status_work); +} + +void rtl8723a_free_checkbthang_workqueue(_adapter * adapter) +{ + if (adapter->priv_checkbt_wq) { + cancel_delayed_work_sync(&adapter->checkbt_work); + flush_workqueue(adapter->priv_checkbt_wq); + destroy_workqueue(adapter->priv_checkbt_wq); + adapter->priv_checkbt_wq = NULL; + } +} +void rtl8723a_cancel_checkbthang_workqueue(_adapter * adapter) +{ + if (adapter->priv_checkbt_wq) { + cancel_delayed_work_sync(&adapter->checkbt_work); + } +} + +void rtl8723a_hal_check_bt_hang(_adapter * adapter) +{ + if (adapter->priv_checkbt_wq) + queue_delayed_work(adapter->priv_checkbt_wq, &(adapter->checkbt_work), 0); +} +#endif diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_mp.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_mp.c index 9ee3996aaad1..c05a0cb39103 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_mp.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_mp.c @@ -1,1179 +1,1214 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#define _RTL8723A_MP_C_ -#ifdef CONFIG_MP_INCLUDED - -#include <drv_types.h> -#include <rtw_mp.h> -#include <rtl8723a_hal.h> - - -/*----------------------------------------------------------------------------- - * Function: mpt_SwitchRfSetting - * - * Overview: Change RF Setting when we siwthc channel/rate/BW for MP. - * - * Input: IN PADAPTER pAdapter - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series. - * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3. - * - *---------------------------------------------------------------------------*/ - static void phy_SwitchRfSetting8723A(PADAPTER pAdapter,u8 channel ) -{ - - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u32 u4RF_IPA[3], u4RF_TXBIAS, u4RF_SYN_G2; - - //default value - { - u4RF_IPA[0] = 0x4F424; //CCK - u4RF_IPA[1] = 0xCF424; //OFDM - u4RF_IPA[2] = 0x8F424; //MCS - u4RF_TXBIAS = 0xC0356; - u4RF_SYN_G2 = 0x4F200; - } - - switch(channel) - { - case 1: - u4RF_IPA[0] = 0x4F40C; - u4RF_IPA[1] = 0xCF466; - u4RF_TXBIAS = 0xC0350; - break; - - case 2: - u4RF_IPA[0] = 0x4F407; - u4RF_TXBIAS = 0xC0350; - break; - - case 3: - u4RF_IPA[0] = 0x4F407; - u4RF_IPA[2] = 0x8F466; - u4RF_TXBIAS = 0xC0350; - break; - - case 5: - case 8: - u4RF_SYN_G2 = 0x0F400; - break; - - case 6: - case 13: - u4RF_IPA[0] = 0x4F40C; - break; - - case 7: - u4RF_IPA[0] = 0x4F40C; - u4RF_SYN_G2 = 0x0F400; - break; - - case 9: - u4RF_IPA[2] = 0x8F454; - u4RF_SYN_G2 = 0x0F400; - break; - - case 11: - u4RF_IPA[0] = 0x4F40C; - u4RF_IPA[1] = 0xCF454; - u4RF_SYN_G2 = 0x0F400; - break; - - default: - u4RF_IPA[0] = 0x4F424; - u4RF_IPA[1] = 0x8F424; - u4RF_IPA[2] = 0xCF424; - u4RF_TXBIAS = 0xC0356; - u4RF_SYN_G2 = 0x4F200; - break; - } - - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[0]); - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[1]); - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[2]); - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_TXBIAS, bRFRegOffsetMask, u4RF_TXBIAS); - PHY_SetRFReg(pAdapter, RF_PATH_A, RF_SYN_G2, bRFRegOffsetMask, u4RF_SYN_G2); - -} - - - - -void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); - u8 ChannelToSw = pMptCtx->MptChannelToSw; - - phy_SwitchRfSetting8723A(pAdapter, ChannelToSw); -} - - - - -s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - - - if (!netif_running(padapter->pnetdev)) { - RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n")); - return _FAIL; - } - - if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { - RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n")); - return _FAIL; - } - - if (enable) - pdmpriv->TxPowerTrackControl = _TRUE; - else - pdmpriv->TxPowerTrackControl = _FALSE; - - return _SUCCESS; -} - -void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - - - *enable = pdmpriv->TxPowerTrackControl; -} - -static void Hal_disable_dm(PADAPTER padapter) -{ - u8 v8; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - - - //3 1. disable firmware dynamic mechanism - // disable Power Training, Rate Adaptive - v8 = rtw_read8(padapter, REG_BCN_CTRL); - v8 &= ~EN_BCN_FUNCTION; - rtw_write8(padapter, REG_BCN_CTRL, v8); - - //3 2. disable driver dynamic mechanism - // disable Dynamic Initial Gain - // disable High Power - // disable Power Tracking - Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); - - // enable APK, LCK and IQK but disable power tracking - pdmpriv->TxPowerTrackControl = _FALSE; - Switch_DM_Func(padapter, DYNAMIC_RF_TX_PWR_TRACK , _TRUE); -} - -void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) -{ - u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0; - u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12; - u8 i; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - - // get current cck swing value and check 0xa22 & 0xa23 later to match the table. - CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord); - - if (!bInCH14) - { - // Readback the current bb cck swing value and compare with the table to - // get the current swing index - for (i = 0; i < CCK_TABLE_SIZE; i++) - { - if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) && - (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) - { - CCKSwingIndex = i; -// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n", -// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex)); - break; - } - } - - //Write 0xa22 0xa23 - TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] + - (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ; - - - //Write 0xa24 ~ 0xa27 - TempVal2 = 0; - TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] + - (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) + - (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+ - (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24); - - //Write 0xa28 0xa29 - TempVal3 = 0; - TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] + - (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ; - } - else - { - for (i = 0; i < CCK_TABLE_SIZE; i++) - { - if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) && - (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) - { - CCKSwingIndex = i; -// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n", -// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex)); - break; - } - } - - //Write 0xa22 0xa23 - TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] + - (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ; - - //Write 0xa24 ~ 0xa27 - TempVal2 = 0; - TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] + - (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) + - (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+ - (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24); - - //Write 0xa28 0xa29 - TempVal3 = 0; - TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] + - (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ; - } - - write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal); - write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2); - write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3); -} - -void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven) -{ - s32 TempCCk; - u8 CCK_index, CCK_index_old; - u8 Action = 0; //0: no action, 1: even->odd, 2:odd->even - u8 TimeOut = 100; - s32 i = 0; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; - - - if (!IS_92C_SERIAL(pHalData->VersionID)) - return; -#if 0 - while(PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE) - { - PlatformSleepUs(100); - TimeOut--; - if(TimeOut <= 0) - { - RTPRINT(FINIT, INIT_TxPower, - ("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" )); - break; - } - } -#endif - if (beven && !pMptCtx->bMptIndexEven) //odd->even - { - Action = 2; - pMptCtx->bMptIndexEven = _TRUE; - } - else if (!beven && pMptCtx->bMptIndexEven) //even->odd - { - Action = 1; - pMptCtx->bMptIndexEven = _FALSE; - } - - if (Action != 0) - { - //Query CCK default setting From 0xa24 - TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK; - for (i = 0; i < CCK_TABLE_SIZE; i++) - { - if (pHalData->dmpriv.bCCKinCH14) - { - if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == _TRUE) - { - CCK_index_old = (u8) i; -// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n", -// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14)); - break; - } - } - else - { - if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == _TRUE) - { - CCK_index_old = (u8) i; -// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n", -// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14)); - break; - } - } - } - - if (Action == 1) - CCK_index = CCK_index_old - 1; - else - CCK_index = CCK_index_old + 1; - -// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n", -// CCK_index)); - - //Adjust CCK according to gain index - if (!pHalData->dmpriv.bCCKinCH14) { - rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]); - rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]); - rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]); - rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]); - rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]); - rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]); - rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]); - rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]); - } else { - rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]); - rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]); - rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]); - rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]); - rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]); - rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]); - rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]); - rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]); - } - } -#if 0 - RTPRINT(FINIT, INIT_TxPower, - ("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20))); - - PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE); -#endif -} -/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ - -/* - * SetChannel - * Description - * Use H2C command to change channel, - * not only modify rf register, but also other setting need to be done. - */ -void Hal_SetChannel(PADAPTER pAdapter) -{ -#if 0 - struct mp_priv *pmp = &pAdapter->mppriv; - -// SelectChannel(pAdapter, pmp->channel); - set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth); -#else - u8 eRFPath; - - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - struct mp_priv *pmp = &pAdapter->mppriv; - u8 channel = pmp->channel; - u8 bandwidth = pmp->bandwidth; - u8 rate = pmp->rateidx; - - - // set RF channel register - for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) - { - if(IS_HARDWARE_TYPE_8192D(pAdapter)) - _write_rfreg(pAdapter, (RF_RADIO_PATH_E)eRFPath, rRfChannel, 0xFF, channel); - else - _write_rfreg(pAdapter, eRFPath, rRfChannel, 0x3FF, channel); - } - Hal_mpt_SwitchRfSetting(pAdapter); - - SelectChannel(pAdapter, channel); - - if (pHalData->CurrentChannel == 14 && !pHalData->dmpriv.bCCKinCH14) { - pHalData->dmpriv.bCCKinCH14 = _TRUE; - Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14); - } - else if (pHalData->CurrentChannel != 14 && pHalData->dmpriv.bCCKinCH14) { - pHalData->dmpriv.bCCKinCH14 = _FALSE; - Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14); - } - -#endif -} - -/* - * Notice - * Switch bandwitdth may change center frequency(channel) - */ -void Hal_SetBandwidth(PADAPTER pAdapter) -{ - struct mp_priv *pmp = &pAdapter->mppriv; - - - SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset); - Hal_mpt_SwitchRfSetting(pAdapter); -} - -void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower) -{ - u32 tmpval = 0; - - - // rf-A cck tx power - write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]); - tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A]; - write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); - - // rf-B cck tx power - write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]); - tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B]; - write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); - - RT_TRACE(_module_mp_, _drv_notice_, - ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n", - TxPower[RF_PATH_A], TxPower[RF_PATH_B])); -} - -void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower) -{ - u32 TxAGC = 0; - u8 tmpval = 0; - PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - - // HT Tx-rf(A) - tmpval = TxPower[RF_PATH_A]; - TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval; - - write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); - write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); - write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); - write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); - write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); - write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); - - if (pHalData->dmpriv.bAPKdone && !IS_NORMAL_CHIP(pHalData->VersionID)) - { - if (tmpval > pMptCtx->APK_bound[RF_PATH_A]) - write_rfreg(pAdapter, RF_PATH_A, 0xe, pHalData->dmpriv.APKoutput[0][0]); - else - write_rfreg(pAdapter, RF_PATH_A, 0xe, pHalData->dmpriv.APKoutput[0][1]); - } - - // HT Tx-rf(B) - tmpval = TxPower[RF_PATH_B]; - TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval; - - write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); - write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); - write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); - write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); - write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); - write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); - - if (pHalData->dmpriv.bAPKdone && !IS_NORMAL_CHIP(pHalData->VersionID)) - { - if (tmpval > pMptCtx->APK_bound[RF_PATH_B]) - write_rfreg(pAdapter, RF_PATH_B, 0xe, pHalData->dmpriv.APKoutput[1][0]); - else - write_rfreg(pAdapter, RF_PATH_B, 0xe, pHalData->dmpriv.APKoutput[1][1]); - } - - RT_TRACE(_module_mp_, _drv_notice_, - ("-SetOFDMTxPower: A[0x%02x] B[0x%02x]\n", - TxPower[RF_PATH_A], TxPower[RF_PATH_B])); -} - -void Hal_SetAntennaPathPower(PADAPTER pAdapter) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u8 TxPowerLevel[MAX_RF_PATH_NUMS]; - u8 rfPath; - - TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx; - TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b; - - switch (pAdapter->mppriv.antenna_tx) - { - case ANTENNA_A: - default: - rfPath = RF_PATH_A; - break; - case ANTENNA_B: - rfPath = RF_PATH_B; - break; - case ANTENNA_C: - rfPath = RF_PATH_C; - break; - } - - switch (pHalData->rf_chip) - { - case RF_8225: - case RF_8256: - case RF_6052: - Hal_SetCCKTxPower(pAdapter, TxPowerLevel); - if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate - Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0); - Hal_SetOFDMTxPower(pAdapter, TxPowerLevel); - break; - - default: - break; - } -} - -void Hal_SetTxPower(PADAPTER pAdapter) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - u8 TxPower = pAdapter->mppriv.txpoweridx; - u8 TxPowerLevel[MAX_RF_PATH_NUMS]; - u8 rf, rfPath; - - for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++) { - TxPowerLevel[rf] = TxPower; - } - - switch (pAdapter->mppriv.antenna_tx) - { - case ANTENNA_A: - default: - rfPath = RF_PATH_A; - break; - case ANTENNA_B: - rfPath = RF_PATH_B; - break; - case ANTENNA_C: - rfPath = RF_PATH_C; - break; - } - - switch (pHalData->rf_chip) - { - // 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!! - // We should call normal driver API later!! - case RF_8225: - case RF_8256: - case RF_6052: - Hal_SetCCKTxPower(pAdapter, TxPowerLevel); - if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate - Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0); - Hal_SetOFDMTxPower(pAdapter, TxPowerLevel); - break; - - default: - break; - } - -// SetCCKTxPower(pAdapter, TxPower); -// SetOFDMTxPower(pAdapter, TxPower); -} - -void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset) -{ - u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC; - - return ; - - TxAGCOffset_B = (ulTxAGCOffset&0x000000ff); - TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8); - TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16); - - tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B); - write_bbreg(pAdapter, rFPGA0_TxGainStage, - (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC); -} - -void Hal_SetDataRate(PADAPTER pAdapter) -{ - if(!IS_HARDWARE_TYPE_8723A(pAdapter)) - Hal_mpt_SwitchRfSetting(pAdapter); -} - - -void Hal_SetAntenna(PADAPTER pAdapter) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */ - R_ANTENNA_SELECT_CCK *p_cck_txrx; - - u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0; - u8 chgTx = 0, chgRx = 0; - u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0; - - - p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val; - p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val; - - p_ofdm_tx->r_ant_ht1 = 0x1; - p_ofdm_tx->r_ant_ht2 = 0x2; // Second TX RF path is A - p_ofdm_tx->r_ant_non_ht = 0x3; // 0x1+0x2=0x3 - - switch (pAdapter->mppriv.antenna_tx) - { - case ANTENNA_A: - p_ofdm_tx->r_tx_antenna = 0x1; - r_ofdm_tx_en_val = 0x1; - p_ofdm_tx->r_ant_l = 0x1; - p_ofdm_tx->r_ant_ht_s1 = 0x1; - p_ofdm_tx->r_ant_non_ht_s1 = 0x1; - p_cck_txrx->r_ccktx_enable = 0x8; - chgTx = 1; - - // From SD3 Willis suggestion !!! Set RF A=TX and B as standby -// if (IS_HARDWARE_TYPE_8192S(pAdapter)) - { - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1); - r_ofdm_tx_en_val = 0x3; - - // Power save - //cosa r_ant_select_ofdm_val = 0x11111111; - - // We need to close RFB by SW control - if (pHalData->rf_type == RF_2T2R) - { - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1); - PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0); - } - } - break; - - case ANTENNA_B: - p_ofdm_tx->r_tx_antenna = 0x2; - r_ofdm_tx_en_val = 0x2; - p_ofdm_tx->r_ant_l = 0x2; - p_ofdm_tx->r_ant_ht_s1 = 0x2; - p_ofdm_tx->r_ant_non_ht_s1 = 0x2; - p_cck_txrx->r_ccktx_enable = 0x4; - chgTx = 1; - - // From SD3 Willis suggestion !!! Set RF A as standby - //if (IS_HARDWARE_TYPE_8192S(pAdapter)) - { - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); - PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); -// r_ofdm_tx_en_val = 0x3; - - // Power save - //cosa r_ant_select_ofdm_val = 0x22222222; - - // 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table. - // 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control - if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) - { - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1); - PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); -// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); - } - } - break; - - case ANTENNA_AB: // For 8192S - p_ofdm_tx->r_tx_antenna = 0x3; - r_ofdm_tx_en_val = 0x3; - p_ofdm_tx->r_ant_l = 0x3; - p_ofdm_tx->r_ant_ht_s1 = 0x3; - p_ofdm_tx->r_ant_non_ht_s1 = 0x3; - p_cck_txrx->r_ccktx_enable = 0xC; - chgTx = 1; - - // From SD3 Willis suggestion !!! Set RF B as standby - //if (IS_HARDWARE_TYPE_8192S(pAdapter)) - { - PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); - PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); - - // Disable Power save - //cosa r_ant_select_ofdm_val = 0x3321333; -#if 0 - // 2008/10/31 MH From SD3 Willi's suggestion. We must read RFA 2T table. - if ((pHalData->VersionID == VERSION_8192S_ACUT)) // For RTL8192SU A-Cut only, by Roger, 2008.11.07. - { - mpt_RFConfigFromPreParaArrary(pAdapter, 1, RF_PATH_A); - } -#endif - // 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control - if (pHalData->rf_type == RF_2T2R) - { - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); -// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); - } - } - break; - - default: - break; - } - - // - // r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D - // r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D - // r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D - // - switch (pAdapter->mppriv.antenna_rx) - { - case ANTENNA_A: - r_rx_antenna_ofdm = 0x1; // A - p_cck_txrx->r_cckrx_enable = 0x0; // default: A - p_cck_txrx->r_cckrx_enable_2 = 0x0; // option: A - chgRx = 1; - break; - - case ANTENNA_B: - r_rx_antenna_ofdm = 0x2; // B - p_cck_txrx->r_cckrx_enable = 0x1; // default: B - p_cck_txrx->r_cckrx_enable_2 = 0x1; // option: B - chgRx = 1; - break; - - case ANTENNA_AB: - r_rx_antenna_ofdm = 0x3; // AB - p_cck_txrx->r_cckrx_enable = 0x0; // default:A - p_cck_txrx->r_cckrx_enable_2 = 0x1; // option:B - chgRx = 1; - break; - - default: - break; - } - - if (chgTx && chgRx) - { - switch(pHalData->rf_chip) - { - case RF_8225: - case RF_8256: - case RF_6052: - //r_ant_sel_cck_val = r_ant_select_cck_val; - PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); //OFDM Tx - PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); //OFDM Tx - PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx - PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx - PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);//r_ant_sel_cck_val); //CCK TxRx - - break; - - default: - break; - } - } - - RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n")); -} - -s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - - if (!netif_running(pAdapter->pnetdev)) { - RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n")); - return _FAIL; - } - - if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { - RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n")); - return _FAIL; - } - - target_ther &= 0xff; - if (target_ther < 0x07) - target_ther = 0x07; - else if (target_ther > 0x1d) - target_ther = 0x1d; - - pHalData->EEPROMThermalMeter = target_ther; - - return _SUCCESS; -} - -void Hal_TriggerRFThermalMeter(PADAPTER pAdapter) -{ - - write_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x60); // 0x24: RF Reg[6:5] - -// RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" )); -} - -u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter) -{ - u32 ThermalValue = 0; - - ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F); // 0x24: RF Reg[4:0] -// RT_TRACE(_module_mp_, _drv_alert_, ("ThermalValue = 0x%x\n", ThermalValue)); - return (u8)ThermalValue; -} - -void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value) -{ -#if 0 - fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER); - rtw_msleep_os(1000); - fw_cmd_data(pAdapter, value, 1); - *value &= 0xFF; -#else - - Hal_TriggerRFThermalMeter(pAdapter); - rtw_msleep_os(1000); - *value = Hal_ReadRFThermalMeter(pAdapter); -#endif -} - -void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - pAdapter->mppriv.MptCtx.bSingleCarrier = bStart; - if (bStart)// Start Single Carrier. - { - RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n")); - // 1. if OFDM block on? - if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) - write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on - - { - // 2. set CCK test mode off, set to CCK normal mode - write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); - // 3. turn on scramble setting - write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); - } - // 4. Turn On Single Carrier Tx and turn off the other test modes. - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); -#ifdef CONFIG_RTL8192C - // 5. Disable TX power saving at STF & LLTF - write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 1); -#endif - } - else// Stop Single Carrier. - { - RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test stop\n")); - - // Turn off all test modes. - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); -#ifdef CONFIG_RTL8192C - // Cancel disable TX power saving at STF&LLTF - write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 0); -#endif - //Delay 10 ms //delay_ms(10); - rtw_msleep_os(10); - - //BB Reset - write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); - write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); - } -} - - -void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID); - - u8 rfPath; - - switch (pAdapter->mppriv.antenna_tx) - { - case ANTENNA_A: - default: - rfPath = RF_PATH_A; - break; - case ANTENNA_B: - rfPath = RF_PATH_B; - break; - case ANTENNA_C: - rfPath = RF_PATH_C; - break; - } - - pAdapter->mppriv.MptCtx.bSingleTone = bStart; - if (bStart)// Start Single Tone. - { - RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test start\n")); - write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0); - write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0); - - if (is92C) - { - _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01); - rtw_usleep_os(100); - if (rfPath == RF_PATH_A) - write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); // PAD all on. - else if (rfPath == RF_PATH_B) - write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); // PAD all on. - write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on. - rtw_usleep_os(100); - } - else - { - write_rfreg(pAdapter, rfPath, 0x21, 0xd4000); - rtw_usleep_os(100); - write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on. - rtw_usleep_os(100); - } - - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); - - } - else// Stop Single Tone. - { - RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n")); - write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1); - write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1); - - if (is92C) { - _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00); - rtw_usleep_os(100); - write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); // PAD all on. - write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); // PAD all on. - rtw_usleep_os(100); - } else { - write_rfreg(pAdapter, rfPath, 0x21, 0x54000); - rtw_usleep_os(100); - write_rfreg(pAdapter, rfPath, 0x00, 0x30000); // PAD all on. - rtw_usleep_os(100); - } - - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); - - } - -} - - -void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) -{ - pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart; - if (bStart) // Start Carrier Suppression. - { - RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n")); - //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B) - if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) - { - // 1. if CCK block on? - if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn)) - write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on - - //Turn Off All Test Mode - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); - - write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode - write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); //turn off scramble setting - - //Set CCK Tx Test Rate - //PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate); - write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); //Set FTxRate to 1Mbps - } - - //Set for dynamic set Power index - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); - - } - else// Stop Carrier Suppression. - { - RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n")); - //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B) - if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) { - write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode - write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); //turn on scramble setting - - //BB Reset - write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); - write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); - } - //Stop for dynamic set Power index - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); - } - //DbgPrint("\n MPT_ProSetCarrierSupp() is finished. \n"); -} - -void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart) -{ - u32 cckrate; - - if (bStart) - { - RT_TRACE(_module_mp_, _drv_alert_, - ("SetCCKContinuousTx: test start\n")); - - // 1. if CCK block on? - if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn)) - write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on - - //Turn Off All Test Mode - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); - //Set CCK Tx Test Rate - #if 0 - switch(pAdapter->mppriv.rateidx) - { - case 2: - cckrate = 0; - break; - case 4: - cckrate = 1; - break; - case 11: - cckrate = 2; - break; - case 22: - cckrate = 3; - break; - default: - cckrate = 0; - break; - } - #else - cckrate = pAdapter->mppriv.rateidx; - #endif - write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate); - write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode - write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting - - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); - - // Patch for CCK 11M waveform - if (cckrate == MPT_RATE_1M) - write_bbreg(pAdapter, 0xA71, BIT(6), bDisable); - else - write_bbreg(pAdapter, 0xA71, BIT(6), bEnable); - - - } - else { - RT_TRACE(_module_mp_, _drv_info_, - ("SetCCKContinuousTx: test stop\n")); - - write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode - write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting - - //BB Reset - write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); - write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); - - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); - } - - pAdapter->mppriv.MptCtx.bCckContTx = bStart; - pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE; -}/* mpt_StartCckContTx */ - -void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - - if (bStart) { - RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n")); - // 1. if OFDM block on? - if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) - write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on - { - - // 2. set CCK test mode off, set to CCK normal mode - write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); - - // 3. turn on scramble setting - write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); - } - // 4. Turn On Continue Tx and turn off the other test modes. - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); - - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500); - - } else { - RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n")); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); - write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); - //Delay 10 ms - rtw_msleep_os(10); - //BB Reset - write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); - write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); - - write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100); - write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100); - } - - pAdapter->mppriv.MptCtx.bCckContTx = _FALSE; - pAdapter->mppriv.MptCtx.bOfdmContTx = bStart; -}/* mpt_StartOfdmContTx */ - -void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart) -{ -#if 0 - // ADC turn off [bit24-21] adc port0 ~ port1 - if (bStart) { - write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF); - rtw_usleep_os(100); - } -#endif - RT_TRACE(_module_mp_, _drv_info_, - ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx)); - - pAdapter->mppriv.MptCtx.bStartContTx = bStart; - if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) - { - Hal_SetCCKContinuousTx(pAdapter, bStart); - } - else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) && - (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15)) - { - Hal_SetOFDMContinuousTx(pAdapter, bStart); - } -#if 0 - // ADC turn on [bit24-21] adc port0 ~ port1 - if (!bStart) { - write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000); - } -#endif -} - -#endif // CONFIG_MP_INCLUDE - +/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8723A_MP_C_
+#ifdef CONFIG_MP_INCLUDED
+
+#include <drv_types.h>
+#include <rtw_mp.h>
+#include <rtl8723a_hal.h>
+
+
+/*-----------------------------------------------------------------------------
+ * Function: mpt_SwitchRfSetting
+ *
+ * Overview: Change RF Setting when we siwthc channel/rate/BW for MP.
+ *
+ * Input: IN PADAPTER pAdapter
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series.
+ * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3.
+ *
+ *---------------------------------------------------------------------------*/
+ static void phy_SwitchRfSetting8723A(PADAPTER pAdapter,u8 channel )
+{
+
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ u32 u4RF_IPA[3], u4RF_TXBIAS, u4RF_SYN_G2;
+
+ DBG_8192C("phy_SwitchRfSetting8723A channel=%d\n",channel);
+
+
+ if(channel >= 1 && channel <= 9)
+ {
+ DBG_8192C("phy_SwitchRfSetting8723A REG_AFE_PLL_CTRL 0xF0FFFF83\n");
+ PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF0FFFF83);
+ }
+ else if (channel >= 10 && channel <= 14)
+ {
+ DBG_8192C("phy_SwitchRfSetting8723A REG_AFE_PLL_CTRL 0xF2FFFF83\n");
+ PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF2FFFF83);
+ }
+
+
+#if DEV_BUS_TYPE==RT_PCI_INTERFACE
+ u4Byte u4RF_IPA[3], u4RF_TXBIAS, u4RF_SYN_G2;
+ //default value
+ {
+ u4RF_IPA[0] = 0x4F424; //CCK
+ u4RF_IPA[1] = 0xCF424; //OFDM
+ u4RF_IPA[2] = 0x8F424; //MCS
+ u4RF_TXBIAS = 0xC0356;
+ u4RF_SYN_G2 = 0x4F200;
+ }
+
+ switch(channel)
+ {
+ case 1:
+ u4RF_IPA[0] = 0x4F40C;
+ u4RF_IPA[1] = 0xCF466;
+ u4RF_TXBIAS = 0xC0350;
+ u4RF_SYN_G2 = 0x0F400;
+ break;
+
+ case 2:
+ u4RF_IPA[0] = 0x4F407;
+ u4RF_TXBIAS = 0xC0350;
+ u4RF_SYN_G2 = 0x0F400;
+ break;
+
+ case 3:
+ u4RF_IPA[0] = 0x4F407;
+ u4RF_IPA[2] = 0x8F466;
+ u4RF_TXBIAS = 0xC0350;
+ u4RF_SYN_G2 = 0x0F400;
+ break;
+
+ case 5:
+ case 8:
+ u4RF_SYN_G2 = 0x0F400;
+ break;
+
+ case 6:
+ case 13:
+ u4RF_IPA[0] = 0x4F40C;
+ break;
+
+ case 7:
+ u4RF_IPA[0] = 0x4F40C;
+ u4RF_SYN_G2 = 0x0F400;
+ break;
+
+ case 9:
+ u4RF_IPA[2] = 0x8F454;
+ u4RF_SYN_G2 = 0x0F400;
+ break;
+
+ case 11:
+ u4RF_IPA[0] = 0x4F40C;
+ u4RF_IPA[1] = 0xCF454;
+ u4RF_SYN_G2 = 0x0F400;
+ break;
+
+ default:
+ u4RF_IPA[0] = 0x4F424;
+ u4RF_IPA[1] = 0x8F424;
+ u4RF_IPA[2] = 0xCF424;
+ u4RF_TXBIAS = 0xC0356;
+ u4RF_SYN_G2 = 0x4F200;
+ break;
+ }
+
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[0]);
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[1]);
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_IPA, bRFRegOffsetMask, u4RF_IPA[2]);
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_TXBIAS, bRFRegOffsetMask, u4RF_TXBIAS);
+ PHY_SetRFReg(pAdapter, ODM_RF_PATH_A, RF_SYN_G2, bRFRegOffsetMask, u4RF_SYN_G2);
+
+ if((channel >= 1 && channel <= 5) || (channel >= 8 && channel <= 9))
+ {
+ PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF0FFFF83);
+ }
+ else
+ {
+ PHY_SetBBReg(pAdapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF2FFFF83);
+ }
+
+#endif
+
+
+}
+
+
+
+
+void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx);
+ u8 ChannelToSw ;
+
+ pMptCtx->MptChannelToSw=pAdapter->mppriv.channel;
+ ChannelToSw =pMptCtx->MptChannelToSw;
+
+ phy_SwitchRfSetting8723A(pAdapter, ChannelToSw);
+}
+
+
+
+
+s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ struct dm_priv *pdmpriv = &pHalData->dmpriv;
+
+
+ if (!netif_running(padapter->pnetdev)) {
+ RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n"));
+ return _FAIL;
+ }
+
+ if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
+ RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n"));
+ return _FAIL;
+ }
+
+ if (enable)
+ pdmpriv->TxPowerTrackControl = _TRUE;
+ else
+ pdmpriv->TxPowerTrackControl = _FALSE;
+
+ return _SUCCESS;
+}
+
+void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ struct dm_priv *pdmpriv = &pHalData->dmpriv;
+
+
+ *enable = pdmpriv->TxPowerTrackControl;
+}
+
+static void Hal_disable_dm(PADAPTER padapter)
+{
+ u8 v8;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ struct dm_priv *pdmpriv = &pHalData->dmpriv;
+
+
+ //3 1. disable firmware dynamic mechanism
+ // disable Power Training, Rate Adaptive
+ v8 = rtw_read8(padapter, REG_BCN_CTRL);
+ v8 &= ~EN_BCN_FUNCTION;
+ rtw_write8(padapter, REG_BCN_CTRL, v8);
+
+ //3 2. disable driver dynamic mechanism
+ // disable Dynamic Initial Gain
+ // disable High Power
+ // disable Power Tracking
+ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
+
+ // enable APK, LCK and IQK but disable power tracking
+ pdmpriv->TxPowerTrackControl = _FALSE;
+ Switch_DM_Func(padapter, DYNAMIC_RF_TX_PWR_TRACK , _TRUE);
+}
+
+void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
+{
+ u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0;
+ u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12;
+ u8 i;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+
+ // get current cck swing value and check 0xa22 & 0xa23 later to match the table.
+ CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord);
+
+ if (!bInCH14)
+ {
+ // Readback the current bb cck swing value and compare with the table to
+ // get the current swing index
+ for (i = 0; i < CCK_TABLE_SIZE; i++)
+ {
+ if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) &&
+ (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1]))
+ {
+ CCKSwingIndex = i;
+// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
+// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
+ break;
+ }
+ }
+
+ //Write 0xa22 0xa23
+ TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] +
+ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ;
+
+
+ //Write 0xa24 ~ 0xa27
+ TempVal2 = 0;
+ TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] +
+ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) +
+ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+
+ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24);
+
+ //Write 0xa28 0xa29
+ TempVal3 = 0;
+ TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] +
+ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ;
+ }
+ else
+ {
+ for (i = 0; i < CCK_TABLE_SIZE; i++)
+ {
+ if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) &&
+ (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1]))
+ {
+ CCKSwingIndex = i;
+// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n",
+// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex));
+ break;
+ }
+ }
+
+ //Write 0xa22 0xa23
+ TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] +
+ (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ;
+
+ //Write 0xa24 ~ 0xa27
+ TempVal2 = 0;
+ TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] +
+ (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) +
+ (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+
+ (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24);
+
+ //Write 0xa28 0xa29
+ TempVal3 = 0;
+ TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] +
+ (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ;
+ }
+
+ write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal);
+ write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2);
+ write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3);
+}
+
+void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven)
+{
+ s32 TempCCk;
+ u8 CCK_index, CCK_index_old;
+ u8 Action = 0; //0: no action, 1: even->odd, 2:odd->even
+ u8 TimeOut = 100;
+ s32 i = 0;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
+
+
+ if (!IS_92C_SERIAL(pHalData->VersionID))
+ return;
+#if 0
+ while(PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE)
+ {
+ PlatformSleepUs(100);
+ TimeOut--;
+ if(TimeOut <= 0)
+ {
+ RTPRINT(FINIT, INIT_TxPower,
+ ("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" ));
+ break;
+ }
+ }
+#endif
+ if (beven && !pMptCtx->bMptIndexEven) //odd->even
+ {
+ Action = 2;
+ pMptCtx->bMptIndexEven = _TRUE;
+ }
+ else if (!beven && pMptCtx->bMptIndexEven) //even->odd
+ {
+ Action = 1;
+ pMptCtx->bMptIndexEven = _FALSE;
+ }
+
+ if (Action != 0)
+ {
+ //Query CCK default setting From 0xa24
+ TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK;
+ for (i = 0; i < CCK_TABLE_SIZE; i++)
+ {
+ if (pHalData->dmpriv.bCCKinCH14)
+ {
+ if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == _TRUE)
+ {
+ CCK_index_old = (u8) i;
+// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n",
+// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));
+ break;
+ }
+ }
+ else
+ {
+ if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == _TRUE)
+ {
+ CCK_index_old = (u8) i;
+// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n",
+// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14));
+ break;
+ }
+ }
+ }
+
+ if (Action == 1)
+ CCK_index = CCK_index_old - 1;
+ else
+ CCK_index = CCK_index_old + 1;
+
+// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n",
+// CCK_index));
+
+ //Adjust CCK according to gain index
+ if (!pHalData->dmpriv.bCCKinCH14) {
+ rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]);
+ rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]);
+ rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]);
+ rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]);
+ rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]);
+ rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]);
+ rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]);
+ rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]);
+ } else {
+ rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]);
+ rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]);
+ rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]);
+ rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]);
+ rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]);
+ rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]);
+ rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]);
+ rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]);
+ }
+ }
+#if 0
+ RTPRINT(FINIT, INIT_TxPower,
+ ("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20)));
+
+ PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE);
+#endif
+}
+/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
+
+/*
+ * SetChannel
+ * Description
+ * Use H2C command to change channel,
+ * not only modify rf register, but also other setting need to be done.
+ */
+void Hal_SetChannel(PADAPTER pAdapter)
+{
+#if 0
+ struct mp_priv *pmp = &pAdapter->mppriv;
+
+// SelectChannel(pAdapter, pmp->channel);
+ set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth);
+#else
+ u8 eRFPath;
+
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ struct mp_priv *pmp = &pAdapter->mppriv;
+ u8 channel = pmp->channel;
+ u8 bandwidth = pmp->bandwidth;
+ u8 rate = pmp->rateidx;
+
+
+ // set RF channel register
+ for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
+ {
+ if(IS_HARDWARE_TYPE_8192D(pAdapter))
+ _write_rfreg(pAdapter, (RF_RADIO_PATH_E)eRFPath, rRfChannel, 0xFF, channel);
+ else
+ _write_rfreg(pAdapter, eRFPath, rRfChannel, 0x3FF, channel);
+ }
+ Hal_mpt_SwitchRfSetting(pAdapter);
+
+ SelectChannel(pAdapter, channel);
+
+ if (pHalData->CurrentChannel == 14 && !pHalData->dmpriv.bCCKinCH14) {
+ pHalData->dmpriv.bCCKinCH14 = _TRUE;
+ Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14);
+ }
+ else if (pHalData->CurrentChannel != 14 && pHalData->dmpriv.bCCKinCH14) {
+ pHalData->dmpriv.bCCKinCH14 = _FALSE;
+ Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14);
+ }
+
+#endif
+}
+
+/*
+ * Notice
+ * Switch bandwitdth may change center frequency(channel)
+ */
+void Hal_SetBandwidth(PADAPTER pAdapter)
+{
+ struct mp_priv *pmp = &pAdapter->mppriv;
+
+
+ SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset);
+ Hal_mpt_SwitchRfSetting(pAdapter);
+}
+
+void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower)
+{
+ u32 tmpval = 0;
+
+
+ // rf-A cck tx power
+ write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]);
+ tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A];
+ write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
+
+ // rf-B cck tx power
+ write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]);
+ tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B];
+ write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
+
+ RT_TRACE(_module_mp_, _drv_notice_,
+ ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n",
+ TxPower[RF_PATH_A], TxPower[RF_PATH_B]));
+}
+
+void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower)
+{
+ u32 TxAGC = 0;
+ u8 tmpval = 0;
+ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+
+
+ // HT Tx-rf(A)
+ tmpval = TxPower[RF_PATH_A];
+ TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
+
+ write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);
+ write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);
+ write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);
+ write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);
+ write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);
+ write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);
+
+ if (pHalData->dmpriv.bAPKdone && !IS_NORMAL_CHIP(pHalData->VersionID))
+ {
+ if (tmpval > pMptCtx->APK_bound[RF_PATH_A])
+ write_rfreg(pAdapter, RF_PATH_A, 0xe, pHalData->dmpriv.APKoutput[0][0]);
+ else
+ write_rfreg(pAdapter, RF_PATH_A, 0xe, pHalData->dmpriv.APKoutput[0][1]);
+ }
+
+ // HT Tx-rf(B)
+ tmpval = TxPower[RF_PATH_B];
+ TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval;
+
+ write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC);
+ write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC);
+ write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC);
+ write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC);
+ write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC);
+ write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC);
+
+ if (pHalData->dmpriv.bAPKdone && !IS_NORMAL_CHIP(pHalData->VersionID))
+ {
+ if (tmpval > pMptCtx->APK_bound[RF_PATH_B])
+ write_rfreg(pAdapter, RF_PATH_B, 0xe, pHalData->dmpriv.APKoutput[1][0]);
+ else
+ write_rfreg(pAdapter, RF_PATH_B, 0xe, pHalData->dmpriv.APKoutput[1][1]);
+ }
+
+ RT_TRACE(_module_mp_, _drv_notice_,
+ ("-SetOFDMTxPower: A[0x%02x] B[0x%02x]\n",
+ TxPower[RF_PATH_A], TxPower[RF_PATH_B]));
+}
+
+void Hal_SetAntennaPathPower(PADAPTER pAdapter)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ u8 TxPowerLevel[MAX_RF_PATH_NUMS];
+ u8 rfPath;
+
+ TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx;
+ TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b;
+
+ switch (pAdapter->mppriv.antenna_tx)
+ {
+ case ANTENNA_A:
+ default:
+ rfPath = RF_PATH_A;
+ break;
+ case ANTENNA_B:
+ rfPath = RF_PATH_B;
+ break;
+ case ANTENNA_C:
+ rfPath = RF_PATH_C;
+ break;
+ }
+
+ switch (pHalData->rf_chip)
+ {
+ case RF_8225:
+ case RF_8256:
+ case RF_6052:
+ Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
+ if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate
+ Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
+ Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
+ break;
+
+ default:
+ break;
+ }
+}
+
+void Hal_SetTxPower(PADAPTER pAdapter)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ u8 TxPower = pAdapter->mppriv.txpoweridx;
+ u8 TxPowerLevel[MAX_RF_PATH_NUMS];
+ u8 rf, rfPath;
+
+ for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++) {
+ TxPowerLevel[rf] = TxPower;
+ }
+
+ switch (pAdapter->mppriv.antenna_tx)
+ {
+ case ANTENNA_A:
+ default:
+ rfPath = RF_PATH_A;
+ break;
+ case ANTENNA_B:
+ rfPath = RF_PATH_B;
+ break;
+ case ANTENNA_C:
+ rfPath = RF_PATH_C;
+ break;
+ }
+
+ switch (pHalData->rf_chip)
+ {
+ // 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!!
+ // We should call normal driver API later!!
+ case RF_8225:
+ case RF_8256:
+ case RF_6052:
+ Hal_SetCCKTxPower(pAdapter, TxPowerLevel);
+ if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate
+ Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0);
+ Hal_SetOFDMTxPower(pAdapter, TxPowerLevel);
+ break;
+
+ default:
+ break;
+ }
+
+// SetCCKTxPower(pAdapter, TxPower);
+// SetOFDMTxPower(pAdapter, TxPower);
+}
+
+void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
+{
+ u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC;
+
+ return ;
+
+ TxAGCOffset_B = (ulTxAGCOffset&0x000000ff);
+ TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8);
+ TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16);
+
+ tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B);
+ write_bbreg(pAdapter, rFPGA0_TxGainStage,
+ (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC);
+}
+
+void Hal_SetDataRate(PADAPTER pAdapter)
+{
+ if(!IS_HARDWARE_TYPE_8723A(pAdapter))
+ Hal_mpt_SwitchRfSetting(pAdapter);
+}
+
+
+void Hal_SetAntenna(PADAPTER pAdapter)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+
+ R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */
+ R_ANTENNA_SELECT_CCK *p_cck_txrx;
+
+ u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0;
+ u8 chgTx = 0, chgRx = 0;
+ u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0;
+
+
+ p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val;
+ p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val;
+
+ p_ofdm_tx->r_ant_ht1 = 0x1;
+ p_ofdm_tx->r_ant_ht2 = 0x2; // Second TX RF path is A
+ p_ofdm_tx->r_ant_non_ht = 0x3; // 0x1+0x2=0x3
+
+ switch (pAdapter->mppriv.antenna_tx)
+ {
+ case ANTENNA_A:
+ p_ofdm_tx->r_tx_antenna = 0x1;
+ r_ofdm_tx_en_val = 0x1;
+ p_ofdm_tx->r_ant_l = 0x1;
+ p_ofdm_tx->r_ant_ht_s1 = 0x1;
+ p_ofdm_tx->r_ant_non_ht_s1 = 0x1;
+ p_cck_txrx->r_ccktx_enable = 0x8;
+ chgTx = 1;
+
+ // From SD3 Willis suggestion !!! Set RF A=TX and B as standby
+// if (IS_HARDWARE_TYPE_8192S(pAdapter))
+ {
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
+ r_ofdm_tx_en_val = 0x3;
+
+ // Power save
+ //cosa r_ant_select_ofdm_val = 0x11111111;
+
+ // We need to close RFB by SW control
+ if (pHalData->rf_type == RF_2T2R)
+ {
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1);
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0);
+ }
+ }
+ break;
+
+ case ANTENNA_B:
+ p_ofdm_tx->r_tx_antenna = 0x2;
+ r_ofdm_tx_en_val = 0x2;
+ p_ofdm_tx->r_ant_l = 0x2;
+ p_ofdm_tx->r_ant_ht_s1 = 0x2;
+ p_ofdm_tx->r_ant_non_ht_s1 = 0x2;
+ p_cck_txrx->r_ccktx_enable = 0x4;
+ chgTx = 1;
+
+ // From SD3 Willis suggestion !!! Set RF A as standby
+ //if (IS_HARDWARE_TYPE_8192S(pAdapter))
+ {
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
+// r_ofdm_tx_en_val = 0x3;
+
+ // Power save
+ //cosa r_ant_select_ofdm_val = 0x22222222;
+
+ // 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table.
+ // 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control
+ if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R)
+ {
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1);
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0);
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
+// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0);
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
+ }
+ }
+ break;
+
+ case ANTENNA_AB: // For 8192S
+ p_ofdm_tx->r_tx_antenna = 0x3;
+ r_ofdm_tx_en_val = 0x3;
+ p_ofdm_tx->r_ant_l = 0x3;
+ p_ofdm_tx->r_ant_ht_s1 = 0x3;
+ p_ofdm_tx->r_ant_non_ht_s1 = 0x3;
+ p_cck_txrx->r_ccktx_enable = 0xC;
+ chgTx = 1;
+
+ // From SD3 Willis suggestion !!! Set RF B as standby
+ //if (IS_HARDWARE_TYPE_8192S(pAdapter))
+ {
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
+
+ // Disable Power save
+ //cosa r_ant_select_ofdm_val = 0x3321333;
+#if 0
+ // 2008/10/31 MH From SD3 Willi's suggestion. We must read RFA 2T table.
+ if ((pHalData->VersionID == VERSION_8192S_ACUT)) // For RTL8192SU A-Cut only, by Roger, 2008.11.07.
+ {
+ mpt_RFConfigFromPreParaArrary(pAdapter, 1, RF_PATH_A);
+ }
+#endif
+ // 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control
+ if (pHalData->rf_type == RF_2T2R)
+ {
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0);
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0);
+// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0);
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1);
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1);
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ //
+ // r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D
+ // r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D
+ // r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D
+ //
+ switch (pAdapter->mppriv.antenna_rx)
+ {
+ case ANTENNA_A:
+ r_rx_antenna_ofdm = 0x1; // A
+ p_cck_txrx->r_cckrx_enable = 0x0; // default: A
+ p_cck_txrx->r_cckrx_enable_2 = 0x0; // option: A
+ chgRx = 1;
+ break;
+
+ case ANTENNA_B:
+ r_rx_antenna_ofdm = 0x2; // B
+ p_cck_txrx->r_cckrx_enable = 0x1; // default: B
+ p_cck_txrx->r_cckrx_enable_2 = 0x1; // option: B
+ chgRx = 1;
+ break;
+
+ case ANTENNA_AB:
+ r_rx_antenna_ofdm = 0x3; // AB
+ p_cck_txrx->r_cckrx_enable = 0x0; // default:A
+ p_cck_txrx->r_cckrx_enable_2 = 0x1; // option:B
+ chgRx = 1;
+ break;
+
+ default:
+ break;
+ }
+
+ if (chgTx && chgRx)
+ {
+ switch(pHalData->rf_chip)
+ {
+ case RF_8225:
+ case RF_8256:
+ case RF_6052:
+ //r_ant_sel_cck_val = r_ant_select_cck_val;
+ PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); //OFDM Tx
+ PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); //OFDM Tx
+ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx
+ PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx
+ PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);//r_ant_sel_cck_val); //CCK TxRx
+
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n"));
+}
+
+s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+
+
+ if (!netif_running(pAdapter->pnetdev)) {
+ RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n"));
+ return _FAIL;
+ }
+
+ if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
+ RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n"));
+ return _FAIL;
+ }
+
+ target_ther &= 0xff;
+ if (target_ther < 0x07)
+ target_ther = 0x07;
+ else if (target_ther > 0x1d)
+ target_ther = 0x1d;
+
+ pHalData->EEPROMThermalMeter = target_ther;
+
+ return _SUCCESS;
+}
+
+void Hal_TriggerRFThermalMeter(PADAPTER pAdapter)
+{
+
+ write_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x60); // 0x24: RF Reg[6:5]
+
+// RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" ));
+}
+
+u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter)
+{
+ u32 ThermalValue = 0;
+
+ ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F); // 0x24: RF Reg[4:0]
+// RT_TRACE(_module_mp_, _drv_alert_, ("ThermalValue = 0x%x\n", ThermalValue));
+ return (u8)ThermalValue;
+}
+
+void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value)
+{
+#if 0
+ fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER);
+ rtw_msleep_os(1000);
+ fw_cmd_data(pAdapter, value, 1);
+ *value &= 0xFF;
+#else
+
+ Hal_TriggerRFThermalMeter(pAdapter);
+ rtw_msleep_os(1000);
+ *value = Hal_ReadRFThermalMeter(pAdapter);
+#endif
+}
+
+void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ pAdapter->mppriv.MptCtx.bSingleCarrier = bStart;
+ if (bStart)// Start Single Carrier.
+ {
+ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n"));
+ // 1. if OFDM block on?
+ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
+ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on
+
+ {
+ // 2. set CCK test mode off, set to CCK normal mode
+ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
+ // 3. turn on scramble setting
+ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
+ }
+ // 4. Turn On Single Carrier Tx and turn off the other test modes.
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
+#ifdef CONFIG_RTL8192C
+ // 5. Disable TX power saving at STF & LLTF
+ write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 1);
+#endif
+ }
+ else// Stop Single Carrier.
+ {
+ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test stop\n"));
+
+ // Turn off all test modes.
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
+#ifdef CONFIG_RTL8192C
+ // Cancel disable TX power saving at STF&LLTF
+ write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 0);
+#endif
+ //Delay 10 ms //delay_ms(10);
+ rtw_msleep_os(10);
+
+ //BB Reset
+ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
+ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
+ }
+}
+
+
+void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID);
+
+ u8 rfPath;
+
+ switch (pAdapter->mppriv.antenna_tx)
+ {
+ case ANTENNA_A:
+ default:
+ rfPath = RF_PATH_A;
+ break;
+ case ANTENNA_B:
+ rfPath = RF_PATH_B;
+ break;
+ case ANTENNA_C:
+ rfPath = RF_PATH_C;
+ break;
+ }
+
+ pAdapter->mppriv.MptCtx.bSingleTone = bStart;
+ if (bStart)// Start Single Tone.
+ {
+ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test start\n"));
+ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0);
+ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0);
+
+ if (is92C)
+ {
+ _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01);
+ rtw_usleep_os(100);
+ if (rfPath == RF_PATH_A)
+ write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); // PAD all on.
+ else if (rfPath == RF_PATH_B)
+ write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); // PAD all on.
+ write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.
+ rtw_usleep_os(100);
+ }
+ else
+ {
+ write_rfreg(pAdapter, rfPath, 0x21, 0xd4000);
+ rtw_usleep_os(100);
+ write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on.
+ rtw_usleep_os(100);
+ }
+
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
+
+ }
+ else// Stop Single Tone.
+ {
+ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n"));
+ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1);
+ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1);
+
+ if (is92C) {
+ _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00);
+ rtw_usleep_os(100);
+ write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); // PAD all on.
+ write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); // PAD all on.
+ rtw_usleep_os(100);
+ } else {
+ write_rfreg(pAdapter, rfPath, 0x21, 0x54000);
+ rtw_usleep_os(100);
+ write_rfreg(pAdapter, rfPath, 0x00, 0x30000); // PAD all on.
+ rtw_usleep_os(100);
+ }
+
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
+
+ }
+
+}
+
+
+void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
+{
+ pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart;
+ if (bStart) // Start Carrier Suppression.
+ {
+ RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n"));
+ //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)
+ if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
+ {
+ // 1. if CCK block on?
+ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
+ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on
+
+ //Turn Off All Test Mode
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
+
+ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
+ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); //turn off scramble setting
+
+ //Set CCK Tx Test Rate
+ //PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate);
+ write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); //Set FTxRate to 1Mbps
+ }
+
+ //Set for dynamic set Power index
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
+
+ }
+ else// Stop Carrier Suppression.
+ {
+ RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n"));
+ //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B)
+ if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) {
+ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode
+ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); //turn on scramble setting
+
+ //BB Reset
+ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
+ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
+ }
+ //Stop for dynamic set Power index
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
+ }
+ //DbgPrint("\n MPT_ProSetCarrierSupp() is finished. \n");
+}
+
+void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart)
+{
+ u32 cckrate;
+
+ if (bStart)
+ {
+ RT_TRACE(_module_mp_, _drv_alert_,
+ ("SetCCKContinuousTx: test start\n"));
+
+ // 1. if CCK block on?
+ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn))
+ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on
+
+ //Turn Off All Test Mode
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
+ //Set CCK Tx Test Rate
+ #if 0
+ switch(pAdapter->mppriv.rateidx)
+ {
+ case 2:
+ cckrate = 0;
+ break;
+ case 4:
+ cckrate = 1;
+ break;
+ case 11:
+ cckrate = 2;
+ break;
+ case 22:
+ cckrate = 3;
+ break;
+ default:
+ cckrate = 0;
+ break;
+ }
+ #else
+ cckrate = pAdapter->mppriv.rateidx;
+ #endif
+ write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
+ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode
+ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
+
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
+
+ // Patch for CCK 11M waveform
+ if (cckrate == MPT_RATE_1M)
+ write_bbreg(pAdapter, 0xA71, BIT(6), bDisable);
+ else
+ write_bbreg(pAdapter, 0xA71, BIT(6), bEnable);
+
+
+ }
+ else {
+ RT_TRACE(_module_mp_, _drv_info_,
+ ("SetCCKContinuousTx: test stop\n"));
+
+ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode
+ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting
+
+ //BB Reset
+ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
+ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
+
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
+ }
+
+ pAdapter->mppriv.MptCtx.bCckContTx = bStart;
+ pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE;
+}/* mpt_StartCckContTx */
+
+void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+
+ if (bStart) {
+ RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n"));
+ // 1. if OFDM block on?
+ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
+ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on
+ {
+
+ // 2. set CCK test mode off, set to CCK normal mode
+ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
+
+ // 3. turn on scramble setting
+ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
+ }
+ // 4. Turn On Continue Tx and turn off the other test modes.
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
+
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000500);
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000500);
+
+ } else {
+ RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n"));
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
+ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
+ //Delay 10 ms
+ rtw_msleep_os(10);
+ //BB Reset
+ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
+ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
+
+ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter1, bMaskDWord, 0x01000100);
+ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter1, bMaskDWord, 0x01000100);
+ }
+
+ pAdapter->mppriv.MptCtx.bCckContTx = _FALSE;
+ pAdapter->mppriv.MptCtx.bOfdmContTx = bStart;
+}/* mpt_StartOfdmContTx */
+
+void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart)
+{
+#if 0
+ // ADC turn off [bit24-21] adc port0 ~ port1
+ if (bStart) {
+ write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF);
+ rtw_usleep_os(100);
+ }
+#endif
+ RT_TRACE(_module_mp_, _drv_info_,
+ ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx));
+
+ pAdapter->mppriv.MptCtx.bStartContTx = bStart;
+ if (pAdapter->mppriv.rateidx <= MPT_RATE_11M)
+ {
+ Hal_SetCCKContinuousTx(pAdapter, bStart);
+ }
+ else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) &&
+ (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15))
+ {
+ Hal_SetOFDMContinuousTx(pAdapter, bStart);
+ }
+#if 0
+ // ADC turn on [bit24-21] adc port0 ~ port1
+ if (!bStart) {
+ write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000);
+ }
+#endif
+}
+
+#endif // CONFIG_MP_INCLUDE
+
diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_phycfg.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_phycfg.c index 87e059996a58..0efb64a89055 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_phycfg.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_phycfg.c @@ -1,3397 +1,3406 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#define _RTL8723A_PHYCFG_C_ - -#include <drv_conf.h> -#include <osdep_service.h> -#include <drv_types.h> -#include <rtw_byteorder.h> - -#ifdef CONFIG_IOL -#include <rtw_iol.h> -#endif - -#include <rtl8723a_hal.h> - - -/*---------------------------Define Local Constant---------------------------*/ -/* Channel switch:The size of command tables for switch channel*/ -#define MAX_PRECMD_CNT 16 -#define MAX_RFDEPENDCMD_CNT 16 -#define MAX_POSTCMD_CNT 16 - -#define MAX_DOZE_WAITING_TIMES_9x 64 - -/*---------------------------Define Local Constant---------------------------*/ - - -/*------------------------Define global variable-----------------------------*/ - -/*------------------------Define local variable------------------------------*/ - - -/*--------------------Define export function prototype-----------------------*/ -// Please refer to header file -/*--------------------Define export function prototype-----------------------*/ - -/*----------------------------Function Body----------------------------------*/ -// -// 1. BB register R/W API -// - -/** -* Function: phy_CalculateBitShift -* -* OverView: Get shifted position of the BitMask -* -* Input: -* u4Byte BitMask, -* -* Output: none -* Return: u4Byte Return the shift bit bit position of the mask -*/ -static u32 -phy_CalculateBitShift( - u32 BitMask - ) -{ - u32 i; - - for(i=0; i<=31; i++) - { - if ( ((BitMask>>i) & 0x1 ) == 1) - break; - } - - return (i); -} - - -/** -* Function: PHY_QueryBBReg -* -* OverView: Read "sepcific bits" from BB register -* -* Input: -* PADAPTER Adapter, -* u4Byte RegAddr, //The target address to be readback -* u4Byte BitMask //The target bit position in the target address -* //to be readback -* Output: None -* Return: u4Byte Data //The readback register value -* Note: This function is equal to "GetRegSetting" in PHY programming guide -*/ -u32 -rtl8192c_PHY_QueryBBReg( - IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask - ) -{ - u32 ReturnValue = 0, OriginalValue, BitShift; - u16 BBWaitCounter = 0; - -#if (DISABLE_BB_RF == 1) - return 0; -#endif - - //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask)); - - OriginalValue = rtw_read32(Adapter, RegAddr); - BitShift = phy_CalculateBitShift(BitMask); - ReturnValue = (OriginalValue & BitMask) >> BitShift; - - //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, OriginalValue)); - //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx), OriginalValue(%#lx)\n", RegAddr, BitMask, OriginalValue)); - - return (ReturnValue); - -} - - -/** -* Function: PHY_SetBBReg -* -* OverView: Write "Specific bits" to BB register (page 8~) -* -* Input: -* PADAPTER Adapter, -* u4Byte RegAddr, //The target address to be modified -* u4Byte BitMask //The target bit position in the target address -* //to be modified -* u4Byte Data //The new register value in the target bit position -* //of the target address -* -* Output: None -* Return: None -* Note: This function is equal to "PutRegSetting" in PHY programming guide -*/ - -VOID -rtl8192c_PHY_SetBBReg( - IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //u16 BBWaitCounter = 0; - u32 OriginalValue, BitShift; - -#if (DISABLE_BB_RF == 1) - return; -#endif - - //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); - - if(BitMask!= bMaskDWord){//if not "double word" write - OriginalValue = rtw_read32(Adapter, RegAddr); - BitShift = phy_CalculateBitShift(BitMask); - Data = ((OriginalValue & (~BitMask)) | (Data << BitShift)); - } - - rtw_write32(Adapter, RegAddr, Data); - - //RTPRINT(FPHY, PHY_BBW, ("BBW MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, Data)); - //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); - -} - - -// -// 2. RF register R/W API -// - -/*----------------------------------------------------------------------------- - * Function: phy_FwRFSerialRead() - * - * Overview: We support firmware to execute RF-R/W. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 01/21/2008 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -static u32 -phy_FwRFSerialRead( - IN PADAPTER Adapter, - IN RF_RADIO_PATH_E eRFPath, - IN u32 Offset ) -{ - u32 retValue = 0; - //RT_ASSERT(FALSE,("deprecate!\n")); - return (retValue); - -} /* phy_FwRFSerialRead */ - - -/*----------------------------------------------------------------------------- - * Function: phy_FwRFSerialWrite() - * - * Overview: We support firmware to execute RF-R/W. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 01/21/2008 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -static VOID -phy_FwRFSerialWrite( - IN PADAPTER Adapter, - IN RF_RADIO_PATH_E eRFPath, - IN u32 Offset, - IN u32 Data ) -{ - //RT_ASSERT(FALSE,("deprecate!\n")); -} - - -/** -* Function: phy_RFSerialRead -* -* OverView: Read regster from RF chips -* -* Input: -* PADAPTER Adapter, -* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D -* u4Byte Offset, //The target address to be read -* -* Output: None -* Return: u4Byte reback value -* Note: Threre are three types of serial operations: -* 1. Software serial write -* 2. Hardware LSSI-Low Speed Serial Interface -* 3. Hardware HSSI-High speed -* serial write. Driver need to implement (1) and (2). -* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() -*/ -static u32 -phy_RFSerialRead( - IN PADAPTER Adapter, - IN RF_RADIO_PATH_E eRFPath, - IN u32 Offset - ) -{ - u32 retValue = 0; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath]; - u32 NewOffset; - u32 tmplong,tmplong2; - u8 RfPiEnable=0; -#if 0 - if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs - return retValue; - if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs - return retValue; -#endif - // - // Make sure RF register offset is correct - // - Offset &= 0x3f; - - // - // Switch page for 8256 RF IC - // - NewOffset = Offset; - - // 2009/06/17 MH We can not execute IO for power save or other accident mode. - //if(RT_CANNOT_IO(Adapter)) - //{ - // RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n")); - // return 0xFFFFFFFF; - //} - - // For 92S LSSI Read RFLSSIRead - // For RF A/B write 0x824/82c(does not work in the future) - // We must use 0x824 for RF A and B to execute read trigger - tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord); - if(eRFPath == RF_PATH_A) - tmplong2 = tmplong; - else - tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord); - - tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; //T65 RF - - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge)); - rtw_udelay_os(10);// PlatformStallExecution(10); - - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); - rtw_udelay_os(100);//PlatformStallExecution(100); - - PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge); - rtw_udelay_os(10);//PlatformStallExecution(10); - - if(eRFPath == RF_PATH_A) - RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8); - else if(eRFPath == RF_PATH_B) - RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8); - - if(RfPiEnable) - { // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF - retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData); - //DBG_8192C("Readback from RF-PI : 0x%x\n", retValue); - } - else - { //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF - retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); - //DBG_8192C("Readback from RF-SI : 0x%x\n", retValue); - } - //DBG_8192C("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue); - - return retValue; - -} - - - -/** -* Function: phy_RFSerialWrite -* -* OverView: Write data to RF register (page 8~) -* -* Input: -* PADAPTER Adapter, -* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D -* u4Byte Offset, //The target address to be read -* u4Byte Data //The new register Data in the target bit position -* //of the target to be read -* -* Output: None -* Return: None -* Note: Threre are three types of serial operations: -* 1. Software serial write -* 2. Hardware LSSI-Low Speed Serial Interface -* 3. Hardware HSSI-High speed -* serial write. Driver need to implement (1) and (2). -* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() - * - * Note: For RF8256 only - * The total count of RTL8256(Zebra4) register is around 36 bit it only employs - * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10]) - * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration - * programming guide" for more details. - * Thus, we define a sub-finction for RTL8526 register address conversion - * =========================================================== - * Register Mode RegCTL[1] RegCTL[0] Note - * (Reg00[12]) (Reg00[10]) - * =========================================================== - * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) - * ------------------------------------------------------------------ - * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) - * ------------------------------------------------------------------ - * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) - * ------------------------------------------------------------------ - * - * 2008/09/02 MH Add 92S RF definition - * - * - * -*/ -static VOID -phy_RFSerialWrite( - IN PADAPTER Adapter, - IN RF_RADIO_PATH_E eRFPath, - IN u32 Offset, - IN u32 Data - ) -{ - u32 DataAndAddr = 0; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath]; - u32 NewOffset; - -#if 0 - //<Roger_TODO> We should check valid regs for RF_6052 case. - if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs - return; - if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs - return; -#endif - - // 2009/06/17 MH We can not execute IO for power save or other accident mode. - //if(RT_CANNOT_IO(Adapter)) - //{ - // RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n")); - // return; - //} - - Offset &= 0x3f; - - // - // Shadow Update - // - //PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); - - // - // Switch page for 8256 RF IC - // - NewOffset = Offset; - - // - // Put write addr in [5:0] and write data in [31:16] - // - //DataAndAddr = (Data<<16) | (NewOffset&0x3f); - DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF - - // - // Write Operation - // - PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); - //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); - -} - - -/** -* Function: PHY_QueryRFReg -* -* OverView: Query "Specific bits" to RF register (page 8~) -* -* Input: -* PADAPTER Adapter, -* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D -* u4Byte RegAddr, //The target address to be read -* u4Byte BitMask //The target bit position in the target address -* //to be read -* -* Output: None -* Return: u4Byte Readback value -* Note: This function is equal to "GetRFRegSetting" in PHY programming guide -*/ -u32 -rtl8192c_PHY_QueryRFReg( - IN PADAPTER Adapter, - IN RF_RADIO_PATH_E eRFPath, - IN u32 RegAddr, - IN u32 BitMask - ) -{ - u32 Original_Value, Readback_Value, BitShift; - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //u8 RFWaitCounter = 0; - //_irqL irqL; - -#if (DISABLE_BB_RF == 1) - return 0; -#endif - - //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), BitMask(%#lx)\n", RegAddr, eRFPath,BitMask)); - -#ifdef CONFIG_USB_HCI - //PlatformAcquireMutex(&pHalData->mxRFOperate); -#else - //_enter_critical(&pHalData->rf_lock, &irqL); -#endif - - - Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); - - BitShift = phy_CalculateBitShift(BitMask); - Readback_Value = (Original_Value & BitMask) >> BitShift; - -#ifdef CONFIG_USB_HCI - //PlatformReleaseMutex(&pHalData->mxRFOperate); -#else - //_exit_critical(&pHalData->rf_lock, &irqL); -#endif - - - //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%lx Addr[0x%lx]=0x%lx\n", eRFPath, BitMask, RegAddr, Original_Value));//BitMask(%#lx),BitMask, - //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), Original_Value(%#lx)\n", - // RegAddr, eRFPath, Original_Value)); - - return (Readback_Value); -} - -/** -* Function: PHY_SetRFReg -* -* OverView: Write "Specific bits" to RF register (page 8~) -* -* Input: -* PADAPTER Adapter, -* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D -* u4Byte RegAddr, //The target address to be modified -* u4Byte BitMask //The target bit position in the target address -* //to be modified -* u4Byte Data //The new register Data in the target bit position -* //of the target address -* -* Output: None -* Return: None -* Note: This function is equal to "PutRFRegSetting" in PHY programming guide -*/ -VOID -rtl8192c_PHY_SetRFReg( - IN PADAPTER Adapter, - IN RF_RADIO_PATH_E eRFPath, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data - ) -{ - - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - //u1Byte RFWaitCounter = 0; - u32 Original_Value, BitShift; - //_irqL irqL; - -#if (DISABLE_BB_RF == 1) - return; -#endif - - //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n", - // RegAddr, BitMask, Data, eRFPath)); - //RTPRINT(FINIT, INIT_RF, ("PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n", - // RegAddr, BitMask, Data, eRFPath)); - - -#ifdef CONFIG_USB_HCI - //PlatformAcquireMutex(&pHalData->mxRFOperate); -#else - //_enter_critical(&pHalData->rf_lock, &irqL); -#endif - - - // RF data is 12 bits only - if (BitMask != bRFRegOffsetMask) - { - Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); - BitShift = phy_CalculateBitShift(BitMask); - Data = ((Original_Value & (~BitMask)) | (Data<< BitShift)); - } - - phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data); - - -#ifdef CONFIG_USB_HCI - //PlatformReleaseMutex(&pHalData->mxRFOperate); -#else - //_exit_critical(&pHalData->rf_lock, &irqL); -#endif - - //PHY_QueryRFReg(Adapter,eRFPath,RegAddr,BitMask); - //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n", - // RegAddr, BitMask, Data, eRFPath)); - -} - - -// -// 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. -// - -/*----------------------------------------------------------------------------- - * Function: phy_ConfigMACWithParaFile() - * - * Overview: This function read BB parameters from general file format, and do register - * Read/Write - * - * Input: PADAPTER Adapter - * ps1Byte pFileName - * - * Output: NONE - * - * Return: RT_STATUS_SUCCESS: configuration file exist - * - * Note: The format of MACPHY_REG.txt is different from PHY and RF. - * [Register][Mask][Value] - *---------------------------------------------------------------------------*/ -static int -phy_ConfigMACWithParaFile( - IN PADAPTER Adapter, - IN u8* pFileName -) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - int rtStatus = _SUCCESS; - - return rtStatus; -} - -/*----------------------------------------------------------------------------- - * Function: phy_ConfigMACWithHeaderFile() - * - * Overview: This function read BB parameters from Header file we gen, and do register - * Read/Write - * - * Input: PADAPTER Adapter - * ps1Byte pFileName - * - * Output: NONE - * - * Return: RT_STATUS_SUCCESS: configuration file exist - * - * Note: The format of MACPHY_REG.txt is different from PHY and RF. - * [Register][Mask][Value] - *---------------------------------------------------------------------------*/ -#ifndef CONFIG_PHY_SETTING_WITH_ODM -static int -phy_ConfigMACWithHeaderFile( - IN PADAPTER Adapter -) -{ - u32 i = 0; - u32 ArrayLength = 0; - u32* ptrArray; - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - //2008.11.06 Modified by tynli. - //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read Rtl819XMACPHY_Array\n")); - ArrayLength = Rtl8723_MAC_ArrayLength; - ptrArray = (u32*)Rtl8723_MAC_Array; - -#ifdef CONFIG_IOL_MAC - { - struct xmit_frame *xmit_frame; - if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) - return _FAIL; - - for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column - rtw_IOL_append_WB_cmd(xmit_frame, ptrArray[i], (u8)ptrArray[i+1]); - } - - return rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0); - } -#else - for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column - rtw_write8(Adapter, ptrArray[i], (u8)ptrArray[i+1]); - } -#endif - - return _SUCCESS; - -} -#endif//#ifndef CONFIG_PHY_SETTING_WITH_ODM - -/*----------------------------------------------------------------------------- - * Function: PHY_MACConfig8192C - * - * Overview: Condig MAC by header file or parameter file. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 08/12/2008 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -s32 PHY_MACConfig8723A(PADAPTER Adapter) -{ - int rtStatus = _SUCCESS; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - s8 *pszMACRegFile; - s8 sz8723MACRegFile[] = RTL8723_PHY_MACREG; - BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID); - - - pszMACRegFile = sz8723MACRegFile; - - // - // Config MAC - // -#ifdef CONFIG_EMBEDDED_FWIMG - #ifdef CONFIG_PHY_SETTING_WITH_ODM - if(HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv)) - rtStatus = _FAIL; - #else - rtStatus = phy_ConfigMACWithHeaderFile(Adapter); - #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM -#else - - // Not make sure EEPROM, add later - //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read MACREG.txt\n")); - rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile); -#endif//CONFIG_EMBEDDED_FWIMG - -#ifdef CONFIG_PCI_HCI - //this switching setting cause some 8192cu hw have redownload fw fail issue - //improve 2-stream TX EVM by Jenyu - if(is92C) - rtw_write8(Adapter, REG_SPS0_CTRL+3,0x71); -#endif - - - // 2010.07.13 AMPDU aggregation number 9 - //rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); - rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0A); //By tynli. 2010.11.18. -#ifdef CONFIG_USB_HCI - if(is92C && (BOARD_USB_DONGLE == pHalData->BoardType)) - rtw_write8(Adapter, 0x40,0x04); -#endif - - return rtStatus; - -} - - -/** -* Function: phy_InitBBRFRegisterDefinition -* -* OverView: Initialize Register definition offset for Radio Path A/B/C/D -* -* Input: -* PADAPTER Adapter, -* -* Output: None -* Return: None -* Note: The initialization value is constant and it should never be changes -*/ -static VOID -phy_InitBBRFRegisterDefinition( - IN PADAPTER Adapter -) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - // RF Interface Sowrtware Control - pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 - pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) - pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 - pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) - - // RF Interface Readback Value - pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 - pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) - pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 - pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) - - // RF Interface Output (and Enable) - pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 - pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 - - // RF Interface (Output and) Enable - pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) - pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) - - //Addr of LSSI. Wirte RF register by driver - pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter - pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; - - // RF parameter - pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select - pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; - pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; - pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; - - // Tx AGC Gain Stage (same for all path. Should we remove this?) - pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage - pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage - pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage - pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage - - // Tranceiver A~D HSSI Parameter-1 - pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 - pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 - - // Tranceiver A~D HSSI Parameter-2 - pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 - pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 - - // RF switch Control - pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control - pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; - pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; - pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; - - // AGC control 1 - pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; - pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; - pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; - pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; - - // AGC control 2 - pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; - pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; - pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; - pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; - - // RX AFE control 1 - pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; - pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; - pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; - pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; - - // RX AFE control 1 - pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE; - pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; - pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; - pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; - - // Tx AFE control 1 - pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; - pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; - pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; - pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; - - // Tx AFE control 2 - pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE; - pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; - pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; - pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; - - // Tranceiver LSSI Readback SI mode - pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; - pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; - pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; - pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; - - // Tranceiver LSSI Readback PI mode - pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; - pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; - //pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack; - //pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack; - -} - - -/*----------------------------------------------------------------------------- - * Function: phy_ConfigBBWithParaFile() - * - * Overview: This function read BB parameters from general file format, and do register - * Read/Write - * - * Input: PADAPTER Adapter - * ps1Byte pFileName - * - * Output: NONE - * - * Return: RT_STATUS_SUCCESS: configuration file exist - * 2008/11/06 MH For 92S we do not support silent reset now. Disable - * parameter file compare!!!!!!?? - * - *---------------------------------------------------------------------------*/ -static int -phy_ConfigBBWithParaFile( - IN PADAPTER Adapter, - IN u8* pFileName -) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - int rtStatus = _SUCCESS; - - return rtStatus; -} - - - -//**************************************** -// The following is for High Power PA -//**************************************** -VOID -phy_ConfigBBExternalPA( - IN PADAPTER Adapter -) -{ -#ifdef CONFIG_USB_HCI - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u16 i=0; - u32 temp=0; - - if(!pHalData->ExternalPA) - { - return; - } - - // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the - // same code as SU. It is already updated in PHY_REG_1T_HP.txt. -#if 0 - PHY_SetBBReg(Adapter, 0xee8, BIT28, 1); - temp = PHY_QueryBBReg(Adapter, 0x860, bMaskDWord); - temp |= (BIT26|BIT21|BIT10|BIT5); - PHY_SetBBReg(Adapter, 0x860, bMaskDWord, temp); - PHY_SetBBReg(Adapter, 0x870, BIT10, 0); - PHY_SetBBReg(Adapter, 0xc80, bMaskDWord, 0x20000080); - PHY_SetBBReg(Adapter, 0xc88, bMaskDWord, 0x40000100); -#endif - -#endif -} - -/*----------------------------------------------------------------------------- - * Function: phy_ConfigBBWithHeaderFile() - * - * Overview: This function read BB parameters from general file format, and do register - * Read/Write - * - * Input: PADAPTER Adapter - * u1Byte ConfigType 0 => PHY_CONFIG - * 1 =>AGC_TAB - * - * Output: NONE - * - * Return: RT_STATUS_SUCCESS: configuration file exist - * - *---------------------------------------------------------------------------*/ -#ifndef CONFIG_PHY_SETTING_WITH_ODM -static int -phy_ConfigBBWithHeaderFile( - IN PADAPTER Adapter, - IN u8 ConfigType -) -{ - int i; - u32* Rtl819XPHY_REGArray_Table; - u32* Rtl819XAGCTAB_Array_Table; - u16 PHY_REGArrayLen, AGCTAB_ArrayLen; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - int ret = _SUCCESS; - - - AGCTAB_ArrayLen = Rtl8723_AGCTAB_1TArrayLength; - Rtl819XAGCTAB_Array_Table = (u32*)Rtl8723_AGCTAB_1TArray; - PHY_REGArrayLen = Rtl8723_PHY_REG_1TArrayLength; - Rtl819XPHY_REGArray_Table = (u32*)Rtl8723_PHY_REG_1TArray; -// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8723AGCTAB_1TArray\n")); -// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8723PHY_REG_1TArray\n")); - - if(ConfigType == BaseBand_Config_PHY_REG) - { - #ifdef CONFIG_IOL_BB_PHY_REG - { - struct xmit_frame *xmit_frame; - u32 tmp_value; - - if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) { - ret = _FAIL; - goto exit; - } - - for(i=0;i<PHY_REGArrayLen;i=i+2) - { - tmp_value=Rtl819XPHY_REGArray_Table[i+1]; - - if (Rtl819XPHY_REGArray_Table[i] == 0xfe) - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50); - else if (Rtl819XPHY_REGArray_Table[i] == 0xfd) - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5); - else if (Rtl819XPHY_REGArray_Table[i] == 0xfc) - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1); - else if (Rtl819XPHY_REGArray_Table[i] == 0xfb) - rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50); - else if (Rtl819XPHY_REGArray_Table[i] == 0xfa) - rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5); - else if (Rtl819XPHY_REGArray_Table[i] == 0xf9) - rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1); - - rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XPHY_REGArray_Table[i], tmp_value); - //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1])); - } - - ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0); - } - #else - for(i=0;i<PHY_REGArrayLen;i=i+2) - { - if (Rtl819XPHY_REGArray_Table[i] == 0xfe){ - #ifdef CONFIG_LONG_DELAY_ISSUE - rtw_msleep_os(50); - #else - rtw_mdelay_os(50); - #endif - } - else if (Rtl819XPHY_REGArray_Table[i] == 0xfd) - rtw_mdelay_os(5); - else if (Rtl819XPHY_REGArray_Table[i] == 0xfc) - rtw_mdelay_os(1); - else if (Rtl819XPHY_REGArray_Table[i] == 0xfb) - rtw_udelay_os(50); - else if (Rtl819XPHY_REGArray_Table[i] == 0xfa) - rtw_udelay_os(5); - else if (Rtl819XPHY_REGArray_Table[i] == 0xf9) - rtw_udelay_os(1); - - PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]); - - // Add 1us delay between BB/RF register setting. - rtw_udelay_os(1); - - //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1])); - } - #endif - // for External PA - phy_ConfigBBExternalPA(Adapter); - } - else if(ConfigType == BaseBand_Config_AGC_TAB) - { - #ifdef CONFIG_IOL_BB_AGC_TAB - { - struct xmit_frame *xmit_frame; - - if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) { - ret = _FAIL; - goto exit; - } - - for(i=0;i<AGCTAB_ArrayLen;i=i+2) - { - rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]); - //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XAGCTAB_Array_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1])); - } - - ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0); - } - #else - for(i=0;i<AGCTAB_ArrayLen;i=i+2) - { - PHY_SetBBReg(Adapter, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]); - - // Add 1us delay between BB/RF register setting. - rtw_udelay_os(1); - - //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XAGCTAB_Array_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1])); - } - #endif - } - -exit: - return ret; -} - -#endif -VOID -storePwrIndexDiffRateOffset( - IN PADAPTER Adapter, - IN u32 RegAddr, - IN u32 BitMask, - IN u32 Data - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - if(RegAddr == rTxAGC_A_Rate18_06) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0])); - } - if(RegAddr == rTxAGC_A_Rate54_24) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1])); - } - if(RegAddr == rTxAGC_A_CCK1_Mcs32) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6])); - } - if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7])); - } - if(RegAddr == rTxAGC_A_Mcs03_Mcs00) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2])); - } - if(RegAddr == rTxAGC_A_Mcs07_Mcs04) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3])); - } - if(RegAddr == rTxAGC_A_Mcs11_Mcs08) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4])); - } - if(RegAddr == rTxAGC_A_Mcs15_Mcs12) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5])); - } - if(RegAddr == rTxAGC_B_Rate18_06) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8])); - } - if(RegAddr == rTxAGC_B_Rate54_24) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9])); - } - if(RegAddr == rTxAGC_B_CCK1_55_Mcs32) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14])); - } - if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15])); - } - if(RegAddr == rTxAGC_B_Mcs03_Mcs00) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10])); - } - if(RegAddr == rTxAGC_B_Mcs07_Mcs04) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11])); - } - if(RegAddr == rTxAGC_B_Mcs11_Mcs08) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12])); - } - if(RegAddr == rTxAGC_B_Mcs15_Mcs12) - { - pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data; - //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%lx\n", pHalData->pwrGroupCnt, - // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13])); - pHalData->pwrGroupCnt++; - } -} -/*----------------------------------------------------------------------------- - * Function: phy_ConfigBBWithPgParaFile - * - * Overview: - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 11/06/2008 MHC Create Version 0. - * 2009/07/29 tynli (porting from 92SE branch)2009/03/11 Add copy parameter file to buffer for silent reset - *---------------------------------------------------------------------------*/ -static int -phy_ConfigBBWithPgParaFile( - IN PADAPTER Adapter, - IN u8* pFileName) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - int rtStatus = _SUCCESS; - - - return rtStatus; - -} /* phy_ConfigBBWithPgParaFile */ - - -/*----------------------------------------------------------------------------- - * Function: phy_ConfigBBWithPgHeaderFile - * - * Overview: Config PHY_REG_PG array - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!! - * 11/10/2008 tynli Modify to mew files. - *---------------------------------------------------------------------------*/ -static int -phy_ConfigBBWithPgHeaderFile( - IN PADAPTER Adapter, - IN u8 ConfigType) -{ - int i; - u32* Rtl819XPHY_REGArray_Table_PG; - u16 PHY_REGArrayPGLen; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - - PHY_REGArrayPGLen = Rtl8723_PHY_REG_Array_PGLength; - Rtl819XPHY_REGArray_Table_PG = (u32*)Rtl8723_PHY_REG_Array_PG; - - if(ConfigType == BaseBand_Config_PHY_REG) - { - for(i=0;i<PHY_REGArrayPGLen;i=i+3) - { - #if 0 //without IO, no delay is neeeded... - if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe){ - #ifdef CONFIG_LONG_DELAY_ISSUE - rtw_msleep_os(50); - #else - rtw_mdelay_os(50); - #endif - } - else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd) - rtw_mdelay_os(5); - else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc) - rtw_mdelay_os(1); - else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb) - rtw_udelay_os(50); - else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa) - rtw_udelay_os(5); - else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9) - rtw_udelay_os(1); - //PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]); - #endif - - storePwrIndexDiffRateOffset(Adapter, Rtl819XPHY_REGArray_Table_PG[i], - Rtl819XPHY_REGArray_Table_PG[i+1], - Rtl819XPHY_REGArray_Table_PG[i+2]); - //RT_TRACE(COMP_SEND, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1])); - } - } - else - { - - //RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n")); - } - - return _SUCCESS; - -} /* phy_ConfigBBWithPgHeaderFile */ - -#if (MP_DRIVER == 1) - -/*----------------------------------------------------------------------------- - * Function: phy_ConfigBBWithMpParaFile() - * - * Overview: This function read BB parameters from general file format, and do register - * Read/Write - * - * Input: PADAPTER Adapter - * ps1Byte pFileName - * - * Output: NONE - * - * Return: RT_STATUS_SUCCESS: configuration file exist - * 2008/11/06 MH For 92S we do not support silent reset now. Disable - * parameter file compare!!!!!!?? - * - *---------------------------------------------------------------------------*/ -static int -phy_ConfigBBWithMpParaFile( - IN PADAPTER Adapter, - IN u8* pFileName -) -{ -#if 1 - int rtStatus = _SUCCESS; -#else - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - s4Byte nLinesRead, ithLine; - RT_STATUS rtStatus = RT_STATUS_SUCCESS; - ps1Byte szLine; - u4Byte u4bRegOffset, u4bRegMask, u4bRegValue; - u4Byte u4bMove; - - if(ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FIRST_INIT)) - { - rtStatus = PlatformReadFile( - Adapter, - pFileName, - (pu1Byte)(pHalData->BufOfLines), - MAX_LINES_HWCONFIG_TXT, - MAX_BYTES_LINE_HWCONFIG_TXT, - &nLinesRead - ); - if(rtStatus == RT_STATUS_SUCCESS) - { - PlatformMoveMemory(pHalData->BufOfLines6, pHalData->BufOfLines, nLinesRead*MAX_BYTES_LINE_HWCONFIG_TXT); - pHalData->nLinesRead6 = nLinesRead; - } - else - { - // Temporarily skip PHY_REG_MP.txt if file does not exist. - pHalData->nLinesRead6 = 0; - RT_TRACE(COMP_INIT, DBG_LOUD, ("No matched file \r\n")); - return RT_STATUS_SUCCESS; - } - } - else - { - PlatformMoveMemory(pHalData->BufOfLines, pHalData->BufOfLines6, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); - nLinesRead = pHalData->nLinesRead6; - rtStatus = RT_STATUS_SUCCESS; - } - - - if(rtStatus == RT_STATUS_SUCCESS) - { - RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_ConfigBBWithMpParaFile(): read %s ok\n", pFileName)); - - for(ithLine = 0; ithLine < nLinesRead; ithLine++) - { - szLine = pHalData->BufOfLines[ithLine]; - - if(!IsCommentString(szLine)) - { - // Get 1st hex value as register offset. - if(GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) - { - if(u4bRegOffset == 0xff) - { // Ending. - break; - } - else if (u4bRegOffset == 0xfe) - delay_ms(50); - else if (u4bRegOffset == 0xfd) - delay_ms(5); - else if (u4bRegOffset == 0xfc) - delay_ms(1); - else if (u4bRegOffset == 0xfb) - PlatformStallExecution(50); - else if (u4bRegOffset == 0xfa) - PlatformStallExecution(5); - else if (u4bRegOffset == 0xf9) - PlatformStallExecution(1); - - // Get 2nd hex value as register value. - szLine += u4bMove; - if(GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) - { - RT_TRACE(COMP_FPGA, DBG_TRACE, ("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue)); - PHY_SetBBReg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue); - - // Add 1us delay between BB/RF register setting. - PlatformStallExecution(1); - } - } - } - } - } - else - { - RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_ConfigBBWithMpParaFile(): Failed%s\n", pFileName)); - } -#endif - - return rtStatus; -} - -/*----------------------------------------------------------------------------- - * Function: phy_ConfigBBWithMpHeaderFile - * - * Overview: Config PHY_REG_MP array - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 02/04/2010 chiyokolin Modify to new files. - *---------------------------------------------------------------------------*/ -static int -phy_ConfigBBWithMpHeaderFile( - IN PADAPTER Adapter, - IN u1Byte ConfigType) -{ - int i; - u32* Rtl8192CPHY_REGArray_Table_MP; - u16 PHY_REGArrayMPLen; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - - PHY_REGArrayMPLen = Rtl8723_PHY_REG_Array_MPLength; - Rtl8192CPHY_REGArray_Table_MP = (u32*)Rtl8723_PHY_REG_Array_MP; - - if(ConfigType == BaseBand_Config_PHY_REG) - { - for(i=0;i<PHY_REGArrayMPLen;i=i+2) - { - if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfe) { - #ifdef CONFIG_LONG_DELAY_ISSUE - rtw_msleep_os(50); - #else - rtw_mdelay_os(50); - #endif - } - else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfd) - rtw_mdelay_os(5); - else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfc) - rtw_mdelay_os(1); - else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfb) { - #ifdef CONFIG_LONG_DELAY_ISSUE - rtw_msleep_os(50); - #else - rtw_mdelay_os(50); - #endif - } - else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfa) - rtw_mdelay_os(5); - else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xf9) - rtw_mdelay_os(1); - PHY_SetBBReg(Adapter, Rtl8192CPHY_REGArray_Table_MP[i], bMaskDWord, Rtl8192CPHY_REGArray_Table_MP[i+1]); - - // Add 1us delay between BB/RF register setting. - rtw_mdelay_os(1); - -// RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl8192CPHY_REGArray_Table_MP[%d] is %lx Rtl8192CPHY_REGArray_Table_MP[%d] is %lx \n", i, i+1, Rtl8192CPHY_REGArray_Table_MP[i], Rtl8192CPHY_REGArray_Table_MP[i+1])); - } - } - else - { -// RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithMpHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n")); - } - - return _SUCCESS; -} /* phy_ConfigBBWithMpHeaderFile */ - -#endif // #if (MP_DRIVER == 1) - -static VOID -phy_BB8192C_Config_1T( - IN PADAPTER Adapter - ) -{ -#if 0 - //for path - A - PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x1); - PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x0303, 0x0101); - PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x1); - PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x1); - PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x1); - PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x1); - PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x1); -#endif - //for path - B - PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2); - PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022); - - // 20100519 Joseph: Add for 1T2R config. Suggested by Kevin, Jenyu and Yunan. - PHY_SetBBReg(Adapter, rCCK0_AFESetting, bMaskByte3, 0x45); - PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x23); - PHY_SetBBReg(Adapter, rOFDM0_AGCParameter1, 0x30, 0x1); // B path first AGC - - PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x2); - PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x2); - PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x2); - PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x2); - PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x2); - - -} - -// Joseph test: new initialize order!! -// Test only!! This part need to be re-organized. -// Now it is just for 8256. -static int -phy_BB8190_Config_HardCode( - IN PADAPTER Adapter - ) -{ - //RT_ASSERT(FALSE, ("This function is not implement yet!! \n")); - return _SUCCESS; -} - -static int -phy_BB8723a_Config_ParaFile( - IN PADAPTER Adapter - ) -{ - EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - int rtStatus = _SUCCESS; - - u8 sz8723BBRegFile[] = RTL8723_PHY_REG; - u8 sz8723AGCTableFile[] = RTL8723_AGC_TAB; - u8 sz8723BBRegPgFile[] = RTL8723_PHY_REG_PG; - u8 sz8723BBRegMpFile[] = RTL8723_PHY_REG_MP; - - u8 *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile=NULL; - - - //RT_TRACE(COMP_INIT, DBG_TRACE, ("==>phy_BB8192S_Config_ParaFile\n")); - - pszBBRegFile = sz8723BBRegFile ; - pszAGCTableFile = sz8723AGCTableFile; - pszBBRegPgFile = sz8723BBRegPgFile; - pszBBRegMpFile = sz8723BBRegMpFile; - - // - // 1. Read PHY_REG.TXT BB INIT!! - // We will seperate as 88C / 92C according to chip version - // -#ifdef CONFIG_EMBEDDED_FWIMG - #ifdef CONFIG_PHY_SETTING_WITH_ODM - if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG)) - rtStatus = _FAIL; - #else - rtStatus = phy_ConfigBBWithHeaderFile(Adapter, BaseBand_Config_PHY_REG); - #endif -#else - // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different - // type of parameter files to phy_reg.txt at first. - rtStatus = phy_ConfigBBWithParaFile(Adapter,pszBBRegFile); -#endif//#ifdef CONFIG_EMBEDDED_FWIMG - - if(rtStatus != _SUCCESS){ - //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!")); - goto phy_BB8190_Config_ParaFile_Fail; - } - -#if MP_DRIVER == 1 - if (Adapter->registrypriv.mp_mode == 1) - { - // - // 1.1 Read PHY_REG_MP.TXT BB INIT!! - // We will seperate as 88C / 92C according to chip version - // -#ifdef CONFIG_EMBEDDED_FWIMG - rtStatus = phy_ConfigBBWithMpHeaderFile(Adapter, BaseBand_Config_PHY_REG); -#else - // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different - // type of parameter files to phy_reg.txt at first. - rtStatus = phy_ConfigBBWithMpParaFile(Adapter, pszBBRegMpFile); -#endif - - if(rtStatus != _SUCCESS){ -// RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg MP Fail!!")); - goto phy_BB8190_Config_ParaFile_Fail; - } - } -#endif // #if (MP_DRIVER == 1) - - // - // 20100318 Joseph: Config 2T2R to 1T2R if necessary. - // - if(pHalData->rf_type == RF_1T2R) - { - phy_BB8192C_Config_1T(Adapter); - DBG_8192C("phy_BB8723a_Config_ParaFile():Config to 1T!!\n"); - } - - // - // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt - // - if (pEEPROM->bautoload_fail_flag == _FALSE) - { - pHalData->pwrGroupCnt = 0; - -#ifdef CONFIG_EMBEDDED_FWIMG - rtStatus = phy_ConfigBBWithPgHeaderFile(Adapter, BaseBand_Config_PHY_REG); -#else - rtStatus = phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile); -#endif - } - - if(rtStatus != _SUCCESS){ - //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!")); - goto phy_BB8190_Config_ParaFile_Fail; - } - - // - // 3. BB AGC table Initialization - // -#ifdef CONFIG_EMBEDDED_FWIMG - #ifdef CONFIG_PHY_SETTING_WITH_ODM - if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB)) - rtStatus = _FAIL; - #else - rtStatus = phy_ConfigBBWithHeaderFile(Adapter, BaseBand_Config_AGC_TAB); - #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM -#else - //RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_BB8192S_Config_ParaFile AGC_TAB.txt\n")); - rtStatus = phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile); -#endif - - if(rtStatus != _SUCCESS){ - //RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n")); - goto phy_BB8190_Config_ParaFile_Fail; - } - -phy_BB8190_Config_ParaFile_Fail: - - return rtStatus; -} - - -int -PHY_BBConfig8723A( - IN PADAPTER Adapter - ) -{ - int rtStatus = _SUCCESS; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u32 RegVal; - u8 TmpU1B=0; - u8 value8,CrystalCap; - - phy_InitBBRFRegisterDefinition(Adapter); - - if(IS_HARDWARE_TYPE_8723A(Adapter)) - { - // Suggested by Scott. tynli_test. 2010.12.30. - //1. 0x28[1] = 1 - TmpU1B = rtw_read8(Adapter, REG_AFE_PLL_CTRL); - rtw_udelay_os(2); - rtw_write8(Adapter, REG_AFE_PLL_CTRL, (TmpU1B|BIT1)); - rtw_udelay_os(2); - - //2. 0x29[7:0] = 0xFF - rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff); - rtw_udelay_os(2); - - //3. 0x02[1:0] = 2b'11 - TmpU1B = rtw_read8(Adapter, REG_SYS_FUNC_EN); - rtw_write8(Adapter, REG_SYS_FUNC_EN, (TmpU1B|FEN_BB_GLB_RSTn|FEN_BBRSTB)); - - //4. 0x25[6] = 0 - TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+1); - rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, (TmpU1B&(~BIT6))); - - //5. 0x24[20] = 0 //Advised by SD3 Alex Wang. 2011.02.09. - TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+2); - rtw_write8(Adapter, REG_AFE_XTAL_CTRL+2, (TmpU1B&(~BIT4))); - - //6. 0x1f[7:0] = 0x07 - rtw_write8(Adapter, REG_RF_CTRL, 0x07); - } - else - { - // Enable BB and RF - RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN); - rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1)); - - // 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. - rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83); - rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb); - - rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB); - -#ifdef CONFIG_USB_HCI - rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB); -#else - rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB); -#endif - - // 2009/10/21 by SD1 Jong. Modified by tynli. Not in Documented in V8.1. -#ifdef CONFIG_USB_HCI - //To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23. - rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f); - rtw_write8(Adapter, 0x15, 0xe9); -#endif - - rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80); - -#ifdef CONFIG_PCI_HCI - // Force use left antenna by default for 88C. - // if(!IS_92C_SERIAL(pHalData->VersionID) || IS_92C_1T2R(pHalData->VersionID)) - if(Adapter->ledpriv.LedStrategy != SW_LED_MODE10) - { - RegVal = rtw_read32(Adapter, REG_LEDCFG0); - rtw_write32(Adapter, REG_LEDCFG0, RegVal|BIT23); - } -#endif - } - - // - // Config BB and AGC - // - rtStatus = phy_BB8723a_Config_ParaFile(Adapter); - -#ifdef CONFIG_USB_HCI - if(IS_HARDWARE_TYPE_8192CU(Adapter)&&IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) - &&(pHalData->BoardType == BOARD_USB_High_PA)) - rtw_write8(Adapter, 0xc72, 0x50); -#endif -//only for B-cut - if(IS_HARDWARE_TYPE_8723A(Adapter) && pHalData->EEPROMVersion >= 0x01) - { - CrystalCap = pHalData->CrystalCap & 0x3F; - PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6))); - } - - if(IS_HARDWARE_TYPE_8723AE(Adapter)) - PHY_SetBBReg(Adapter, REG_LDOA15_CTRL, bMaskDWord, 0x01572505); - return rtStatus; -} - - -int -PHY_RFConfig8723A( - IN PADAPTER Adapter - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - int rtStatus = _SUCCESS; - - // - // RF config - // - rtStatus = PHY_RF6052_Config8723A(Adapter); - return rtStatus; -} - - -/*----------------------------------------------------------------------------- - * Function: PHY_ConfigRFWithParaFile() - * - * Overview: This function read RF parameters from general file format, and do RF 3-wire - * - * Input: PADAPTER Adapter - * ps1Byte pFileName - * RF_RADIO_PATH_E eRFPath - * - * Output: NONE - * - * Return: RT_STATUS_SUCCESS: configuration file exist - * - * Note: Delay may be required for RF configuration - *---------------------------------------------------------------------------*/ -int -rtl8192c_PHY_ConfigRFWithParaFile( - IN PADAPTER Adapter, - IN u8* pFileName, - RF_RADIO_PATH_E eRFPath -) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - int rtStatus = _SUCCESS; - - - return rtStatus; - -} - -//**************************************** -// The following is for High Power PA -//**************************************** -#define HighPowerRadioAArrayLen 22 -//This is for High power PA -u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = { -0x013,0x00029ea4, -0x013,0x00025e74, -0x013,0x00020ea4, -0x013,0x0001ced0, -0x013,0x00019f40, -0x013,0x00014e70, -0x013,0x000106a0, -0x013,0x0000c670, -0x013,0x000082a0, -0x013,0x00004270, -0x013,0x00000240, -}; - -int -PHY_ConfigRFExternalPA( - IN PADAPTER Adapter, - RF_RADIO_PATH_E eRFPath -) -{ - int rtStatus = _SUCCESS; -#ifdef CONFIG_USB_HCI - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u16 i=0; - - if(!pHalData->ExternalPA) - { - return rtStatus; - } - - // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the - // same code as SU. It is already updated in radio_a_1T_HP.txt. -#if 0 - //add for SU High Power PA - for(i = 0;i<HighPowerRadioAArrayLen; i=i+2) - { - RT_TRACE(COMP_INIT, DBG_LOUD, ("External PA, write RF 0x%lx=0x%lx\n", Rtl8192S_HighPower_RadioA_Array[i], Rtl8192S_HighPower_RadioA_Array[i+1])); - PHY_SetRFReg(Adapter, eRFPath, Rtl8192S_HighPower_RadioA_Array[i], bRFRegOffsetMask, Rtl8192S_HighPower_RadioA_Array[i+1]); - } -#endif - -#endif - return rtStatus; -} -//**************************************** -/*----------------------------------------------------------------------------- - * Function: PHY_ConfigRFWithHeaderFile() - * - * Overview: This function read RF parameters from general file format, and do RF 3-wire - * - * Input: PADAPTER Adapter - * ps1Byte pFileName - * RF_RADIO_PATH_E eRFPath - * - * Output: NONE - * - * Return: RT_STATUS_SUCCESS: configuration file exist - * - * Note: Delay may be required for RF configuration - *---------------------------------------------------------------------------*/ -#ifndef CONFIG_PHY_SETTING_WITH_ODM -int -rtl8723a_PHY_ConfigRFWithHeaderFile( - IN PADAPTER Adapter, - RF_RADIO_PATH_E eRFPath -) -{ - - int i; - int rtStatus = _SUCCESS; - u32* Rtl819XRadioA_Array_Table; - u32* Rtl819XRadioB_Array_Table; - u16 RadioA_ArrayLen,RadioB_ArrayLen; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - - RadioA_ArrayLen = Rtl8723_RadioA_1TArrayLength; - Rtl819XRadioA_Array_Table = (u32*)Rtl8723_RadioA_1TArray; - RadioB_ArrayLen = Rtl8723_RadioB_1TArrayLength; - Rtl819XRadioB_Array_Table = (u32*)Rtl8723_RadioB_1TArray; -// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_A:Rtl8723RadioA_1TArray\n")); -// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_B:Rtl8723RadioB_1TArray\n")); - - switch (eRFPath) - { - case RF_PATH_A: - #ifdef CONFIG_IOL_RF_RF90_PATH_A - { - struct xmit_frame *xmit_frame; - if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) { - rtStatus = _FAIL; - goto exit; - } - - for(i = 0;i<RadioA_ArrayLen; i=i+2) - { - if(Rtl819XRadioA_Array_Table[i] == 0xfe) - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50); - else if (Rtl819XRadioA_Array_Table[i] == 0xfd) - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5); - else if (Rtl819XRadioA_Array_Table[i] == 0xfc) - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1); - else if (Rtl819XRadioA_Array_Table[i] == 0xfb) - rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50); - else if (Rtl819XRadioA_Array_Table[i] == 0xfa) - rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5); - else if (Rtl819XRadioA_Array_Table[i] == 0xf9) - rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1); - else - { - BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath]; - u32 NewOffset = 0; - u32 DataAndAddr = 0; - - NewOffset = Rtl819XRadioA_Array_Table[i] & 0x3f; - DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioA_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF - rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr); - } - } - rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0); - } - #else - for(i = 0;i<RadioA_ArrayLen; i=i+2) - { - if(Rtl819XRadioA_Array_Table[i] == 0xfe) { - #ifdef CONFIG_LONG_DELAY_ISSUE - rtw_msleep_os(50); - #else - rtw_mdelay_os(50); - #endif - } - else if (Rtl819XRadioA_Array_Table[i] == 0xfd) - rtw_mdelay_os(5); - else if (Rtl819XRadioA_Array_Table[i] == 0xfc) - rtw_mdelay_os(1); - else if (Rtl819XRadioA_Array_Table[i] == 0xfb) - rtw_udelay_os(50); - else if (Rtl819XRadioA_Array_Table[i] == 0xfa) - rtw_udelay_os(5); - else if (Rtl819XRadioA_Array_Table[i] == 0xf9) - rtw_udelay_os(1); - else - { - PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]); - // Add 1us delay between BB/RF register setting. - rtw_udelay_os(1); - } - } - #endif - //Add for High Power PA - PHY_ConfigRFExternalPA(Adapter, eRFPath); - break; - case RF_PATH_B: - #ifdef CONFIG_IOL_RF_RF_PATH_B - { - struct xmit_frame *xmit_frame; - if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) { - rtStatus = _FAIL; - goto exit; - } - - for(i = 0;i<RadioB_ArrayLen; i=i+2) - { - if(Rtl819XRadioB_Array_Table[i] == 0xfe) - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50); - else if (Rtl819XRadioB_Array_Table[i] == 0xfd) - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5); - else if (Rtl819XRadioB_Array_Table[i] == 0xfc) - rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1); - else if (Rtl819XRadioB_Array_Table[i] == 0xfb) - rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50); - else if (Rtl819XRadioB_Array_Table[i] == 0xfa) - rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5); - else if (Rtl819XRadioB_Array_Table[i] == 0xf9) - rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1); - else - { - BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath]; - u32 NewOffset = 0; - u32 DataAndAddr = 0; - - NewOffset = Rtl819XRadioB_Array_Table[i] & 0x3f; - DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioB_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF - rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr); - } - } - rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0); - } - #else - for(i = 0;i<RadioB_ArrayLen; i=i+2) - { - if(Rtl819XRadioB_Array_Table[i] == 0xfe) - { // Deay specific ms. Only RF configuration require delay. -#if 0//#ifdef CONFIG_USB_HCI - #ifdef CONFIG_LONG_DELAY_ISSUE - rtw_msleep_os(1000); - #else - rtw_mdelay_os(1000); - #endif -#else - #ifdef CONFIG_LONG_DELAY_ISSUE - rtw_msleep_os(50); - #else - rtw_mdelay_os(50); - #endif -#endif - } - else if (Rtl819XRadioB_Array_Table[i] == 0xfd) - rtw_mdelay_os(5); - else if (Rtl819XRadioB_Array_Table[i] == 0xfc) - rtw_mdelay_os(1); - else if (Rtl819XRadioB_Array_Table[i] == 0xfb) - rtw_udelay_os(50); - else if (Rtl819XRadioB_Array_Table[i] == 0xfa) - rtw_udelay_os(5); - else if (Rtl819XRadioB_Array_Table[i] == 0xf9) - rtw_udelay_os(1); - else - { - PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]); - // Add 1us delay between BB/RF register setting. - rtw_udelay_os(1); - } - } - #endif - break; - case RF_PATH_C: - break; - case RF_PATH_D: - break; - } - -exit: - return rtStatus; - -} -#endif - -/*----------------------------------------------------------------------------- - * Function: PHY_CheckBBAndRFOK() - * - * Overview: This function is write register and then readback to make sure whether - * BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok - * - * Input: PADAPTER Adapter - * HW90_BLOCK_E CheckBlock - * RF_RADIO_PATH_E eRFPath // it is used only when CheckBlock is HW90_BLOCK_RF - * - * Output: NONE - * - * Return: RT_STATUS_SUCCESS: PHY is OK - * - * Note: This function may be removed in the ASIC - *---------------------------------------------------------------------------*/ -int -PHY_CheckBBAndRFOK( - IN PADAPTER Adapter, - IN HW90_BLOCK_E CheckBlock, - IN RF_RADIO_PATH_E eRFPath - ) -{ - int rtStatus = _SUCCESS; - - u32 i, CheckTimes = 4,ulRegRead = 0; - - u32 WriteAddr[4]; - u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; - - // Initialize register address offset to be checked - WriteAddr[HW90_BLOCK_MAC] = 0x100; - WriteAddr[HW90_BLOCK_PHY0] = 0x900; - WriteAddr[HW90_BLOCK_PHY1] = 0x800; - WriteAddr[HW90_BLOCK_RF] = 0x3; - - for(i=0 ; i < CheckTimes ; i++) - { - - // - // Write Data to register and readback - // - switch(CheckBlock) - { - case HW90_BLOCK_MAC: - //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!")); - //RT_TRACE(COMP_INIT, DBG_LOUD, ("PHY_CheckBBRFOK(): Never Write 0x100 here!\n")); - break; - - case HW90_BLOCK_PHY0: - case HW90_BLOCK_PHY1: - rtw_write32(Adapter, WriteAddr[CheckBlock], WriteData[i]); - ulRegRead = rtw_read32(Adapter, WriteAddr[CheckBlock]); - break; - - case HW90_BLOCK_RF: - // When initialization, we want the delay function(delay_ms(), delay_us() - // ==> actually we call PlatformStallExecution()) to do NdisStallExecution() - // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK - // to run at Dispatch level to achive it. - //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK); - WriteData[i] &= 0xfff; - PHY_SetRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]); - // TODO: we should not delay for such a long time. Ask SD3 - rtw_mdelay_os(10); - ulRegRead = PHY_QueryRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); - rtw_mdelay_os(10); - //cosa PlatformReleaseSpinLock(Adapter, RT_INITIAL_SPINLOCK); - break; - - default: - rtStatus = _FAIL; - break; - } - - - // - // Check whether readback data is correct - // - if(ulRegRead != WriteData[i]) - { - //RT_TRACE(COMP_FPGA, DBG_LOUD, ("ulRegRead: %lx, WriteData: %lx \n", ulRegRead, WriteData[i])); - rtStatus = _FAIL; - break; - } - } - - return rtStatus; -} - - -VOID -rtl8192c_PHY_GetHWRegOriginalValue( - IN PADAPTER Adapter - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - // read rx initial gain - pHalData->DefaultInitialGain[0] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XAAGCCore1, bMaskByte0); - pHalData->DefaultInitialGain[1] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XBAGCCore1, bMaskByte0); - pHalData->DefaultInitialGain[2] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XCAGCCore1, bMaskByte0); - pHalData->DefaultInitialGain[3] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XDAGCCore1, bMaskByte0); - //RT_TRACE(COMP_INIT, DBG_LOUD, - //("Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", - //pHalData->DefaultInitialGain[0], pHalData->DefaultInitialGain[1], - //pHalData->DefaultInitialGain[2], pHalData->DefaultInitialGain[3])); - - // read framesync - pHalData->framesync = (u8)PHY_QueryBBReg(Adapter, rOFDM0_RxDetector3, bMaskByte0); - pHalData->framesyncC34 = PHY_QueryBBReg(Adapter, rOFDM0_RxDetector2, bMaskDWord); - //RT_TRACE(COMP_INIT, DBG_LOUD, ("Default framesync (0x%x) = 0x%x \n", - // rOFDM0_RxDetector3, pHalData->framesync)); -} - - -// -// Description: -// Map dBm into Tx power index according to -// current HW model, for example, RF and PA, and -// current wireless mode. -// By Bruce, 2008-01-29. -// -static u8 -phy_DbmToTxPwrIdx( - IN PADAPTER Adapter, - IN WIRELESS_MODE WirelessMode, - IN int PowerInDbm - ) -{ - u8 TxPwrIdx = 0; - int Offset = 0; - - - // - // Tested by MP, we found that CCK Index 0 equals to 8dbm, OFDM legacy equals to - // 3dbm, and OFDM HT equals to 0dbm repectively. - // Note: - // The mapping may be different by different NICs. Do not use this formula for what needs accurate result. - // By Bruce, 2008-01-29. - // - switch(WirelessMode) - { - case WIRELESS_MODE_B: - Offset = -7; - break; - - case WIRELESS_MODE_G: - case WIRELESS_MODE_N_24G: - Offset = -8; - break; - default: - Offset = -8; - break; - } - - if((PowerInDbm - Offset) > 0) - { - TxPwrIdx = (u8)((PowerInDbm - Offset) * 2); - } - else - { - TxPwrIdx = 0; - } - - // Tx Power Index is too large. - if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S) - TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S; - - return TxPwrIdx; -} - -// -// Description: -// Map Tx power index into dBm according to -// current HW model, for example, RF and PA, and -// current wireless mode. -// By Bruce, 2008-01-29. -// -int -phy_TxPwrIdxToDbm( - IN PADAPTER Adapter, - IN WIRELESS_MODE WirelessMode, - IN u8 TxPwrIdx - ) -{ - int Offset = 0; - int PwrOutDbm = 0; - - // - // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to -8dbm. - // Note: - // The mapping may be different by different NICs. Do not use this formula for what needs accurate result. - // By Bruce, 2008-01-29. - // - switch(WirelessMode) - { - case WIRELESS_MODE_B: - Offset = -7; - break; - - case WIRELESS_MODE_G: - case WIRELESS_MODE_N_24G: - Offset = -8; - default: - Offset = -8; - break; - } - - PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part. - - return PwrOutDbm; -} - - -/*----------------------------------------------------------------------------- - * Function: GetTxPowerLevel8190() - * - * Overview: This function is export to "common" moudule - * - * Input: PADAPTER Adapter - * psByte Power Level - * - * Output: NONE - * - * Return: NONE - * - *---------------------------------------------------------------------------*/ -VOID -PHY_GetTxPowerLevel8192C( - IN PADAPTER Adapter, - OUT u32* powerlevel - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 TxPwrLevel = 0; - int TxPwrDbm; - - // - // Because the Tx power indexes are different, we report the maximum of them to - // meet the CCX TPC request. By Bruce, 2008-01-31. - // - - // CCK - TxPwrLevel = pHalData->CurrentCckTxPwrIdx; - TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_B, TxPwrLevel); - - // Legacy OFDM - TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx + pHalData->LegacyHTTxPowerDiff; - - // Compare with Legacy OFDM Tx power. - if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm) - TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel); - - // HT OFDM - TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx; - - // Compare with HT OFDM Tx power. - if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm) - TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel); - - *powerlevel = TxPwrDbm; -} - - -static void getTxPowerIndex( - IN PADAPTER Adapter, - IN u8 channel, - IN OUT u8* cckPowerLevel, - IN OUT u8* ofdmPowerLevel - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 index = (channel -1); - // 1. CCK - cckPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelCck[RF_PATH_A][index]; //RF-A - cckPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelCck[RF_PATH_B][index]; //RF-B - - // 2. OFDM for 1S or 2S - if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R) - { - // Read HT 40 OFDM TX power - ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_1S[RF_PATH_A][index]; - ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_1S[RF_PATH_B][index]; - } - else if (GET_RF_TYPE(Adapter) == RF_2T2R) - { - // Read HT 40 OFDM TX power - ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_2S[RF_PATH_A][index]; - ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_2S[RF_PATH_B][index]; - } - //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel)); -} - -static void ccxPowerIndexCheck( - IN PADAPTER Adapter, - IN u8 channel, - IN OUT u8* cckPowerLevel, - IN OUT u8* ofdmPowerLevel - ) -{ -#if 0 - PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PRT_CCX_INFO pCcxInfo = GET_CCX_INFO(pMgntInfo); - - // - // CCX 2 S31, AP control of client transmit power: - // 1. We shall not exceed Cell Power Limit as possible as we can. - // 2. Tolerance is +/- 5dB. - // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit. - // - // TODO: - // 1. 802.11h power contraint - // - // 071011, by rcnjko. - // - if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE && - pMgntInfo->mAssoc && - pCcxInfo->bUpdateCcxPwr && - pCcxInfo->bWithCcxCellPwr && - channel == pMgntInfo->dot11CurrentChannelNumber) - { - u1Byte CckCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pCcxInfo->CcxCellPwr); - u1Byte LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pCcxInfo->CcxCellPwr); - u1Byte OfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pCcxInfo->CcxCellPwr); - - RT_TRACE(COMP_TXAGC, DBG_LOUD, - ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", - pCcxInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx)); - RT_TRACE(COMP_TXAGC, DBG_LOUD, - ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", - channel, cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0])); - - // CCK - if(cckPowerLevel[0] > CckCellPwrIdx) - cckPowerLevel[0] = CckCellPwrIdx; - // Legacy OFDM, HT OFDM - if(ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx) - { - if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0) - { - ofdmPowerLevel[0] = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff; - } - else - { - ofdmPowerLevel[0] = 0; - } - } - - RT_TRACE(COMP_TXAGC, DBG_LOUD, - ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n", - cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0])); - } - - pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0]; - pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0]; - - RT_TRACE(COMP_TXAGC, DBG_LOUD, - ("PHY_SetTxPowerLevel8192S(): CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n", - cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0])); -#endif -} -/*----------------------------------------------------------------------------- - * Function: SetTxPowerLevel8190() - * - * Overview: This function is export to "HalCommon" moudule - * We must consider RF path later!!!!!!! - * - * Input: PADAPTER Adapter - * u1Byte channel - * - * Output: NONE - * - * Return: NONE - * 2008/11/04 MHC We remove EEPROM_93C56. - * We need to move CCX relative code to independet file. - * 2009/01/21 MHC Support new EEPROM format from SD3 requirement. - * - *---------------------------------------------------------------------------*/ -VOID -PHY_SetTxPowerLevel8192C( - IN PADAPTER Adapter, - IN u8 channel - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 cckPowerLevel[2], ofdmPowerLevel[2]; // [0]:RF-A, [1]:RF-B -/* -#if(MP_DRIVER == 1) - if (Adapter->registrypriv.mp_mode == 1) - return; -#endif -*/ - if(pHalData->bTXPowerDataReadFromEEPORM == _FALSE) - return; - - getTxPowerIndex(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]); - //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n", - // channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1])); - - ccxPowerIndexCheck(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]); - - rtl8192c_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]); - rtl8192c_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel); - -#if 0 - switch(pHalData->rf_chip) - { - case RF_8225: - PHY_SetRF8225CckTxPower(Adapter, cckPowerLevel[0]); - PHY_SetRF8225OfdmTxPower(Adapter, ofdmPowerLevel[0]); - break; - - case RF_8256: - PHY_SetRF8256CCKTxPower(Adapter, cckPowerLevel[0]); - PHY_SetRF8256OFDMTxPower(Adapter, ofdmPowerLevel[0]); - break; - - case RF_6052: - PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]); - PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel); - break; - - case RF_8258: - break; - } -#endif - -} - - -// -// Description: -// Update transmit power level of all channel supported. -// -// TODO: -// A mode. -// By Bruce, 2008-02-04. -// -BOOLEAN -PHY_UpdateTxPowerDbm8192C( - IN PADAPTER Adapter, - IN int powerInDbm - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 idx; - u8 rf_path; - - // TODO: A mode Tx power. - u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, powerInDbm); - u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, powerInDbm); - - if(OfdmTxPwrIdx - pHalData->LegacyHTTxPowerDiff > 0) - OfdmTxPwrIdx -= pHalData->LegacyHTTxPowerDiff; - else - OfdmTxPwrIdx = 0; - - //RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx)); - - for(idx = 0; idx < 14; idx++) - { - for (rf_path = 0; rf_path < 2; rf_path++) - { - pHalData->TxPwrLevelCck[rf_path][idx] = CckTxPwrIdx; - pHalData->TxPwrLevelHT40_1S[rf_path][idx] = - pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx; - } - } - - //Adapter->HalFunc.SetTxPowerLevelHandler(Adapter, pHalData->CurrentChannel);//gtest:todo - - return _TRUE; -} - - -/* - Description: - When beacon interval is changed, the values of the - hw registers should be modified. - By tynli, 2008.10.24. - -*/ - - -void -rtl8192c_PHY_SetBeaconHwReg( - IN PADAPTER Adapter, - IN u16 BeaconInterval - ) -{ - -} - - -VOID -PHY_ScanOperationBackup8192C( - IN PADAPTER Adapter, - IN u8 Operation - ) -{ -#if 0 - IO_TYPE IoType; - - if(!Adapter->bDriverStopped) - { - switch(Operation) - { - case SCAN_OPT_BACKUP: - IoType = IO_CMD_PAUSE_DM_BY_SCAN; - rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType); - - break; - - case SCAN_OPT_RESTORE: - IoType = IO_CMD_RESUME_DM_BY_SCAN; - rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType); - break; - - default: - RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n")); - break; - } - } -#endif -} - -/*----------------------------------------------------------------------------- - * Function: PHY_SetBWModeCallback8192C() - * - * Overview: Timer callback function for SetSetBWMode - * - * Input: PRT_TIMER pTimer - * - * Output: NONE - * - * Return: NONE - * - * Note: (1) We do not take j mode into consideration now - * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run - * concurrently? - *---------------------------------------------------------------------------*/ -static VOID -_PHY_SetBWMode92C( - IN PADAPTER Adapter -) -{ -// PADAPTER Adapter = (PADAPTER)pTimer->Adapter; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 regBwOpMode; - u8 regRRSR_RSC; - - //return; - - // Added it for 20/40 mhz switch time evaluation by guangan 070531 - //u4Byte NowL, NowH; - //u8Byte BeginTime, EndTime; - - /*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C() Switch to %s bandwidth\n", \ - pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/ - - if(pHalData->rf_chip == RF_PSEUDO_11N) - { - //pHalData->SetBWModeInProgress= _FALSE; - return; - } - - // There is no 40MHz mode in RF_8225. - if(pHalData->rf_chip==RF_8225) - return; - - if(Adapter->bDriverStopped) - return; - - // Added it for 20/40 mhz switch time evaluation by guangan 070531 - //NowL = PlatformEFIORead4Byte(Adapter, TSFR); - //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4); - //BeginTime = ((u8Byte)NowH << 32) + NowL; - - //3// - //3//<1>Set MAC register - //3// - //Adapter->HalFunc.SetBWModeHandler(); - - regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE); - regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2); - //regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(pu1Byte)®BwOpMode); - - switch(pHalData->CurrentChannelBW) - { - case HT_CHANNEL_WIDTH_20: - regBwOpMode |= BW_OPMODE_20MHZ; - // 2007/02/07 Mark by Emily becasue we have not verify whether this register works - rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode); - break; - - case HT_CHANNEL_WIDTH_40: - regBwOpMode &= ~BW_OPMODE_20MHZ; - // 2007/02/07 Mark by Emily becasue we have not verify whether this register works - rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode); - - regRRSR_RSC = (regRRSR_RSC&0x90) |(pHalData->nCur40MhzPrimeSC<<5); - rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC); - break; - - default: - /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): - unknown Bandwidth: %#X\n",pHalData->CurrentChannelBW));*/ - break; - } - - //3// - //3//<2>Set PHY related register - //3// - switch(pHalData->CurrentChannelBW) - { - /* 20 MHz channel*/ - case HT_CHANNEL_WIDTH_20: - PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); - PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); - PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); - - break; - - - /* 40 MHz channel*/ - case HT_CHANNEL_WIDTH_40: - PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); - PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); - - // Set Control channel to upper or lower. These settings are required only for 40MHz - PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1)); - PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); - PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0); - - PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1); - - break; - - - - default: - /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): unknown Bandwidth: %#X\n"\ - ,pHalData->CurrentChannelBW));*/ - break; - - } - //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 - - // Added it for 20/40 mhz switch time evaluation by guangan 070531 - //NowL = PlatformEFIORead4Byte(Adapter, TSFR); - //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4); - //EndTime = ((u8Byte)NowH << 32) + NowL; - //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime))); - - //3<3>Set RF related register - switch(pHalData->rf_chip) - { - case RF_8225: - //PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); - break; - - case RF_8256: - // Please implement this function in Hal8190PciPhy8256.c - //PHY_SetRF8256Bandwidth(Adapter, pHalData->CurrentChannelBW); - break; - - case RF_8258: - // Please implement this function in Hal8190PciPhy8258.c - // PHY_SetRF8258Bandwidth(); - break; - - case RF_PSEUDO_11N: - // Do Nothing - break; - - case RF_6052: - rtl8192c_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW); - break; - - default: - //RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID)); - break; - } - - //pHalData->SetBWModeInProgress= FALSE; - - //RT_TRACE(COMP_SCAN, DBG_LOUD, ("<==PHY_SetBWModeCallback8192C() \n" )); -} - - - /*----------------------------------------------------------------------------- - * Function: SetBWMode8190Pci() - * - * Overview: This function is export to "HalCommon" moudule - * - * Input: PADAPTER Adapter - * HT_CHANNEL_WIDTH Bandwidth //20M or 40M - * - * Output: NONE - * - * Return: NONE - * - * Note: We do not take j mode into consideration now - *---------------------------------------------------------------------------*/ -VOID -PHY_SetBWMode8192C( - IN PADAPTER Adapter, - IN HT_CHANNEL_WIDTH Bandwidth, // 20M or 40M - IN unsigned char Offset // Upper, Lower, or Don't care -) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - HT_CHANNEL_WIDTH tmpBW= pHalData->CurrentChannelBW; - // Modified it for 20/40 mhz switch by guangan 070531 - //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; - - //return; - - //if(pHalData->SwChnlInProgress) -// if(pMgntInfo->bScanInProgress) -// { -// RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s Exit because bScanInProgress!\n", -// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")); -// return; -// } - -// if(pHalData->SetBWModeInProgress) -// { -// // Modified it for 20/40 mhz switch by guangan 070531 -// RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s cancel last timer because SetBWModeInProgress!\n", -// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")); -// PlatformCancelTimer(Adapter, &pHalData->SetBWModeTimer); -// //return; -// } - - //if(pHalData->SetBWModeInProgress) - // return; - - //pHalData->SetBWModeInProgress= TRUE; - - pHalData->CurrentChannelBW = Bandwidth; - -#if 0 - if(Offset==HT_EXTCHNL_OFFSET_LOWER) - pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; - else if(Offset==HT_EXTCHNL_OFFSET_UPPER) - pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; - else - pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; -#else - pHalData->nCur40MhzPrimeSC = Offset; -#endif - - if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) - { - - #if 0 - //PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0); - #else - _PHY_SetBWMode92C(Adapter); - #endif - - } - else - { - //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n")); - //pHalData->SetBWModeInProgress= FALSE; - pHalData->CurrentChannelBW = tmpBW; - } - -} - - -static void _PHY_SwChnl8192C(PADAPTER Adapter, u8 channel) -{ - u8 eRFPath; - u32 param1, param2; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - if ( Adapter->bNotifyChannelChange ) - { - DBG_871X( "[%s] ch = %d\n", __FUNCTION__, channel ); - } - - //s1. pre common command - CmdID_SetTxPowerLevel - PHY_SetTxPowerLevel8192C(Adapter, channel); - - //s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel - param1 = RF_CHNLBW; - param2 = channel; - for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) - { - pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2); - PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]); - } - - - //s3. post common command - CmdID_End, None - -} - -VOID -PHY_SwChnl8192C( // Call after initialization - IN PADAPTER Adapter, - IN u8 channel - ) -{ - //PADAPTER Adapter = ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, _TRUE); - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u8 tmpchannel = pHalData->CurrentChannel; - BOOLEAN bResult = _TRUE; - - if(pHalData->rf_chip == RF_PSEUDO_11N) - { - //pHalData->SwChnlInProgress=FALSE; - return; //return immediately if it is peudo-phy - } - - //if(pHalData->SwChnlInProgress) - // return; - - //if(pHalData->SetBWModeInProgress) - // return; - - //-------------------------------------------- - switch(pHalData->CurrentWirelessMode) - { - case WIRELESS_MODE_A: - case WIRELESS_MODE_N_5G: - //RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14")); - break; - - case WIRELESS_MODE_B: - //RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14")); - break; - - case WIRELESS_MODE_G: - case WIRELESS_MODE_N_24G: - //RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14")); - break; - - default: - //RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode)); - break; - } - //-------------------------------------------- - - //pHalData->SwChnlInProgress = TRUE; - if(channel == 0) - channel = 1; - - pHalData->CurrentChannel=channel; - - //pHalData->SwChnlStage=0; - //pHalData->SwChnlStep=0; - - if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) - { - - #if 0 - //PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0); - #else - _PHY_SwChnl8192C(Adapter, channel); - #endif - - if(bResult) - { - //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n")); - } - else - { - //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n")); - //if(IS_HARDWARE_TYPE_8192SU(Adapter)) - //{ - // pHalData->SwChnlInProgress = FALSE; - pHalData->CurrentChannel = tmpchannel; - //} - } - - } - else - { - //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n")); - //if(IS_HARDWARE_TYPE_8192SU(Adapter)) - //{ - // pHalData->SwChnlInProgress = FALSE; - pHalData->CurrentChannel = tmpchannel; - //} - } -} - - -static BOOLEAN -phy_SwChnlStepByStep( - IN PADAPTER Adapter, - IN u8 channel, - IN u8 *stage, - IN u8 *step, - OUT u32 *delay - ) -{ -#if 0 - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - PCHANNEL_ACCESS_SETTING pChnlAccessSetting; - SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; - u4Byte PreCommonCmdCnt; - SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; - u4Byte PostCommonCmdCnt; - SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; - u4Byte RfDependCmdCnt; - SwChnlCmd *CurrentCmd; - u1Byte eRFPath; - u4Byte RfTXPowerCtrl; - BOOLEAN bAdjRfTXPowerCtrl = _FALSE; - - - RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n")); -#if(MP_DRIVER != 1) - RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel)); -#endif - RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n")); - - pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting; - RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n")); - - //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) - //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) - //{ - // <1> Fill up pre common command. - PreCommonCmdCnt = 0; - phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, - CmdID_SetTxPowerLevel, 0, 0, 0); - phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, - CmdID_End, 0, 0, 0); - - // <2> Fill up post common command. - PostCommonCmdCnt = 0; - - phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, - CmdID_End, 0, 0, 0); - - // <3> Fill up RF dependent command. - RfDependCmdCnt = 0; - switch( pHalData->RFChipID ) - { - case RF_8225: - RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); - // 2008/09/04 MH Change channel. - if(channel==14) channel++; - phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10); - phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_End, 0, 0, 0); - break; - - case RF_8256: - // TEST!! This is not the table for 8256!! - RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); - phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_RF_WriteReg, rRfChannel, channel, 10); - phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_End, 0, 0, 0); - break; - - case RF_6052: - RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); - phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_RF_WriteReg, RF_CHNLBW, channel, 10); - phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, - CmdID_End, 0, 0, 0); - - break; - - case RF_8258: - break; - - // For FPGA two MAC verification - case RF_PSEUDO_11N: - return TRUE; - default: - RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID)); - return FALSE; - break; - } - - - do{ - switch(*stage) - { - case 0: - CurrentCmd=&PreCommonCmd[*step]; - break; - case 1: - CurrentCmd=&RfDependCmd[*step]; - break; - case 2: - CurrentCmd=&PostCommonCmd[*step]; - break; - } - - if(CurrentCmd->CmdID==CmdID_End) - { - if((*stage)==2) - { - return TRUE; - } - else - { - (*stage)++; - (*step)=0; - continue; - } - } - - switch(CurrentCmd->CmdID) - { - case CmdID_SetTxPowerLevel: - PHY_SetTxPowerLevel8192C(Adapter,channel); - break; - case CmdID_WritePortUlong: - PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2); - break; - case CmdID_WritePortUshort: - PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2); - break; - case CmdID_WritePortUchar: - PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2); - break; - case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!! - for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) - { -#if 1 - pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2); - PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]); -#else - PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2)); -#endif - } - break; - } - - break; - }while(TRUE); - //cosa }/*for(Number of RF paths)*/ - - (*delay)=CurrentCmd->msDelay; - (*step)++; - return FALSE; -#endif - return _TRUE; -} - - -static BOOLEAN -phy_SetSwChnlCmdArray( - SwChnlCmd* CmdTable, - u32 CmdTableIdx, - u32 CmdTableSz, - SwChnlCmdID CmdID, - u32 Para1, - u32 Para2, - u32 msDelay - ) -{ - SwChnlCmd* pCmd; - - if(CmdTable == NULL) - { - //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n")); - return _FALSE; - } - if(CmdTableIdx >= CmdTableSz) - { - //RT_ASSERT(FALSE, - // ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n", - // CmdTableIdx, CmdTableSz)); - return _FALSE; - } - - pCmd = CmdTable + CmdTableIdx; - pCmd->CmdID = CmdID; - pCmd->Para1 = Para1; - pCmd->Para2 = Para2; - pCmd->msDelay = msDelay; - - return _TRUE; -} - - -static void -phy_FinishSwChnlNow( // We should not call this function directly - IN PADAPTER Adapter, - IN u8 channel - ) -{ -#if 0 - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u32 delay; - - while(!phy_SwChnlStepByStep(Adapter,channel,&pHalData->SwChnlStage,&pHalData->SwChnlStep,&delay)) - { - if(delay>0) - rtw_mdelay_os(delay); - } -#endif -} - - - -// -// Description: -// Switch channel synchronously. Called by SwChnlByDelayHandler. -// -// Implemented by Bruce, 2008-02-14. -// The following procedure is operted according to SwChanlCallback8190Pci(). -// However, this procedure is performed synchronously which should be running under -// passive level. -// -VOID -PHY_SwChnlPhy8192C( // Only called during initialize - IN PADAPTER Adapter, - IN u8 channel - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - //RT_TRACE(COMP_SCAN | COMP_RM, DBG_LOUD, ("==>PHY_SwChnlPhy8192S(), switch from channel %d to channel %d.\n", pHalData->CurrentChannel, channel)); - - // Cannot IO. - //if(RT_CANNOT_IO(Adapter)) - // return; - - // Channel Switching is in progress. - //if(pHalData->SwChnlInProgress) - // return; - - //return immediately if it is peudo-phy - if(pHalData->rf_chip == RF_PSEUDO_11N) - { - //pHalData->SwChnlInProgress=FALSE; - return; - } - - //pHalData->SwChnlInProgress = TRUE; - if( channel == 0) - channel = 1; - - pHalData->CurrentChannel=channel; - - //pHalData->SwChnlStage = 0; - //pHalData->SwChnlStep = 0; - - phy_FinishSwChnlNow(Adapter,channel); - - //pHalData->SwChnlInProgress = FALSE; -} - - -// -// Description: -// Configure H/W functionality to enable/disable Monitor mode. -// Note, because we possibly need to configure BB and RF in this function, -// so caller should in PASSIVE_LEVEL. 080118, by rcnjko. -// -VOID -PHY_SetMonitorMode8192C( - IN PADAPTER pAdapter, - IN BOOLEAN bEnableMonitorMode - ) -{ -#if 0 - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - BOOLEAN bFilterOutNonAssociatedBSSID = FALSE; - - //2 Note: we may need to stop antenna diversity. - if(bEnableMonitorMode) - { - bFilterOutNonAssociatedBSSID = FALSE; - RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n")); - - pHalData->bInMonitorMode = TRUE; - pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE); - rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID); - } - else - { - bFilterOutNonAssociatedBSSID = TRUE; - RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n")); - - pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE); - pHalData->bInMonitorMode = FALSE; - rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID); - } -#endif -} - - -/*----------------------------------------------------------------------------- - * Function: PHYCheckIsLegalRfPath8190Pci() - * - * Overview: Check different RF type to execute legal judgement. If RF Path is illegal - * We will return false. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 11/15/2007 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -BOOLEAN -PHY_CheckIsLegalRfPath8192C( - IN PADAPTER pAdapter, - IN u32 eRFPath) -{ -// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - BOOLEAN rtValue = _TRUE; - - // NOt check RF Path now.! -#if 0 - if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A) - { - rtValue = FALSE; - } - if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A) - { - - } -#endif - return rtValue; - -} /* PHY_CheckIsLegalRfPath8192C */ - -static VOID _PHY_SetRFPathSwitch( - IN PADAPTER pAdapter, - IN BOOLEAN bMain, - IN BOOLEAN is2T - ) -{ - u8 u1bTmp; - - if(!pAdapter->hw_init_completed) - { - u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7; - rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp); - //PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - - if(is2T) - { - if(bMain) - PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A - else - PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT - } - else - { - - if(bMain) - PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2); //Main - else - PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1); //Aux - } - -} - -//return value TRUE => Main; FALSE => Aux - -static BOOLEAN _PHY_QueryRFPathSwitch( - IN PADAPTER pAdapter, - IN BOOLEAN is2T - ) -{ -// if(is2T) -// return _TRUE; - - if(!pAdapter->hw_init_completed) - { - PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01); - PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); - } - - if(is2T) - { - if(PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) - return _TRUE; - else - return _FALSE; - } - else - { - if(PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02) - return _TRUE; - else - return _FALSE; - } -} - - -static VOID -_PHY_DumpRFReg(IN PADAPTER pAdapter) -{ - u32 rfRegValue,rfRegOffset; - - //RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n")); - - for(rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){ - rfRegValue = PHY_QueryRFReg(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord); - //RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue)); - } - //RTPRINT(FINIT, INIT_RF, ("<===== PHY_DumpRFReg()\n")); -} - - -VOID rtl8192c_PHY_SetRFPathSwitch( - IN PADAPTER pAdapter, - IN BOOLEAN bMain - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); - -#if DISABLE_BB_RF - return; -#endif - - if(IS_92C_SERIAL( pHalData->VersionID)){ - _PHY_SetRFPathSwitch(pAdapter, bMain, _TRUE); - } - else{ - // For 88C 1T1R - _PHY_SetRFPathSwitch(pAdapter, bMain, _FALSE); - } -} - -// -// Move from phycfg.c to gen.c to be code independent later -// -//-------------------------Move to other DIR later----------------------------*/ -#ifdef CONFIG_USB_HCI - -// -// Description: -// To dump all Tx FIFO LLT related link-list table. -// Added by Roger, 2009.03.10. -// -VOID -DumpBBDbgPort_92CU( - IN PADAPTER Adapter - ) -{ - - //RT_TRACE(COMP_SEND, DBG_WARNING, ("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n")); - //RT_TRACE(COMP_SEND, DBG_WARNING, ("BaseBand Debug Ports:\n")); - - PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0000); - //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); - - PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0803); - //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); - - PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0a06); - //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); - - PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0007); - //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); - - PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100); - PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x000f0000); - //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); - - PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100); - PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x00150000); - //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); - - //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x800, PHY_QueryBBReg(Adapter, 0x0800, bMaskDWord))); - //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x900, PHY_QueryBBReg(Adapter, 0x0900, bMaskDWord))); - //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa00, PHY_QueryBBReg(Adapter, 0x0a00, bMaskDWord))); - //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa54, PHY_QueryBBReg(Adapter, 0x0a54, bMaskDWord))); - //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa58, PHY_QueryBBReg(Adapter, 0x0a58, bMaskDWord))); - -} -#endif - +/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8723A_PHYCFG_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtw_byteorder.h>
+
+#ifdef CONFIG_IOL
+#include <rtw_iol.h>
+#endif
+
+#include <rtl8723a_hal.h>
+
+
+/*---------------------------Define Local Constant---------------------------*/
+/* Channel switch:The size of command tables for switch channel*/
+#define MAX_PRECMD_CNT 16
+#define MAX_RFDEPENDCMD_CNT 16
+#define MAX_POSTCMD_CNT 16
+
+#define MAX_DOZE_WAITING_TIMES_9x 64
+
+/*---------------------------Define Local Constant---------------------------*/
+
+
+/*------------------------Define global variable-----------------------------*/
+
+/*------------------------Define local variable------------------------------*/
+
+
+/*--------------------Define export function prototype-----------------------*/
+// Please refer to header file
+/*--------------------Define export function prototype-----------------------*/
+
+/*----------------------------Function Body----------------------------------*/
+//
+// 1. BB register R/W API
+//
+
+/**
+* Function: phy_CalculateBitShift
+*
+* OverView: Get shifted position of the BitMask
+*
+* Input:
+* u4Byte BitMask,
+*
+* Output: none
+* Return: u4Byte Return the shift bit bit position of the mask
+*/
+static u32
+phy_CalculateBitShift(
+ u32 BitMask
+ )
+{
+ u32 i;
+
+ for(i=0; i<=31; i++)
+ {
+ if ( ((BitMask>>i) & 0x1 ) == 1)
+ break;
+ }
+
+ return (i);
+}
+
+
+/**
+* Function: PHY_QueryBBReg
+*
+* OverView: Read "sepcific bits" from BB register
+*
+* Input:
+* PADAPTER Adapter,
+* u4Byte RegAddr, //The target address to be readback
+* u4Byte BitMask //The target bit position in the target address
+* //to be readback
+* Output: None
+* Return: u4Byte Data //The readback register value
+* Note: This function is equal to "GetRegSetting" in PHY programming guide
+*/
+u32
+rtl8192c_PHY_QueryBBReg(
+ IN PADAPTER Adapter,
+ IN u32 RegAddr,
+ IN u32 BitMask
+ )
+{
+ u32 ReturnValue = 0, OriginalValue, BitShift;
+ u16 BBWaitCounter = 0;
+
+#if (DISABLE_BB_RF == 1)
+ return 0;
+#endif
+
+ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask));
+
+ OriginalValue = rtw_read32(Adapter, RegAddr);
+ BitShift = phy_CalculateBitShift(BitMask);
+ ReturnValue = (OriginalValue & BitMask) >> BitShift;
+
+ //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, OriginalValue));
+ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx), OriginalValue(%#lx)\n", RegAddr, BitMask, OriginalValue));
+
+ return (ReturnValue);
+
+}
+
+
+/**
+* Function: PHY_SetBBReg
+*
+* OverView: Write "Specific bits" to BB register (page 8~)
+*
+* Input:
+* PADAPTER Adapter,
+* u4Byte RegAddr, //The target address to be modified
+* u4Byte BitMask //The target bit position in the target address
+* //to be modified
+* u4Byte Data //The new register value in the target bit position
+* //of the target address
+*
+* Output: None
+* Return: None
+* Note: This function is equal to "PutRegSetting" in PHY programming guide
+*/
+
+VOID
+rtl8192c_PHY_SetBBReg(
+ IN PADAPTER Adapter,
+ IN u32 RegAddr,
+ IN u32 BitMask,
+ IN u32 Data
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ //u16 BBWaitCounter = 0;
+ u32 OriginalValue, BitShift;
+
+#if (DISABLE_BB_RF == 1)
+ return;
+#endif
+
+ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));
+
+ if(BitMask!= bMaskDWord){//if not "double word" write
+ OriginalValue = rtw_read32(Adapter, RegAddr);
+ BitShift = phy_CalculateBitShift(BitMask);
+ Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
+ }
+
+ rtw_write32(Adapter, RegAddr, Data);
+
+ //RTPRINT(FPHY, PHY_BBW, ("BBW MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, Data));
+ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));
+
+}
+
+
+//
+// 2. RF register R/W API
+//
+
+/*-----------------------------------------------------------------------------
+ * Function: phy_FwRFSerialRead()
+ *
+ * Overview: We support firmware to execute RF-R/W.
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 01/21/2008 MHC Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+static u32
+phy_FwRFSerialRead(
+ IN PADAPTER Adapter,
+ IN RF_RADIO_PATH_E eRFPath,
+ IN u32 Offset )
+{
+ u32 retValue = 0;
+ //RT_ASSERT(FALSE,("deprecate!\n"));
+ return (retValue);
+
+} /* phy_FwRFSerialRead */
+
+
+/*-----------------------------------------------------------------------------
+ * Function: phy_FwRFSerialWrite()
+ *
+ * Overview: We support firmware to execute RF-R/W.
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 01/21/2008 MHC Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+static VOID
+phy_FwRFSerialWrite(
+ IN PADAPTER Adapter,
+ IN RF_RADIO_PATH_E eRFPath,
+ IN u32 Offset,
+ IN u32 Data )
+{
+ //RT_ASSERT(FALSE,("deprecate!\n"));
+}
+
+
+/**
+* Function: phy_RFSerialRead
+*
+* OverView: Read regster from RF chips
+*
+* Input:
+* PADAPTER Adapter,
+* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
+* u4Byte Offset, //The target address to be read
+*
+* Output: None
+* Return: u4Byte reback value
+* Note: Threre are three types of serial operations:
+* 1. Software serial write
+* 2. Hardware LSSI-Low Speed Serial Interface
+* 3. Hardware HSSI-High speed
+* serial write. Driver need to implement (1) and (2).
+* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
+*/
+static u32
+phy_RFSerialRead(
+ IN PADAPTER Adapter,
+ IN RF_RADIO_PATH_E eRFPath,
+ IN u32 Offset
+ )
+{
+ u32 retValue = 0;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
+ u32 NewOffset;
+ u32 tmplong,tmplong2;
+ u8 RfPiEnable=0;
+#if 0
+ if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
+ return retValue;
+ if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
+ return retValue;
+#endif
+ //
+ // Make sure RF register offset is correct
+ //
+ Offset &= 0x3f;
+
+ //
+ // Switch page for 8256 RF IC
+ //
+ NewOffset = Offset;
+
+ // 2009/06/17 MH We can not execute IO for power save or other accident mode.
+ //if(RT_CANNOT_IO(Adapter))
+ //{
+ // RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n"));
+ // return 0xFFFFFFFF;
+ //}
+
+ // For 92S LSSI Read RFLSSIRead
+ // For RF A/B write 0x824/82c(does not work in the future)
+ // We must use 0x824 for RF A and B to execute read trigger
+ tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);
+ if(eRFPath == RF_PATH_A)
+ tmplong2 = tmplong;
+ else
+ tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord);
+
+ tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; //T65 RF
+
+ PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
+ rtw_udelay_os(10);// PlatformStallExecution(10);
+
+ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
+ rtw_udelay_os(100);//PlatformStallExecution(100);
+
+ PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
+ rtw_udelay_os(10);//PlatformStallExecution(10);
+
+ if(eRFPath == RF_PATH_A)
+ RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);
+ else if(eRFPath == RF_PATH_B)
+ RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);
+
+ if(RfPiEnable)
+ { // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF
+ retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
+ //DBG_8192C("Readback from RF-PI : 0x%x\n", retValue);
+ }
+ else
+ { //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF
+ retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
+ //DBG_8192C("Readback from RF-SI : 0x%x\n", retValue);
+ }
+ //DBG_8192C("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue);
+
+ return retValue;
+
+}
+
+
+
+/**
+* Function: phy_RFSerialWrite
+*
+* OverView: Write data to RF register (page 8~)
+*
+* Input:
+* PADAPTER Adapter,
+* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
+* u4Byte Offset, //The target address to be read
+* u4Byte Data //The new register Data in the target bit position
+* //of the target to be read
+*
+* Output: None
+* Return: None
+* Note: Threre are three types of serial operations:
+* 1. Software serial write
+* 2. Hardware LSSI-Low Speed Serial Interface
+* 3. Hardware HSSI-High speed
+* serial write. Driver need to implement (1) and (2).
+* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
+ *
+ * Note: For RF8256 only
+ * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
+ * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
+ * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
+ * programming guide" for more details.
+ * Thus, we define a sub-finction for RTL8526 register address conversion
+ * ===========================================================
+ * Register Mode RegCTL[1] RegCTL[0] Note
+ * (Reg00[12]) (Reg00[10])
+ * ===========================================================
+ * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
+ * ------------------------------------------------------------------
+ * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
+ * ------------------------------------------------------------------
+ * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
+ * ------------------------------------------------------------------
+ *
+ * 2008/09/02 MH Add 92S RF definition
+ *
+ *
+ *
+*/
+static VOID
+phy_RFSerialWrite(
+ IN PADAPTER Adapter,
+ IN RF_RADIO_PATH_E eRFPath,
+ IN u32 Offset,
+ IN u32 Data
+ )
+{
+ u32 DataAndAddr = 0;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
+ u32 NewOffset;
+
+#if 0
+ //<Roger_TODO> We should check valid regs for RF_6052 case.
+ if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
+ return;
+ if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
+ return;
+#endif
+
+ // 2009/06/17 MH We can not execute IO for power save or other accident mode.
+ //if(RT_CANNOT_IO(Adapter))
+ //{
+ // RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n"));
+ // return;
+ //}
+
+ Offset &= 0x3f;
+
+ //
+ // Shadow Update
+ //
+ //PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data);
+
+ //
+ // Switch page for 8256 RF IC
+ //
+ NewOffset = Offset;
+
+ //
+ // Put write addr in [5:0] and write data in [31:16]
+ //
+ //DataAndAddr = (Data<<16) | (NewOffset&0x3f);
+ DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF
+
+ //
+ // Write Operation
+ //
+ PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
+ //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
+
+}
+
+
+/**
+* Function: PHY_QueryRFReg
+*
+* OverView: Query "Specific bits" to RF register (page 8~)
+*
+* Input:
+* PADAPTER Adapter,
+* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
+* u4Byte RegAddr, //The target address to be read
+* u4Byte BitMask //The target bit position in the target address
+* //to be read
+*
+* Output: None
+* Return: u4Byte Readback value
+* Note: This function is equal to "GetRFRegSetting" in PHY programming guide
+*/
+u32
+rtl8192c_PHY_QueryRFReg(
+ IN PADAPTER Adapter,
+ IN RF_RADIO_PATH_E eRFPath,
+ IN u32 RegAddr,
+ IN u32 BitMask
+ )
+{
+ u32 Original_Value, Readback_Value, BitShift;
+ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ //u8 RFWaitCounter = 0;
+ //_irqL irqL;
+
+#if (DISABLE_BB_RF == 1)
+ return 0;
+#endif
+
+ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), BitMask(%#lx)\n", RegAddr, eRFPath,BitMask));
+
+#ifdef CONFIG_USB_HCI
+ //PlatformAcquireMutex(&pHalData->mxRFOperate);
+#else
+ //_enter_critical(&pHalData->rf_lock, &irqL);
+#endif
+
+
+ Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
+
+ BitShift = phy_CalculateBitShift(BitMask);
+ Readback_Value = (Original_Value & BitMask) >> BitShift;
+
+#ifdef CONFIG_USB_HCI
+ //PlatformReleaseMutex(&pHalData->mxRFOperate);
+#else
+ //_exit_critical(&pHalData->rf_lock, &irqL);
+#endif
+
+
+ //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%lx Addr[0x%lx]=0x%lx\n", eRFPath, BitMask, RegAddr, Original_Value));//BitMask(%#lx),BitMask,
+ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), Original_Value(%#lx)\n",
+ // RegAddr, eRFPath, Original_Value));
+
+ return (Readback_Value);
+}
+
+/**
+* Function: PHY_SetRFReg
+*
+* OverView: Write "Specific bits" to RF register (page 8~)
+*
+* Input:
+* PADAPTER Adapter,
+* RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
+* u4Byte RegAddr, //The target address to be modified
+* u4Byte BitMask //The target bit position in the target address
+* //to be modified
+* u4Byte Data //The new register Data in the target bit position
+* //of the target address
+*
+* Output: None
+* Return: None
+* Note: This function is equal to "PutRFRegSetting" in PHY programming guide
+*/
+VOID
+rtl8192c_PHY_SetRFReg(
+ IN PADAPTER Adapter,
+ IN RF_RADIO_PATH_E eRFPath,
+ IN u32 RegAddr,
+ IN u32 BitMask,
+ IN u32 Data
+ )
+{
+
+ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ //u1Byte RFWaitCounter = 0;
+ u32 Original_Value, BitShift;
+ //_irqL irqL;
+
+#if (DISABLE_BB_RF == 1)
+ return;
+#endif
+
+ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
+ // RegAddr, BitMask, Data, eRFPath));
+ //RTPRINT(FINIT, INIT_RF, ("PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
+ // RegAddr, BitMask, Data, eRFPath));
+
+
+#ifdef CONFIG_USB_HCI
+ //PlatformAcquireMutex(&pHalData->mxRFOperate);
+#else
+ //_enter_critical(&pHalData->rf_lock, &irqL);
+#endif
+
+
+ // RF data is 12 bits only
+ if (BitMask != bRFRegOffsetMask)
+ {
+ Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
+ BitShift = phy_CalculateBitShift(BitMask);
+ Data = ((Original_Value & (~BitMask)) | (Data<< BitShift));
+ }
+
+ phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);
+
+
+#ifdef CONFIG_USB_HCI
+ //PlatformReleaseMutex(&pHalData->mxRFOperate);
+#else
+ //_exit_critical(&pHalData->rf_lock, &irqL);
+#endif
+
+ //PHY_QueryRFReg(Adapter,eRFPath,RegAddr,BitMask);
+ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
+ // RegAddr, BitMask, Data, eRFPath));
+
+}
+
+
+//
+// 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
+//
+
+/*-----------------------------------------------------------------------------
+ * Function: phy_ConfigMACWithParaFile()
+ *
+ * Overview: This function read BB parameters from general file format, and do register
+ * Read/Write
+ *
+ * Input: PADAPTER Adapter
+ * ps1Byte pFileName
+ *
+ * Output: NONE
+ *
+ * Return: RT_STATUS_SUCCESS: configuration file exist
+ *
+ * Note: The format of MACPHY_REG.txt is different from PHY and RF.
+ * [Register][Mask][Value]
+ *---------------------------------------------------------------------------*/
+static int
+phy_ConfigMACWithParaFile(
+ IN PADAPTER Adapter,
+ IN u8* pFileName
+)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ int rtStatus = _SUCCESS;
+
+ return rtStatus;
+}
+
+/*-----------------------------------------------------------------------------
+ * Function: phy_ConfigMACWithHeaderFile()
+ *
+ * Overview: This function read BB parameters from Header file we gen, and do register
+ * Read/Write
+ *
+ * Input: PADAPTER Adapter
+ * ps1Byte pFileName
+ *
+ * Output: NONE
+ *
+ * Return: RT_STATUS_SUCCESS: configuration file exist
+ *
+ * Note: The format of MACPHY_REG.txt is different from PHY and RF.
+ * [Register][Mask][Value]
+ *---------------------------------------------------------------------------*/
+#ifndef CONFIG_PHY_SETTING_WITH_ODM
+static int
+phy_ConfigMACWithHeaderFile(
+ IN PADAPTER Adapter
+)
+{
+ u32 i = 0;
+ u32 ArrayLength = 0;
+ u32* ptrArray;
+ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ //2008.11.06 Modified by tynli.
+ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read Rtl819XMACPHY_Array\n"));
+ ArrayLength = Rtl8723_MAC_ArrayLength;
+ ptrArray = (u32*)Rtl8723_MAC_Array;
+
+#ifdef CONFIG_IOL_MAC
+ {
+ struct xmit_frame *xmit_frame;
+ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)
+ return _FAIL;
+
+ for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
+ rtw_IOL_append_WB_cmd(xmit_frame, ptrArray[i], (u8)ptrArray[i+1]);
+ }
+
+ return rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);
+ }
+#else
+ for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
+ rtw_write8(Adapter, ptrArray[i], (u8)ptrArray[i+1]);
+ }
+#endif
+
+ return _SUCCESS;
+
+}
+#endif//#ifndef CONFIG_PHY_SETTING_WITH_ODM
+
+/*-----------------------------------------------------------------------------
+ * Function: PHY_MACConfig8192C
+ *
+ * Overview: Condig MAC by header file or parameter file.
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 08/12/2008 MHC Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+s32 PHY_MACConfig8723A(PADAPTER Adapter)
+{
+ int rtStatus = _SUCCESS;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ s8 *pszMACRegFile;
+ s8 sz8723MACRegFile[] = RTL8723_PHY_MACREG;
+ BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID);
+
+
+ pszMACRegFile = sz8723MACRegFile;
+
+ //
+ // Config MAC
+ //
+#ifdef CONFIG_EMBEDDED_FWIMG
+ #ifdef CONFIG_PHY_SETTING_WITH_ODM
+ if(HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv))
+ rtStatus = _FAIL;
+ #else
+ rtStatus = phy_ConfigMACWithHeaderFile(Adapter);
+ #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM
+#else
+
+ // Not make sure EEPROM, add later
+ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read MACREG.txt\n"));
+ rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile);
+#endif//CONFIG_EMBEDDED_FWIMG
+
+#ifdef CONFIG_PCI_HCI
+ //this switching setting cause some 8192cu hw have redownload fw fail issue
+ //improve 2-stream TX EVM by Jenyu
+ if(is92C)
+ rtw_write8(Adapter, REG_SPS0_CTRL+3,0x71);
+#endif
+
+
+ // 2010.07.13 AMPDU aggregation number 9
+ //rtw_write8(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM);
+ rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0A); //By tynli. 2010.11.18.
+#ifdef CONFIG_USB_HCI
+ if(is92C && (BOARD_USB_DONGLE == pHalData->BoardType))
+ rtw_write8(Adapter, 0x40,0x04);
+#endif
+
+ return rtStatus;
+
+}
+
+
+/**
+* Function: phy_InitBBRFRegisterDefinition
+*
+* OverView: Initialize Register definition offset for Radio Path A/B/C/D
+*
+* Input:
+* PADAPTER Adapter,
+*
+* Output: None
+* Return: None
+* Note: The initialization value is constant and it should never be changes
+*/
+static VOID
+phy_InitBBRFRegisterDefinition(
+ IN PADAPTER Adapter
+)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ // RF Interface Sowrtware Control
+ pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
+ pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
+ pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
+ pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
+
+ // RF Interface Readback Value
+ pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
+ pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
+ pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
+ pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
+
+ // RF Interface Output (and Enable)
+ pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
+ pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
+
+ // RF Interface (Output and) Enable
+ pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
+ pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
+
+ //Addr of LSSI. Wirte RF register by driver
+ pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
+ pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
+
+ // RF parameter
+ pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
+ pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
+ pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
+ pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
+
+ // Tx AGC Gain Stage (same for all path. Should we remove this?)
+ pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
+ pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
+ pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
+ pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
+
+ // Tranceiver A~D HSSI Parameter-1
+ pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
+ pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
+
+ // Tranceiver A~D HSSI Parameter-2
+ pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
+ pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
+
+ // RF switch Control
+ pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
+ pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
+ pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
+ pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
+
+ // AGC control 1
+ pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
+ pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
+ pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
+ pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
+
+ // AGC control 2
+ pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
+ pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
+ pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
+ pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
+
+ // RX AFE control 1
+ pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
+ pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
+ pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
+ pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
+
+ // RX AFE control 1
+ pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
+ pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
+ pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
+ pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
+
+ // Tx AFE control 1
+ pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
+ pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
+ pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
+ pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
+
+ // Tx AFE control 2
+ pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
+ pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
+ pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
+ pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
+
+ // Tranceiver LSSI Readback SI mode
+ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
+ pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
+ pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
+ pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
+
+ // Tranceiver LSSI Readback PI mode
+ pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
+ pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
+ //pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
+ //pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
+
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Function: phy_ConfigBBWithParaFile()
+ *
+ * Overview: This function read BB parameters from general file format, and do register
+ * Read/Write
+ *
+ * Input: PADAPTER Adapter
+ * ps1Byte pFileName
+ *
+ * Output: NONE
+ *
+ * Return: RT_STATUS_SUCCESS: configuration file exist
+ * 2008/11/06 MH For 92S we do not support silent reset now. Disable
+ * parameter file compare!!!!!!??
+ *
+ *---------------------------------------------------------------------------*/
+static int
+phy_ConfigBBWithParaFile(
+ IN PADAPTER Adapter,
+ IN u8* pFileName
+)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ int rtStatus = _SUCCESS;
+
+ return rtStatus;
+}
+
+
+
+//****************************************
+// The following is for High Power PA
+//****************************************
+VOID
+phy_ConfigBBExternalPA(
+ IN PADAPTER Adapter
+)
+{
+#ifdef CONFIG_USB_HCI
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u16 i=0;
+ u32 temp=0;
+
+ if(!pHalData->ExternalPA)
+ {
+ return;
+ }
+
+ // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
+ // same code as SU. It is already updated in PHY_REG_1T_HP.txt.
+#if 0
+ PHY_SetBBReg(Adapter, 0xee8, BIT28, 1);
+ temp = PHY_QueryBBReg(Adapter, 0x860, bMaskDWord);
+ temp |= (BIT26|BIT21|BIT10|BIT5);
+ PHY_SetBBReg(Adapter, 0x860, bMaskDWord, temp);
+ PHY_SetBBReg(Adapter, 0x870, BIT10, 0);
+ PHY_SetBBReg(Adapter, 0xc80, bMaskDWord, 0x20000080);
+ PHY_SetBBReg(Adapter, 0xc88, bMaskDWord, 0x40000100);
+#endif
+
+#endif
+}
+
+/*-----------------------------------------------------------------------------
+ * Function: phy_ConfigBBWithHeaderFile()
+ *
+ * Overview: This function read BB parameters from general file format, and do register
+ * Read/Write
+ *
+ * Input: PADAPTER Adapter
+ * u1Byte ConfigType 0 => PHY_CONFIG
+ * 1 =>AGC_TAB
+ *
+ * Output: NONE
+ *
+ * Return: RT_STATUS_SUCCESS: configuration file exist
+ *
+ *---------------------------------------------------------------------------*/
+#ifndef CONFIG_PHY_SETTING_WITH_ODM
+static int
+phy_ConfigBBWithHeaderFile(
+ IN PADAPTER Adapter,
+ IN u8 ConfigType
+)
+{
+ int i;
+ u32* Rtl819XPHY_REGArray_Table;
+ u32* Rtl819XAGCTAB_Array_Table;
+ u16 PHY_REGArrayLen, AGCTAB_ArrayLen;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ int ret = _SUCCESS;
+
+
+ AGCTAB_ArrayLen = Rtl8723_AGCTAB_1TArrayLength;
+ Rtl819XAGCTAB_Array_Table = (u32*)Rtl8723_AGCTAB_1TArray;
+ PHY_REGArrayLen = Rtl8723_PHY_REG_1TArrayLength;
+ Rtl819XPHY_REGArray_Table = (u32*)Rtl8723_PHY_REG_1TArray;
+// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8723AGCTAB_1TArray\n"));
+// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8723PHY_REG_1TArray\n"));
+
+ if(ConfigType == BaseBand_Config_PHY_REG)
+ {
+ #ifdef CONFIG_IOL_BB_PHY_REG
+ {
+ struct xmit_frame *xmit_frame;
+ u32 tmp_value;
+
+ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
+ ret = _FAIL;
+ goto exit;
+ }
+
+ for(i=0;i<PHY_REGArrayLen;i=i+2)
+ {
+ tmp_value=Rtl819XPHY_REGArray_Table[i+1];
+
+ if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
+ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
+ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
+ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
+ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
+ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
+ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);
+
+ rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XPHY_REGArray_Table[i], tmp_value);
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]));
+ }
+
+ ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);
+ }
+ #else
+ for(i=0;i<PHY_REGArrayLen;i=i+2)
+ {
+ if (Rtl819XPHY_REGArray_Table[i] == 0xfe){
+ #ifdef CONFIG_LONG_DELAY_ISSUE
+ rtw_msleep_os(50);
+ #else
+ rtw_mdelay_os(50);
+ #endif
+ }
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
+ rtw_mdelay_os(5);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
+ rtw_mdelay_os(1);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
+ rtw_udelay_os(50);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
+ rtw_udelay_os(5);
+ else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
+ rtw_udelay_os(1);
+
+ PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
+
+ // Add 1us delay between BB/RF register setting.
+ rtw_udelay_os(1);
+
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]));
+ }
+ #endif
+ // for External PA
+ phy_ConfigBBExternalPA(Adapter);
+ }
+ else if(ConfigType == BaseBand_Config_AGC_TAB)
+ {
+ #ifdef CONFIG_IOL_BB_AGC_TAB
+ {
+ struct xmit_frame *xmit_frame;
+
+ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
+ ret = _FAIL;
+ goto exit;
+ }
+
+ for(i=0;i<AGCTAB_ArrayLen;i=i+2)
+ {
+ rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XAGCTAB_Array_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]));
+ }
+
+ ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);
+ }
+ #else
+ for(i=0;i<AGCTAB_ArrayLen;i=i+2)
+ {
+ PHY_SetBBReg(Adapter, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
+
+ // Add 1us delay between BB/RF register setting.
+ rtw_udelay_os(1);
+
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XAGCTAB_Array_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]));
+ }
+ #endif
+ }
+
+exit:
+ return ret;
+}
+
+#endif
+VOID
+storePwrIndexDiffRateOffset(
+ IN PADAPTER Adapter,
+ IN u32 RegAddr,
+ IN u32 BitMask,
+ IN u32 Data
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ if(RegAddr == rTxAGC_A_Rate18_06)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]));
+ }
+ if(RegAddr == rTxAGC_A_Rate54_24)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1]));
+ }
+ if(RegAddr == rTxAGC_A_CCK1_Mcs32)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6]));
+ }
+ if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7]));
+ }
+ if(RegAddr == rTxAGC_A_Mcs03_Mcs00)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2]));
+ }
+ if(RegAddr == rTxAGC_A_Mcs07_Mcs04)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3]));
+ }
+ if(RegAddr == rTxAGC_A_Mcs11_Mcs08)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4]));
+ }
+ if(RegAddr == rTxAGC_A_Mcs15_Mcs12)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5]));
+ }
+ if(RegAddr == rTxAGC_B_Rate18_06)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8]));
+ }
+ if(RegAddr == rTxAGC_B_Rate54_24)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9]));
+ }
+ if(RegAddr == rTxAGC_B_CCK1_55_Mcs32)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14]));
+ }
+ if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15]));
+ }
+ if(RegAddr == rTxAGC_B_Mcs03_Mcs00)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10]));
+ }
+ if(RegAddr == rTxAGC_B_Mcs07_Mcs04)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11]));
+ }
+ if(RegAddr == rTxAGC_B_Mcs11_Mcs08)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12]));
+ }
+ if(RegAddr == rTxAGC_B_Mcs15_Mcs12)
+ {
+ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data;
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%lx\n", pHalData->pwrGroupCnt,
+ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13]));
+ pHalData->pwrGroupCnt++;
+ }
+}
+/*-----------------------------------------------------------------------------
+ * Function: phy_ConfigBBWithPgParaFile
+ *
+ * Overview:
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 11/06/2008 MHC Create Version 0.
+ * 2009/07/29 tynli (porting from 92SE branch)2009/03/11 Add copy parameter file to buffer for silent reset
+ *---------------------------------------------------------------------------*/
+static int
+phy_ConfigBBWithPgParaFile(
+ IN PADAPTER Adapter,
+ IN u8* pFileName)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ int rtStatus = _SUCCESS;
+
+
+ return rtStatus;
+
+} /* phy_ConfigBBWithPgParaFile */
+
+
+/*-----------------------------------------------------------------------------
+ * Function: phy_ConfigBBWithPgHeaderFile
+ *
+ * Overview: Config PHY_REG_PG array
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!!
+ * 11/10/2008 tynli Modify to mew files.
+ *---------------------------------------------------------------------------*/
+static int
+phy_ConfigBBWithPgHeaderFile(
+ IN PADAPTER Adapter,
+ IN u8 ConfigType)
+{
+ int i;
+ u32* Rtl819XPHY_REGArray_Table_PG;
+ u16 PHY_REGArrayPGLen;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+
+ PHY_REGArrayPGLen = Rtl8723_PHY_REG_Array_PGLength;
+ Rtl819XPHY_REGArray_Table_PG = (u32*)Rtl8723_PHY_REG_Array_PG;
+
+ if(ConfigType == BaseBand_Config_PHY_REG)
+ {
+ for(i=0;i<PHY_REGArrayPGLen;i=i+3)
+ {
+ #if 0 //without IO, no delay is neeeded...
+ if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe){
+ #ifdef CONFIG_LONG_DELAY_ISSUE
+ rtw_msleep_os(50);
+ #else
+ rtw_mdelay_os(50);
+ #endif
+ }
+ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
+ rtw_mdelay_os(5);
+ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
+ rtw_mdelay_os(1);
+ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
+ rtw_udelay_os(50);
+ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
+ rtw_udelay_os(5);
+ else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
+ rtw_udelay_os(1);
+ //PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
+ #endif
+
+ storePwrIndexDiffRateOffset(Adapter, Rtl819XPHY_REGArray_Table_PG[i],
+ Rtl819XPHY_REGArray_Table_PG[i+1],
+ Rtl819XPHY_REGArray_Table_PG[i+2]);
+ //RT_TRACE(COMP_SEND, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]));
+ }
+ }
+ else
+ {
+
+ //RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"));
+ }
+
+ return _SUCCESS;
+
+} /* phy_ConfigBBWithPgHeaderFile */
+
+#if (MP_DRIVER == 1)
+
+/*-----------------------------------------------------------------------------
+ * Function: phy_ConfigBBWithMpParaFile()
+ *
+ * Overview: This function read BB parameters from general file format, and do register
+ * Read/Write
+ *
+ * Input: PADAPTER Adapter
+ * ps1Byte pFileName
+ *
+ * Output: NONE
+ *
+ * Return: RT_STATUS_SUCCESS: configuration file exist
+ * 2008/11/06 MH For 92S we do not support silent reset now. Disable
+ * parameter file compare!!!!!!??
+ *
+ *---------------------------------------------------------------------------*/
+static int
+phy_ConfigBBWithMpParaFile(
+ IN PADAPTER Adapter,
+ IN u8* pFileName
+)
+{
+#if 1
+ int rtStatus = _SUCCESS;
+#else
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ s4Byte nLinesRead, ithLine;
+ RT_STATUS rtStatus = RT_STATUS_SUCCESS;
+ ps1Byte szLine;
+ u4Byte u4bRegOffset, u4bRegMask, u4bRegValue;
+ u4Byte u4bMove;
+
+ if(ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FIRST_INIT))
+ {
+ rtStatus = PlatformReadFile(
+ Adapter,
+ pFileName,
+ (pu1Byte)(pHalData->BufOfLines),
+ MAX_LINES_HWCONFIG_TXT,
+ MAX_BYTES_LINE_HWCONFIG_TXT,
+ &nLinesRead
+ );
+ if(rtStatus == RT_STATUS_SUCCESS)
+ {
+ PlatformMoveMemory(pHalData->BufOfLines6, pHalData->BufOfLines, nLinesRead*MAX_BYTES_LINE_HWCONFIG_TXT);
+ pHalData->nLinesRead6 = nLinesRead;
+ }
+ else
+ {
+ // Temporarily skip PHY_REG_MP.txt if file does not exist.
+ pHalData->nLinesRead6 = 0;
+ RT_TRACE(COMP_INIT, DBG_LOUD, ("No matched file \r\n"));
+ return RT_STATUS_SUCCESS;
+ }
+ }
+ else
+ {
+ PlatformMoveMemory(pHalData->BufOfLines, pHalData->BufOfLines6, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT);
+ nLinesRead = pHalData->nLinesRead6;
+ rtStatus = RT_STATUS_SUCCESS;
+ }
+
+
+ if(rtStatus == RT_STATUS_SUCCESS)
+ {
+ RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_ConfigBBWithMpParaFile(): read %s ok\n", pFileName));
+
+ for(ithLine = 0; ithLine < nLinesRead; ithLine++)
+ {
+ szLine = pHalData->BufOfLines[ithLine];
+
+ if(!IsCommentString(szLine))
+ {
+ // Get 1st hex value as register offset.
+ if(GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove))
+ {
+ if(u4bRegOffset == 0xff)
+ { // Ending.
+ break;
+ }
+ else if (u4bRegOffset == 0xfe)
+ delay_ms(50);
+ else if (u4bRegOffset == 0xfd)
+ delay_ms(5);
+ else if (u4bRegOffset == 0xfc)
+ delay_ms(1);
+ else if (u4bRegOffset == 0xfb)
+ PlatformStallExecution(50);
+ else if (u4bRegOffset == 0xfa)
+ PlatformStallExecution(5);
+ else if (u4bRegOffset == 0xf9)
+ PlatformStallExecution(1);
+
+ // Get 2nd hex value as register value.
+ szLine += u4bMove;
+ if(GetHexValueFromString(szLine, &u4bRegValue, &u4bMove))
+ {
+ RT_TRACE(COMP_FPGA, DBG_TRACE, ("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue));
+ PHY_SetBBReg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
+
+ // Add 1us delay between BB/RF register setting.
+ PlatformStallExecution(1);
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_ConfigBBWithMpParaFile(): Failed%s\n", pFileName));
+ }
+#endif
+
+ return rtStatus;
+}
+
+/*-----------------------------------------------------------------------------
+ * Function: phy_ConfigBBWithMpHeaderFile
+ *
+ * Overview: Config PHY_REG_MP array
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 02/04/2010 chiyokolin Modify to new files.
+ *---------------------------------------------------------------------------*/
+static int
+phy_ConfigBBWithMpHeaderFile(
+ IN PADAPTER Adapter,
+ IN u1Byte ConfigType)
+{
+ int i;
+ u32* Rtl8192CPHY_REGArray_Table_MP;
+ u16 PHY_REGArrayMPLen;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+
+ PHY_REGArrayMPLen = Rtl8723_PHY_REG_Array_MPLength;
+ Rtl8192CPHY_REGArray_Table_MP = (u32*)Rtl8723_PHY_REG_Array_MP;
+
+ if(ConfigType == BaseBand_Config_PHY_REG)
+ {
+ for(i=0;i<PHY_REGArrayMPLen;i=i+2)
+ {
+ if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfe) {
+ #ifdef CONFIG_LONG_DELAY_ISSUE
+ rtw_msleep_os(50);
+ #else
+ rtw_mdelay_os(50);
+ #endif
+ }
+ else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfd)
+ rtw_mdelay_os(5);
+ else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfc)
+ rtw_mdelay_os(1);
+ else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfb) {
+ #ifdef CONFIG_LONG_DELAY_ISSUE
+ rtw_msleep_os(50);
+ #else
+ rtw_mdelay_os(50);
+ #endif
+ }
+ else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfa)
+ rtw_mdelay_os(5);
+ else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xf9)
+ rtw_mdelay_os(1);
+ PHY_SetBBReg(Adapter, Rtl8192CPHY_REGArray_Table_MP[i], bMaskDWord, Rtl8192CPHY_REGArray_Table_MP[i+1]);
+
+ // Add 1us delay between BB/RF register setting.
+ rtw_mdelay_os(1);
+
+// RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl8192CPHY_REGArray_Table_MP[%d] is %lx Rtl8192CPHY_REGArray_Table_MP[%d] is %lx \n", i, i+1, Rtl8192CPHY_REGArray_Table_MP[i], Rtl8192CPHY_REGArray_Table_MP[i+1]));
+ }
+ }
+ else
+ {
+// RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithMpHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"));
+ }
+
+ return _SUCCESS;
+} /* phy_ConfigBBWithMpHeaderFile */
+
+#endif // #if (MP_DRIVER == 1)
+
+static VOID
+phy_BB8192C_Config_1T(
+ IN PADAPTER Adapter
+ )
+{
+#if 0
+ //for path - A
+ PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x1);
+ PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x0303, 0x0101);
+ PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x1);
+ PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x1);
+ PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x1);
+ PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x1);
+ PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x1);
+#endif
+ //for path - B
+ PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);
+ PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022);
+
+ // 20100519 Joseph: Add for 1T2R config. Suggested by Kevin, Jenyu and Yunan.
+ PHY_SetBBReg(Adapter, rCCK0_AFESetting, bMaskByte3, 0x45);
+ PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x23);
+ PHY_SetBBReg(Adapter, rOFDM0_AGCParameter1, 0x30, 0x1); // B path first AGC
+
+ PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x2);
+ PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x2);
+ PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x2);
+ PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x2);
+ PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x2);
+
+
+}
+
+// Joseph test: new initialize order!!
+// Test only!! This part need to be re-organized.
+// Now it is just for 8256.
+static int
+phy_BB8190_Config_HardCode(
+ IN PADAPTER Adapter
+ )
+{
+ //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
+ return _SUCCESS;
+}
+
+static int
+phy_BB8723a_Config_ParaFile(
+ IN PADAPTER Adapter
+ )
+{
+ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ int rtStatus = _SUCCESS;
+
+ u8 sz8723BBRegFile[] = RTL8723_PHY_REG;
+ u8 sz8723AGCTableFile[] = RTL8723_AGC_TAB;
+ u8 sz8723BBRegPgFile[] = RTL8723_PHY_REG_PG;
+ u8 sz8723BBRegMpFile[] = RTL8723_PHY_REG_MP;
+
+ u8 *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile=NULL;
+
+
+ //RT_TRACE(COMP_INIT, DBG_TRACE, ("==>phy_BB8192S_Config_ParaFile\n"));
+
+ pszBBRegFile = sz8723BBRegFile ;
+ pszAGCTableFile = sz8723AGCTableFile;
+ pszBBRegPgFile = sz8723BBRegPgFile;
+ pszBBRegMpFile = sz8723BBRegMpFile;
+
+ //
+ // 1. Read PHY_REG.TXT BB INIT!!
+ // We will seperate as 88C / 92C according to chip version
+ //
+#ifdef CONFIG_EMBEDDED_FWIMG
+ #ifdef CONFIG_PHY_SETTING_WITH_ODM
+ if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
+ rtStatus = _FAIL;
+ #else
+ rtStatus = phy_ConfigBBWithHeaderFile(Adapter, BaseBand_Config_PHY_REG);
+ #endif
+#else
+ // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different
+ // type of parameter files to phy_reg.txt at first.
+ rtStatus = phy_ConfigBBWithParaFile(Adapter,pszBBRegFile);
+#endif//#ifdef CONFIG_EMBEDDED_FWIMG
+
+ if(rtStatus != _SUCCESS){
+ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!"));
+ goto phy_BB8190_Config_ParaFile_Fail;
+ }
+
+#if MP_DRIVER == 1
+ if (Adapter->registrypriv.mp_mode == 1)
+ {
+ //
+ // 1.1 Read PHY_REG_MP.TXT BB INIT!!
+ // We will seperate as 88C / 92C according to chip version
+ //
+#ifdef CONFIG_EMBEDDED_FWIMG
+ rtStatus = phy_ConfigBBWithMpHeaderFile(Adapter, BaseBand_Config_PHY_REG);
+#else
+ // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different
+ // type of parameter files to phy_reg.txt at first.
+ rtStatus = phy_ConfigBBWithMpParaFile(Adapter, pszBBRegMpFile);
+#endif
+
+ if(rtStatus != _SUCCESS){
+// RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg MP Fail!!"));
+ goto phy_BB8190_Config_ParaFile_Fail;
+ }
+ }
+#endif // #if (MP_DRIVER == 1)
+
+ //
+ // 20100318 Joseph: Config 2T2R to 1T2R if necessary.
+ //
+ if(pHalData->rf_type == RF_1T2R)
+ {
+ phy_BB8192C_Config_1T(Adapter);
+ DBG_8192C("phy_BB8723a_Config_ParaFile():Config to 1T!!\n");
+ }
+
+ //
+ // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
+ //
+ if (pEEPROM->bautoload_fail_flag == _FALSE)
+ {
+ pHalData->pwrGroupCnt = 0;
+
+#ifdef CONFIG_EMBEDDED_FWIMG
+ rtStatus = phy_ConfigBBWithPgHeaderFile(Adapter, BaseBand_Config_PHY_REG);
+#else
+ rtStatus = phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile);
+#endif
+ }
+
+ if(rtStatus != _SUCCESS){
+ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!"));
+ goto phy_BB8190_Config_ParaFile_Fail;
+ }
+
+ //
+ // 3. BB AGC table Initialization
+ //
+#ifdef CONFIG_EMBEDDED_FWIMG
+ #ifdef CONFIG_PHY_SETTING_WITH_ODM
+ if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
+ rtStatus = _FAIL;
+ #else
+ rtStatus = phy_ConfigBBWithHeaderFile(Adapter, BaseBand_Config_AGC_TAB);
+ #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM
+#else
+ //RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_BB8192S_Config_ParaFile AGC_TAB.txt\n"));
+ rtStatus = phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile);
+#endif
+
+ if(rtStatus != _SUCCESS){
+ //RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n"));
+ goto phy_BB8190_Config_ParaFile_Fail;
+ }
+
+phy_BB8190_Config_ParaFile_Fail:
+
+ return rtStatus;
+}
+
+
+int
+PHY_BBConfig8723A(
+ IN PADAPTER Adapter
+ )
+{
+ int rtStatus = _SUCCESS;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u32 RegVal;
+ u8 TmpU1B=0;
+ u8 value8,CrystalCap;
+
+ phy_InitBBRFRegisterDefinition(Adapter);
+
+ if(IS_HARDWARE_TYPE_8723A(Adapter))
+ {
+ // Suggested by Scott. tynli_test. 2010.12.30.
+ //1. 0x28[1] = 1
+ TmpU1B = rtw_read8(Adapter, REG_AFE_PLL_CTRL);
+ rtw_udelay_os(2);
+ rtw_write8(Adapter, REG_AFE_PLL_CTRL, (TmpU1B|BIT1));
+ rtw_udelay_os(2);
+
+ //2. 0x29[7:0] = 0xFF
+ rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff);
+ rtw_udelay_os(2);
+
+ //3. 0x02[1:0] = 2b'11
+ TmpU1B = rtw_read8(Adapter, REG_SYS_FUNC_EN);
+ rtw_write8(Adapter, REG_SYS_FUNC_EN, (TmpU1B|FEN_BB_GLB_RSTn|FEN_BBRSTB));
+
+ //4. 0x25[6] = 0
+ TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+1);
+ rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, (TmpU1B&(~BIT6)));
+
+ //5. 0x24[20] = 0 //Advised by SD3 Alex Wang. 2011.02.09.
+ TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+2);
+ rtw_write8(Adapter, REG_AFE_XTAL_CTRL+2, (TmpU1B&(~BIT4)));
+
+ //6. 0x1f[7:0] = 0x07
+ rtw_write8(Adapter, REG_RF_CTRL, 0x07);
+ }
+ else
+ {
+ // Enable BB and RF
+ RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
+ rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
+
+ // 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF.
+ rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);
+ rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb);
+
+ rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
+
+#ifdef CONFIG_USB_HCI
+ rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
+#else
+ rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
+#endif
+
+ // 2009/10/21 by SD1 Jong. Modified by tynli. Not in Documented in V8.1.
+#ifdef CONFIG_USB_HCI
+ //To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23.
+ rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f);
+ rtw_write8(Adapter, 0x15, 0xe9);
+#endif
+
+ rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
+
+#ifdef CONFIG_PCI_HCI
+ // Force use left antenna by default for 88C.
+ // if(!IS_92C_SERIAL(pHalData->VersionID) || IS_92C_1T2R(pHalData->VersionID))
+ if(Adapter->ledpriv.LedStrategy != SW_LED_MODE10)
+ {
+ RegVal = rtw_read32(Adapter, REG_LEDCFG0);
+ rtw_write32(Adapter, REG_LEDCFG0, RegVal|BIT23);
+ }
+#endif
+ }
+
+ //
+ // Config BB and AGC
+ //
+ rtStatus = phy_BB8723a_Config_ParaFile(Adapter);
+
+#ifdef CONFIG_USB_HCI
+ if(IS_HARDWARE_TYPE_8192CU(Adapter)&&IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)
+ &&(pHalData->BoardType == BOARD_USB_High_PA))
+ rtw_write8(Adapter, 0xc72, 0x50);
+#endif
+//only for B-cut
+ if(IS_HARDWARE_TYPE_8723A(Adapter) && pHalData->EEPROMVersion >= 0x01)
+ {
+ CrystalCap = pHalData->CrystalCap & 0x3F;
+ PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
+ }
+
+ if(IS_HARDWARE_TYPE_8723AE(Adapter))
+ PHY_SetBBReg(Adapter, REG_LDOA15_CTRL, bMaskDWord, 0x01572505);
+ return rtStatus;
+}
+
+
+int
+PHY_RFConfig8723A(
+ IN PADAPTER Adapter
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ int rtStatus = _SUCCESS;
+
+ //
+ // RF config
+ //
+ rtStatus = PHY_RF6052_Config8723A(Adapter);
+ return rtStatus;
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Function: PHY_ConfigRFWithParaFile()
+ *
+ * Overview: This function read RF parameters from general file format, and do RF 3-wire
+ *
+ * Input: PADAPTER Adapter
+ * ps1Byte pFileName
+ * RF_RADIO_PATH_E eRFPath
+ *
+ * Output: NONE
+ *
+ * Return: RT_STATUS_SUCCESS: configuration file exist
+ *
+ * Note: Delay may be required for RF configuration
+ *---------------------------------------------------------------------------*/
+int
+rtl8192c_PHY_ConfigRFWithParaFile(
+ IN PADAPTER Adapter,
+ IN u8* pFileName,
+ RF_RADIO_PATH_E eRFPath
+)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ int rtStatus = _SUCCESS;
+
+
+ return rtStatus;
+
+}
+
+//****************************************
+// The following is for High Power PA
+//****************************************
+#define HighPowerRadioAArrayLen 22
+//This is for High power PA
+u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = {
+0x013,0x00029ea4,
+0x013,0x00025e74,
+0x013,0x00020ea4,
+0x013,0x0001ced0,
+0x013,0x00019f40,
+0x013,0x00014e70,
+0x013,0x000106a0,
+0x013,0x0000c670,
+0x013,0x000082a0,
+0x013,0x00004270,
+0x013,0x00000240,
+};
+
+int
+PHY_ConfigRFExternalPA(
+ IN PADAPTER Adapter,
+ RF_RADIO_PATH_E eRFPath
+)
+{
+ int rtStatus = _SUCCESS;
+#ifdef CONFIG_USB_HCI
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u16 i=0;
+
+ if(!pHalData->ExternalPA)
+ {
+ return rtStatus;
+ }
+
+ // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
+ // same code as SU. It is already updated in radio_a_1T_HP.txt.
+#if 0
+ //add for SU High Power PA
+ for(i = 0;i<HighPowerRadioAArrayLen; i=i+2)
+ {
+ RT_TRACE(COMP_INIT, DBG_LOUD, ("External PA, write RF 0x%lx=0x%lx\n", Rtl8192S_HighPower_RadioA_Array[i], Rtl8192S_HighPower_RadioA_Array[i+1]));
+ PHY_SetRFReg(Adapter, eRFPath, Rtl8192S_HighPower_RadioA_Array[i], bRFRegOffsetMask, Rtl8192S_HighPower_RadioA_Array[i+1]);
+ }
+#endif
+
+#endif
+ return rtStatus;
+}
+//****************************************
+/*-----------------------------------------------------------------------------
+ * Function: PHY_ConfigRFWithHeaderFile()
+ *
+ * Overview: This function read RF parameters from general file format, and do RF 3-wire
+ *
+ * Input: PADAPTER Adapter
+ * ps1Byte pFileName
+ * RF_RADIO_PATH_E eRFPath
+ *
+ * Output: NONE
+ *
+ * Return: RT_STATUS_SUCCESS: configuration file exist
+ *
+ * Note: Delay may be required for RF configuration
+ *---------------------------------------------------------------------------*/
+#ifndef CONFIG_PHY_SETTING_WITH_ODM
+int
+rtl8723a_PHY_ConfigRFWithHeaderFile(
+ IN PADAPTER Adapter,
+ RF_RADIO_PATH_E eRFPath
+)
+{
+
+ int i;
+ int rtStatus = _SUCCESS;
+ u32* Rtl819XRadioA_Array_Table;
+ u32* Rtl819XRadioB_Array_Table;
+ u16 RadioA_ArrayLen,RadioB_ArrayLen;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+
+ RadioA_ArrayLen = Rtl8723_RadioA_1TArrayLength;
+ Rtl819XRadioA_Array_Table = (u32*)Rtl8723_RadioA_1TArray;
+ RadioB_ArrayLen = Rtl8723_RadioB_1TArrayLength;
+ Rtl819XRadioB_Array_Table = (u32*)Rtl8723_RadioB_1TArray;
+// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_A:Rtl8723RadioA_1TArray\n"));
+// RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_B:Rtl8723RadioB_1TArray\n"));
+
+ switch (eRFPath)
+ {
+ case RF_PATH_A:
+ #ifdef CONFIG_IOL_RF_RF90_PATH_A
+ {
+ struct xmit_frame *xmit_frame;
+ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
+ rtStatus = _FAIL;
+ goto exit;
+ }
+
+ for(i = 0;i<RadioA_ArrayLen; i=i+2)
+ {
+ if(Rtl819XRadioA_Array_Table[i] == 0xfe)
+ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
+ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
+ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
+ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
+ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
+ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);
+ else
+ {
+ BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
+ u32 NewOffset = 0;
+ u32 DataAndAddr = 0;
+
+ NewOffset = Rtl819XRadioA_Array_Table[i] & 0x3f;
+ DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioA_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF
+ rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr);
+ }
+ }
+ rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);
+ }
+ #else
+ for(i = 0;i<RadioA_ArrayLen; i=i+2)
+ {
+ if(Rtl819XRadioA_Array_Table[i] == 0xfe) {
+ #ifdef CONFIG_LONG_DELAY_ISSUE
+ rtw_msleep_os(50);
+ #else
+ rtw_mdelay_os(50);
+ #endif
+ }
+ else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
+ rtw_mdelay_os(5);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
+ rtw_mdelay_os(1);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
+ rtw_udelay_os(50);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
+ rtw_udelay_os(5);
+ else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
+ rtw_udelay_os(1);
+ else
+ {
+ PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
+ // Add 1us delay between BB/RF register setting.
+ rtw_udelay_os(1);
+ }
+ }
+ #endif
+ //Add for High Power PA
+ PHY_ConfigRFExternalPA(Adapter, eRFPath);
+ break;
+ case RF_PATH_B:
+ #ifdef CONFIG_IOL_RF_RF_PATH_B
+ {
+ struct xmit_frame *xmit_frame;
+ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
+ rtStatus = _FAIL;
+ goto exit;
+ }
+
+ for(i = 0;i<RadioB_ArrayLen; i=i+2)
+ {
+ if(Rtl819XRadioB_Array_Table[i] == 0xfe)
+ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
+ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
+ rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
+ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
+ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
+ rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);
+ else
+ {
+ BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
+ u32 NewOffset = 0;
+ u32 DataAndAddr = 0;
+
+ NewOffset = Rtl819XRadioB_Array_Table[i] & 0x3f;
+ DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioB_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF
+ rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr);
+ }
+ }
+ rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);
+ }
+ #else
+ for(i = 0;i<RadioB_ArrayLen; i=i+2)
+ {
+ if(Rtl819XRadioB_Array_Table[i] == 0xfe)
+ { // Deay specific ms. Only RF configuration require delay.
+#if 0//#ifdef CONFIG_USB_HCI
+ #ifdef CONFIG_LONG_DELAY_ISSUE
+ rtw_msleep_os(1000);
+ #else
+ rtw_mdelay_os(1000);
+ #endif
+#else
+ #ifdef CONFIG_LONG_DELAY_ISSUE
+ rtw_msleep_os(50);
+ #else
+ rtw_mdelay_os(50);
+ #endif
+#endif
+ }
+ else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
+ rtw_mdelay_os(5);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
+ rtw_mdelay_os(1);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
+ rtw_udelay_os(50);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
+ rtw_udelay_os(5);
+ else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
+ rtw_udelay_os(1);
+ else
+ {
+ PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
+ // Add 1us delay between BB/RF register setting.
+ rtw_udelay_os(1);
+ }
+ }
+ #endif
+ break;
+ case RF_PATH_C:
+ break;
+ case RF_PATH_D:
+ break;
+ }
+
+exit:
+ return rtStatus;
+
+}
+#endif
+
+/*-----------------------------------------------------------------------------
+ * Function: PHY_CheckBBAndRFOK()
+ *
+ * Overview: This function is write register and then readback to make sure whether
+ * BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
+ *
+ * Input: PADAPTER Adapter
+ * HW90_BLOCK_E CheckBlock
+ * RF_RADIO_PATH_E eRFPath // it is used only when CheckBlock is HW90_BLOCK_RF
+ *
+ * Output: NONE
+ *
+ * Return: RT_STATUS_SUCCESS: PHY is OK
+ *
+ * Note: This function may be removed in the ASIC
+ *---------------------------------------------------------------------------*/
+int
+PHY_CheckBBAndRFOK(
+ IN PADAPTER Adapter,
+ IN HW90_BLOCK_E CheckBlock,
+ IN RF_RADIO_PATH_E eRFPath
+ )
+{
+ int rtStatus = _SUCCESS;
+
+ u32 i, CheckTimes = 4,ulRegRead = 0;
+
+ u32 WriteAddr[4];
+ u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
+
+ // Initialize register address offset to be checked
+ WriteAddr[HW90_BLOCK_MAC] = 0x100;
+ WriteAddr[HW90_BLOCK_PHY0] = 0x900;
+ WriteAddr[HW90_BLOCK_PHY1] = 0x800;
+ WriteAddr[HW90_BLOCK_RF] = 0x3;
+
+ for(i=0 ; i < CheckTimes ; i++)
+ {
+
+ //
+ // Write Data to register and readback
+ //
+ switch(CheckBlock)
+ {
+ case HW90_BLOCK_MAC:
+ //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
+ //RT_TRACE(COMP_INIT, DBG_LOUD, ("PHY_CheckBBRFOK(): Never Write 0x100 here!\n"));
+ break;
+
+ case HW90_BLOCK_PHY0:
+ case HW90_BLOCK_PHY1:
+ rtw_write32(Adapter, WriteAddr[CheckBlock], WriteData[i]);
+ ulRegRead = rtw_read32(Adapter, WriteAddr[CheckBlock]);
+ break;
+
+ case HW90_BLOCK_RF:
+ // When initialization, we want the delay function(delay_ms(), delay_us()
+ // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
+ // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
+ // to run at Dispatch level to achive it.
+ //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
+ WriteData[i] &= 0xfff;
+ PHY_SetRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
+ // TODO: we should not delay for such a long time. Ask SD3
+ rtw_mdelay_os(10);
+ ulRegRead = PHY_QueryRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
+ rtw_mdelay_os(10);
+ //cosa PlatformReleaseSpinLock(Adapter, RT_INITIAL_SPINLOCK);
+ break;
+
+ default:
+ rtStatus = _FAIL;
+ break;
+ }
+
+
+ //
+ // Check whether readback data is correct
+ //
+ if(ulRegRead != WriteData[i])
+ {
+ //RT_TRACE(COMP_FPGA, DBG_LOUD, ("ulRegRead: %lx, WriteData: %lx \n", ulRegRead, WriteData[i]));
+ rtStatus = _FAIL;
+ break;
+ }
+ }
+
+ return rtStatus;
+}
+
+
+VOID
+rtl8192c_PHY_GetHWRegOriginalValue(
+ IN PADAPTER Adapter
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ // read rx initial gain
+ pHalData->DefaultInitialGain[0] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XAAGCCore1, bMaskByte0);
+ pHalData->DefaultInitialGain[1] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XBAGCCore1, bMaskByte0);
+ pHalData->DefaultInitialGain[2] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XCAGCCore1, bMaskByte0);
+ pHalData->DefaultInitialGain[3] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XDAGCCore1, bMaskByte0);
+ //RT_TRACE(COMP_INIT, DBG_LOUD,
+ //("Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
+ //pHalData->DefaultInitialGain[0], pHalData->DefaultInitialGain[1],
+ //pHalData->DefaultInitialGain[2], pHalData->DefaultInitialGain[3]));
+
+ // read framesync
+ pHalData->framesync = (u8)PHY_QueryBBReg(Adapter, rOFDM0_RxDetector3, bMaskByte0);
+ pHalData->framesyncC34 = PHY_QueryBBReg(Adapter, rOFDM0_RxDetector2, bMaskDWord);
+ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Default framesync (0x%x) = 0x%x \n",
+ // rOFDM0_RxDetector3, pHalData->framesync));
+}
+
+
+//
+// Description:
+// Map dBm into Tx power index according to
+// current HW model, for example, RF and PA, and
+// current wireless mode.
+// By Bruce, 2008-01-29.
+//
+static u8
+phy_DbmToTxPwrIdx(
+ IN PADAPTER Adapter,
+ IN WIRELESS_MODE WirelessMode,
+ IN int PowerInDbm
+ )
+{
+ u8 TxPwrIdx = 0;
+ int Offset = 0;
+
+
+ //
+ // Tested by MP, we found that CCK Index 0 equals to 8dbm, OFDM legacy equals to
+ // 3dbm, and OFDM HT equals to 0dbm repectively.
+ // Note:
+ // The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
+ // By Bruce, 2008-01-29.
+ //
+ switch(WirelessMode)
+ {
+ case WIRELESS_MODE_B:
+ Offset = -7;
+ break;
+
+ case WIRELESS_MODE_G:
+ case WIRELESS_MODE_N_24G:
+ Offset = -8;
+ break;
+ default:
+ Offset = -8;
+ break;
+ }
+
+ if((PowerInDbm - Offset) > 0)
+ {
+ TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
+ }
+ else
+ {
+ TxPwrIdx = 0;
+ }
+
+ // Tx Power Index is too large.
+ if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
+ TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
+
+ return TxPwrIdx;
+}
+
+//
+// Description:
+// Map Tx power index into dBm according to
+// current HW model, for example, RF and PA, and
+// current wireless mode.
+// By Bruce, 2008-01-29.
+//
+int
+phy_TxPwrIdxToDbm(
+ IN PADAPTER Adapter,
+ IN WIRELESS_MODE WirelessMode,
+ IN u8 TxPwrIdx
+ )
+{
+ int Offset = 0;
+ int PwrOutDbm = 0;
+
+ //
+ // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to -8dbm.
+ // Note:
+ // The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
+ // By Bruce, 2008-01-29.
+ //
+ switch(WirelessMode)
+ {
+ case WIRELESS_MODE_B:
+ Offset = -7;
+ break;
+
+ case WIRELESS_MODE_G:
+ case WIRELESS_MODE_N_24G:
+ Offset = -8;
+ default:
+ Offset = -8;
+ break;
+ }
+
+ PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
+
+ return PwrOutDbm;
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Function: GetTxPowerLevel8190()
+ *
+ * Overview: This function is export to "common" moudule
+ *
+ * Input: PADAPTER Adapter
+ * psByte Power Level
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ *---------------------------------------------------------------------------*/
+VOID
+PHY_GetTxPowerLevel8192C(
+ IN PADAPTER Adapter,
+ OUT u32* powerlevel
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u8 TxPwrLevel = 0;
+ int TxPwrDbm;
+
+ //
+ // Because the Tx power indexes are different, we report the maximum of them to
+ // meet the CCX TPC request. By Bruce, 2008-01-31.
+ //
+
+ // CCK
+ TxPwrLevel = pHalData->CurrentCckTxPwrIdx;
+ TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_B, TxPwrLevel);
+
+ // Legacy OFDM
+ TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx + pHalData->LegacyHTTxPowerDiff;
+
+ // Compare with Legacy OFDM Tx power.
+ if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
+ TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel);
+
+ // HT OFDM
+ TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx;
+
+ // Compare with HT OFDM Tx power.
+ if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
+ TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel);
+
+ *powerlevel = TxPwrDbm;
+}
+
+
+static void getTxPowerIndex(
+ IN PADAPTER Adapter,
+ IN u8 channel,
+ IN OUT u8* cckPowerLevel,
+ IN OUT u8* ofdmPowerLevel
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u8 index = (channel -1);
+ // 1. CCK
+ cckPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelCck[RF_PATH_A][index]; //RF-A
+ cckPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelCck[RF_PATH_B][index]; //RF-B
+
+ // 2. OFDM for 1S or 2S
+ if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R)
+ {
+ // Read HT 40 OFDM TX power
+ ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_1S[RF_PATH_A][index];
+ ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_1S[RF_PATH_B][index];
+ }
+ else if (GET_RF_TYPE(Adapter) == RF_2T2R)
+ {
+ // Read HT 40 OFDM TX power
+ ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_2S[RF_PATH_A][index];
+ ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_2S[RF_PATH_B][index];
+ }
+ //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));
+}
+
+static void ccxPowerIndexCheck(
+ IN PADAPTER Adapter,
+ IN u8 channel,
+ IN OUT u8* cckPowerLevel,
+ IN OUT u8* ofdmPowerLevel
+ )
+{
+#if 0
+ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ PRT_CCX_INFO pCcxInfo = GET_CCX_INFO(pMgntInfo);
+
+ //
+ // CCX 2 S31, AP control of client transmit power:
+ // 1. We shall not exceed Cell Power Limit as possible as we can.
+ // 2. Tolerance is +/- 5dB.
+ // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
+ //
+ // TODO:
+ // 1. 802.11h power contraint
+ //
+ // 071011, by rcnjko.
+ //
+ if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
+ pMgntInfo->mAssoc &&
+ pCcxInfo->bUpdateCcxPwr &&
+ pCcxInfo->bWithCcxCellPwr &&
+ channel == pMgntInfo->dot11CurrentChannelNumber)
+ {
+ u1Byte CckCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pCcxInfo->CcxCellPwr);
+ u1Byte LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pCcxInfo->CcxCellPwr);
+ u1Byte OfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pCcxInfo->CcxCellPwr);
+
+ RT_TRACE(COMP_TXAGC, DBG_LOUD,
+ ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
+ pCcxInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
+ RT_TRACE(COMP_TXAGC, DBG_LOUD,
+ ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
+ channel, cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
+
+ // CCK
+ if(cckPowerLevel[0] > CckCellPwrIdx)
+ cckPowerLevel[0] = CckCellPwrIdx;
+ // Legacy OFDM, HT OFDM
+ if(ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
+ {
+ if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
+ {
+ ofdmPowerLevel[0] = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
+ }
+ else
+ {
+ ofdmPowerLevel[0] = 0;
+ }
+ }
+
+ RT_TRACE(COMP_TXAGC, DBG_LOUD,
+ ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
+ cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
+ }
+
+ pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];
+ pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
+
+ RT_TRACE(COMP_TXAGC, DBG_LOUD,
+ ("PHY_SetTxPowerLevel8192S(): CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
+ cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
+#endif
+}
+/*-----------------------------------------------------------------------------
+ * Function: SetTxPowerLevel8190()
+ *
+ * Overview: This function is export to "HalCommon" moudule
+ * We must consider RF path later!!!!!!!
+ *
+ * Input: PADAPTER Adapter
+ * u1Byte channel
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ * 2008/11/04 MHC We remove EEPROM_93C56.
+ * We need to move CCX relative code to independet file.
+ * 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
+ *
+ *---------------------------------------------------------------------------*/
+VOID
+PHY_SetTxPowerLevel8192C(
+ IN PADAPTER Adapter,
+ IN u8 channel
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u8 cckPowerLevel[2], ofdmPowerLevel[2]; // [0]:RF-A, [1]:RF-B
+/*
+#if(MP_DRIVER == 1)
+ if (Adapter->registrypriv.mp_mode == 1)
+ return;
+#endif
+*/
+ if(pHalData->bTXPowerDataReadFromEEPORM == _FALSE)
+ return;
+
+ getTxPowerIndex(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);
+ //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
+ // channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1]));
+
+ ccxPowerIndexCheck(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);
+
+ rtl8192c_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
+ rtl8192c_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);
+
+#if 0
+ switch(pHalData->rf_chip)
+ {
+ case RF_8225:
+ PHY_SetRF8225CckTxPower(Adapter, cckPowerLevel[0]);
+ PHY_SetRF8225OfdmTxPower(Adapter, ofdmPowerLevel[0]);
+ break;
+
+ case RF_8256:
+ PHY_SetRF8256CCKTxPower(Adapter, cckPowerLevel[0]);
+ PHY_SetRF8256OFDMTxPower(Adapter, ofdmPowerLevel[0]);
+ break;
+
+ case RF_6052:
+ PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
+ PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);
+ break;
+
+ case RF_8258:
+ break;
+ }
+#endif
+
+}
+
+
+//
+// Description:
+// Update transmit power level of all channel supported.
+//
+// TODO:
+// A mode.
+// By Bruce, 2008-02-04.
+//
+BOOLEAN
+PHY_UpdateTxPowerDbm8192C(
+ IN PADAPTER Adapter,
+ IN int powerInDbm
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u8 idx;
+ u8 rf_path;
+
+ // TODO: A mode Tx power.
+ u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, powerInDbm);
+ u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, powerInDbm);
+
+ if(OfdmTxPwrIdx - pHalData->LegacyHTTxPowerDiff > 0)
+ OfdmTxPwrIdx -= pHalData->LegacyHTTxPowerDiff;
+ else
+ OfdmTxPwrIdx = 0;
+
+ //RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx));
+
+ for(idx = 0; idx < 14; idx++)
+ {
+ for (rf_path = 0; rf_path < 2; rf_path++)
+ {
+ pHalData->TxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
+ pHalData->TxPwrLevelHT40_1S[rf_path][idx] =
+ pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx;
+ }
+ }
+
+ //Adapter->HalFunc.SetTxPowerLevelHandler(Adapter, pHalData->CurrentChannel);//gtest:todo
+
+ return _TRUE;
+}
+
+
+/*
+ Description:
+ When beacon interval is changed, the values of the
+ hw registers should be modified.
+ By tynli, 2008.10.24.
+
+*/
+
+
+void
+rtl8192c_PHY_SetBeaconHwReg(
+ IN PADAPTER Adapter,
+ IN u16 BeaconInterval
+ )
+{
+
+}
+
+
+VOID
+PHY_ScanOperationBackup8192C(
+ IN PADAPTER Adapter,
+ IN u8 Operation
+ )
+{
+#if 0
+ IO_TYPE IoType;
+
+ if(!Adapter->bDriverStopped)
+ {
+ switch(Operation)
+ {
+ case SCAN_OPT_BACKUP:
+ IoType = IO_CMD_PAUSE_DM_BY_SCAN;
+ rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
+
+ break;
+
+ case SCAN_OPT_RESTORE:
+ IoType = IO_CMD_RESUME_DM_BY_SCAN;
+ rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
+ break;
+
+ default:
+ RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
+ break;
+ }
+ }
+#endif
+}
+
+/*-----------------------------------------------------------------------------
+ * Function: PHY_SetBWModeCallback8192C()
+ *
+ * Overview: Timer callback function for SetSetBWMode
+ *
+ * Input: PRT_TIMER pTimer
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Note: (1) We do not take j mode into consideration now
+ * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
+ * concurrently?
+ *---------------------------------------------------------------------------*/
+static VOID
+_PHY_SetBWMode92C(
+ IN PADAPTER Adapter
+)
+{
+// PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u8 regBwOpMode;
+ u8 regRRSR_RSC;
+
+ //return;
+
+ // Added it for 20/40 mhz switch time evaluation by guangan 070531
+ //u4Byte NowL, NowH;
+ //u8Byte BeginTime, EndTime;
+
+ /*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C() Switch to %s bandwidth\n", \
+ pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/
+
+ if(pHalData->rf_chip == RF_PSEUDO_11N)
+ {
+ //pHalData->SetBWModeInProgress= _FALSE;
+ return;
+ }
+
+ // There is no 40MHz mode in RF_8225.
+ if(pHalData->rf_chip==RF_8225)
+ return;
+
+ if(Adapter->bDriverStopped)
+ return;
+
+ // Added it for 20/40 mhz switch time evaluation by guangan 070531
+ //NowL = PlatformEFIORead4Byte(Adapter, TSFR);
+ //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);
+ //BeginTime = ((u8Byte)NowH << 32) + NowL;
+
+ //3//
+ //3//<1>Set MAC register
+ //3//
+ //Adapter->HalFunc.SetBWModeHandler();
+
+ regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
+ regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);
+ //regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(pu1Byte)®BwOpMode);
+
+ switch(pHalData->CurrentChannelBW)
+ {
+ case HT_CHANNEL_WIDTH_20:
+ regBwOpMode |= BW_OPMODE_20MHZ;
+ // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
+ rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
+ break;
+
+ case HT_CHANNEL_WIDTH_40:
+ regBwOpMode &= ~BW_OPMODE_20MHZ;
+ // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
+ rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
+
+ regRRSR_RSC = (regRRSR_RSC&0x90) |(pHalData->nCur40MhzPrimeSC<<5);
+ rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
+ break;
+
+ default:
+ /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C():
+ unknown Bandwidth: %#X\n",pHalData->CurrentChannelBW));*/
+ break;
+ }
+
+ //3//
+ //3//<2>Set PHY related register
+ //3//
+ switch(pHalData->CurrentChannelBW)
+ {
+ /* 20 MHz channel*/
+ case HT_CHANNEL_WIDTH_20:
+ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
+ PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
+ PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1);
+
+ break;
+
+
+ /* 40 MHz channel*/
+ case HT_CHANNEL_WIDTH_40:
+ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
+ PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
+
+ // Set Control channel to upper or lower. These settings are required only for 40MHz
+ PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
+ PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
+ PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0);
+
+ PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1);
+
+ break;
+
+
+
+ default:
+ /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): unknown Bandwidth: %#X\n"\
+ ,pHalData->CurrentChannelBW));*/
+ break;
+
+ }
+ //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
+
+ // Added it for 20/40 mhz switch time evaluation by guangan 070531
+ //NowL = PlatformEFIORead4Byte(Adapter, TSFR);
+ //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);
+ //EndTime = ((u8Byte)NowH << 32) + NowL;
+ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
+
+ //3<3>Set RF related register
+ switch(pHalData->rf_chip)
+ {
+ case RF_8225:
+ //PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
+ break;
+
+ case RF_8256:
+ // Please implement this function in Hal8190PciPhy8256.c
+ //PHY_SetRF8256Bandwidth(Adapter, pHalData->CurrentChannelBW);
+ break;
+
+ case RF_8258:
+ // Please implement this function in Hal8190PciPhy8258.c
+ // PHY_SetRF8258Bandwidth();
+ break;
+
+ case RF_PSEUDO_11N:
+ // Do Nothing
+ break;
+
+ case RF_6052:
+ rtl8192c_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW);
+ break;
+
+ default:
+ //RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
+ break;
+ }
+
+ //pHalData->SetBWModeInProgress= FALSE;
+
+ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("<==PHY_SetBWModeCallback8192C() \n" ));
+}
+
+
+ /*-----------------------------------------------------------------------------
+ * Function: SetBWMode8190Pci()
+ *
+ * Overview: This function is export to "HalCommon" moudule
+ *
+ * Input: PADAPTER Adapter
+ * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Note: We do not take j mode into consideration now
+ *---------------------------------------------------------------------------*/
+VOID
+PHY_SetBWMode8192C(
+ IN PADAPTER Adapter,
+ IN HT_CHANNEL_WIDTH Bandwidth, // 20M or 40M
+ IN unsigned char Offset // Upper, Lower, or Don't care
+)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ HT_CHANNEL_WIDTH tmpBW= pHalData->CurrentChannelBW;
+ // Modified it for 20/40 mhz switch by guangan 070531
+ //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
+
+ //return;
+
+ //if(pHalData->SwChnlInProgress)
+// if(pMgntInfo->bScanInProgress)
+// {
+// RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s Exit because bScanInProgress!\n",
+// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
+// return;
+// }
+
+// if(pHalData->SetBWModeInProgress)
+// {
+// // Modified it for 20/40 mhz switch by guangan 070531
+// RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s cancel last timer because SetBWModeInProgress!\n",
+// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
+// PlatformCancelTimer(Adapter, &pHalData->SetBWModeTimer);
+// //return;
+// }
+
+ //if(pHalData->SetBWModeInProgress)
+ // return;
+
+ //pHalData->SetBWModeInProgress= TRUE;
+
+ pHalData->CurrentChannelBW = Bandwidth;
+
+#if 0
+ if(Offset==HT_EXTCHNL_OFFSET_LOWER)
+ pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
+ else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
+ pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
+ else
+ pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
+#else
+ pHalData->nCur40MhzPrimeSC = Offset;
+#endif
+
+ if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
+ {
+
+ #if 0
+ //PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0);
+ #else
+ _PHY_SetBWMode92C(Adapter);
+ #endif
+
+ }
+ else
+ {
+ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n"));
+ //pHalData->SetBWModeInProgress= FALSE;
+ pHalData->CurrentChannelBW = tmpBW;
+ }
+
+}
+
+
+static void _PHY_SwChnl8192C(PADAPTER Adapter, u8 channel)
+{
+ u8 eRFPath;
+ u32 param1, param2;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ if ( Adapter->bNotifyChannelChange )
+ {
+ DBG_871X( "[%s] ch = %d\n", __FUNCTION__, channel );
+ }
+
+ //s1. pre common command - CmdID_SetTxPowerLevel
+ PHY_SetTxPowerLevel8192C(Adapter, channel);
+
+ //s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel
+ param1 = RF_CHNLBW;
+ param2 = channel;
+ for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
+ {
+ pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
+ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
+ }
+
+ if(channel >= 1 && channel <= 9)
+ {
+ //DBG_8192C("phy_SwitchRfSetting8723A REG_AFE_PLL_CTRL 0xF0FFFF83\n");
+ PHY_SetBBReg(Adapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF0FFFF83);
+ }
+ else if (channel >= 10 && channel <= 14)
+ {
+ //DBG_8192C("phy_SwitchRfSetting8723A REG_AFE_PLL_CTRL 0xF2FFFF83\n");
+ PHY_SetBBReg(Adapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF2FFFF83);
+ }
+ //s3. post common command - CmdID_End, None
+
+}
+
+VOID
+PHY_SwChnl8192C( // Call after initialization
+ IN PADAPTER Adapter,
+ IN u8 channel
+ )
+{
+ //PADAPTER Adapter = ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, _TRUE);
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u8 tmpchannel = pHalData->CurrentChannel;
+ BOOLEAN bResult = _TRUE;
+
+ if(pHalData->rf_chip == RF_PSEUDO_11N)
+ {
+ //pHalData->SwChnlInProgress=FALSE;
+ return; //return immediately if it is peudo-phy
+ }
+
+ //if(pHalData->SwChnlInProgress)
+ // return;
+
+ //if(pHalData->SetBWModeInProgress)
+ // return;
+
+ //--------------------------------------------
+ switch(pHalData->CurrentWirelessMode)
+ {
+ case WIRELESS_MODE_A:
+ case WIRELESS_MODE_N_5G:
+ //RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14"));
+ break;
+
+ case WIRELESS_MODE_B:
+ //RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14"));
+ break;
+
+ case WIRELESS_MODE_G:
+ case WIRELESS_MODE_N_24G:
+ //RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14"));
+ break;
+
+ default:
+ //RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode));
+ break;
+ }
+ //--------------------------------------------
+
+ //pHalData->SwChnlInProgress = TRUE;
+ if(channel == 0)
+ channel = 1;
+
+ pHalData->CurrentChannel=channel;
+
+ //pHalData->SwChnlStage=0;
+ //pHalData->SwChnlStep=0;
+
+ if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
+ {
+
+ #if 0
+ //PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0);
+ #else
+ _PHY_SwChnl8192C(Adapter, channel);
+ #endif
+
+ if(bResult)
+ {
+ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n"));
+ }
+ else
+ {
+ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n"));
+ //if(IS_HARDWARE_TYPE_8192SU(Adapter))
+ //{
+ // pHalData->SwChnlInProgress = FALSE;
+ pHalData->CurrentChannel = tmpchannel;
+ //}
+ }
+
+ }
+ else
+ {
+ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n"));
+ //if(IS_HARDWARE_TYPE_8192SU(Adapter))
+ //{
+ // pHalData->SwChnlInProgress = FALSE;
+ pHalData->CurrentChannel = tmpchannel;
+ //}
+ }
+}
+
+
+static BOOLEAN
+phy_SwChnlStepByStep(
+ IN PADAPTER Adapter,
+ IN u8 channel,
+ IN u8 *stage,
+ IN u8 *step,
+ OUT u32 *delay
+ )
+{
+#if 0
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
+ SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
+ u4Byte PreCommonCmdCnt;
+ SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
+ u4Byte PostCommonCmdCnt;
+ SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
+ u4Byte RfDependCmdCnt;
+ SwChnlCmd *CurrentCmd;
+ u1Byte eRFPath;
+ u4Byte RfTXPowerCtrl;
+ BOOLEAN bAdjRfTXPowerCtrl = _FALSE;
+
+
+ RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n"));
+#if(MP_DRIVER != 1)
+ RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
+#endif
+ RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
+
+ pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
+ RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
+
+ //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
+ //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
+ //{
+ // <1> Fill up pre common command.
+ PreCommonCmdCnt = 0;
+ phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
+ CmdID_SetTxPowerLevel, 0, 0, 0);
+ phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
+ CmdID_End, 0, 0, 0);
+
+ // <2> Fill up post common command.
+ PostCommonCmdCnt = 0;
+
+ phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
+ CmdID_End, 0, 0, 0);
+
+ // <3> Fill up RF dependent command.
+ RfDependCmdCnt = 0;
+ switch( pHalData->RFChipID )
+ {
+ case RF_8225:
+ RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
+ // 2008/09/04 MH Change channel.
+ if(channel==14) channel++;
+ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10);
+ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_End, 0, 0, 0);
+ break;
+
+ case RF_8256:
+ // TEST!! This is not the table for 8256!!
+ RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
+ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_RF_WriteReg, rRfChannel, channel, 10);
+ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_End, 0, 0, 0);
+ break;
+
+ case RF_6052:
+ RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
+ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
+ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
+ CmdID_End, 0, 0, 0);
+
+ break;
+
+ case RF_8258:
+ break;
+
+ // For FPGA two MAC verification
+ case RF_PSEUDO_11N:
+ return TRUE;
+ default:
+ RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
+ return FALSE;
+ break;
+ }
+
+
+ do{
+ switch(*stage)
+ {
+ case 0:
+ CurrentCmd=&PreCommonCmd[*step];
+ break;
+ case 1:
+ CurrentCmd=&RfDependCmd[*step];
+ break;
+ case 2:
+ CurrentCmd=&PostCommonCmd[*step];
+ break;
+ }
+
+ if(CurrentCmd->CmdID==CmdID_End)
+ {
+ if((*stage)==2)
+ {
+ return TRUE;
+ }
+ else
+ {
+ (*stage)++;
+ (*step)=0;
+ continue;
+ }
+ }
+
+ switch(CurrentCmd->CmdID)
+ {
+ case CmdID_SetTxPowerLevel:
+ PHY_SetTxPowerLevel8192C(Adapter,channel);
+ break;
+ case CmdID_WritePortUlong:
+ PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2);
+ break;
+ case CmdID_WritePortUshort:
+ PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2);
+ break;
+ case CmdID_WritePortUchar:
+ PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2);
+ break;
+ case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
+ for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
+ {
+#if 1
+ pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);
+ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
+#else
+ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));
+#endif
+ }
+ break;
+ }
+
+ break;
+ }while(TRUE);
+ //cosa }/*for(Number of RF paths)*/
+
+ (*delay)=CurrentCmd->msDelay;
+ (*step)++;
+ return FALSE;
+#endif
+ return _TRUE;
+}
+
+
+static BOOLEAN
+phy_SetSwChnlCmdArray(
+ SwChnlCmd* CmdTable,
+ u32 CmdTableIdx,
+ u32 CmdTableSz,
+ SwChnlCmdID CmdID,
+ u32 Para1,
+ u32 Para2,
+ u32 msDelay
+ )
+{
+ SwChnlCmd* pCmd;
+
+ if(CmdTable == NULL)
+ {
+ //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
+ return _FALSE;
+ }
+ if(CmdTableIdx >= CmdTableSz)
+ {
+ //RT_ASSERT(FALSE,
+ // ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n",
+ // CmdTableIdx, CmdTableSz));
+ return _FALSE;
+ }
+
+ pCmd = CmdTable + CmdTableIdx;
+ pCmd->CmdID = CmdID;
+ pCmd->Para1 = Para1;
+ pCmd->Para2 = Para2;
+ pCmd->msDelay = msDelay;
+
+ return _TRUE;
+}
+
+
+static void
+phy_FinishSwChnlNow( // We should not call this function directly
+ IN PADAPTER Adapter,
+ IN u8 channel
+ )
+{
+#if 0
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u32 delay;
+
+ while(!phy_SwChnlStepByStep(Adapter,channel,&pHalData->SwChnlStage,&pHalData->SwChnlStep,&delay))
+ {
+ if(delay>0)
+ rtw_mdelay_os(delay);
+ }
+#endif
+}
+
+
+
+//
+// Description:
+// Switch channel synchronously. Called by SwChnlByDelayHandler.
+//
+// Implemented by Bruce, 2008-02-14.
+// The following procedure is operted according to SwChanlCallback8190Pci().
+// However, this procedure is performed synchronously which should be running under
+// passive level.
+//
+VOID
+PHY_SwChnlPhy8192C( // Only called during initialize
+ IN PADAPTER Adapter,
+ IN u8 channel
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ //RT_TRACE(COMP_SCAN | COMP_RM, DBG_LOUD, ("==>PHY_SwChnlPhy8192S(), switch from channel %d to channel %d.\n", pHalData->CurrentChannel, channel));
+
+ // Cannot IO.
+ //if(RT_CANNOT_IO(Adapter))
+ // return;
+
+ // Channel Switching is in progress.
+ //if(pHalData->SwChnlInProgress)
+ // return;
+
+ //return immediately if it is peudo-phy
+ if(pHalData->rf_chip == RF_PSEUDO_11N)
+ {
+ //pHalData->SwChnlInProgress=FALSE;
+ return;
+ }
+
+ //pHalData->SwChnlInProgress = TRUE;
+ if( channel == 0)
+ channel = 1;
+
+ pHalData->CurrentChannel=channel;
+
+ //pHalData->SwChnlStage = 0;
+ //pHalData->SwChnlStep = 0;
+
+ phy_FinishSwChnlNow(Adapter,channel);
+
+ //pHalData->SwChnlInProgress = FALSE;
+}
+
+
+//
+// Description:
+// Configure H/W functionality to enable/disable Monitor mode.
+// Note, because we possibly need to configure BB and RF in this function,
+// so caller should in PASSIVE_LEVEL. 080118, by rcnjko.
+//
+VOID
+PHY_SetMonitorMode8192C(
+ IN PADAPTER pAdapter,
+ IN BOOLEAN bEnableMonitorMode
+ )
+{
+#if 0
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ BOOLEAN bFilterOutNonAssociatedBSSID = FALSE;
+
+ //2 Note: we may need to stop antenna diversity.
+ if(bEnableMonitorMode)
+ {
+ bFilterOutNonAssociatedBSSID = FALSE;
+ RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));
+
+ pHalData->bInMonitorMode = TRUE;
+ pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE);
+ rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
+ }
+ else
+ {
+ bFilterOutNonAssociatedBSSID = TRUE;
+ RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));
+
+ pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE);
+ pHalData->bInMonitorMode = FALSE;
+ rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
+ }
+#endif
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Function: PHYCheckIsLegalRfPath8190Pci()
+ *
+ * Overview: Check different RF type to execute legal judgement. If RF Path is illegal
+ * We will return false.
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 11/15/2007 MHC Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+BOOLEAN
+PHY_CheckIsLegalRfPath8192C(
+ IN PADAPTER pAdapter,
+ IN u32 eRFPath)
+{
+// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+ BOOLEAN rtValue = _TRUE;
+
+ // NOt check RF Path now.!
+#if 0
+ if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
+ {
+ rtValue = FALSE;
+ }
+ if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
+ {
+
+ }
+#endif
+ return rtValue;
+
+} /* PHY_CheckIsLegalRfPath8192C */
+
+static VOID _PHY_SetRFPathSwitch(
+ IN PADAPTER pAdapter,
+ IN BOOLEAN bMain,
+ IN BOOLEAN is2T
+ )
+{
+ u8 u1bTmp;
+
+ if(!pAdapter->hw_init_completed)
+ {
+ u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7;
+ rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp);
+ //PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
+ }
+
+ if(is2T)
+ {
+ if(bMain)
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A
+ else
+ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT
+ }
+ else
+ {
+
+ if(bMain)
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2); //Main
+ else
+ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1); //Aux
+ }
+
+}
+
+//return value TRUE => Main; FALSE => Aux
+
+static BOOLEAN _PHY_QueryRFPathSwitch(
+ IN PADAPTER pAdapter,
+ IN BOOLEAN is2T
+ )
+{
+// if(is2T)
+// return _TRUE;
+
+ if(!pAdapter->hw_init_completed)
+ {
+ PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
+ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
+ }
+
+ if(is2T)
+ {
+ if(PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)
+ return _TRUE;
+ else
+ return _FALSE;
+ }
+ else
+ {
+ if(PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02)
+ return _TRUE;
+ else
+ return _FALSE;
+ }
+}
+
+
+static VOID
+_PHY_DumpRFReg(IN PADAPTER pAdapter)
+{
+ u32 rfRegValue,rfRegOffset;
+
+ //RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n"));
+
+ for(rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){
+ rfRegValue = PHY_QueryRFReg(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord);
+ //RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue));
+ }
+ //RTPRINT(FINIT, INIT_RF, ("<===== PHY_DumpRFReg()\n"));
+}
+
+
+VOID rtl8192c_PHY_SetRFPathSwitch(
+ IN PADAPTER pAdapter,
+ IN BOOLEAN bMain
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
+
+#if DISABLE_BB_RF
+ return;
+#endif
+
+ if(IS_92C_SERIAL( pHalData->VersionID)){
+ _PHY_SetRFPathSwitch(pAdapter, bMain, _TRUE);
+ }
+ else{
+ // For 88C 1T1R
+ _PHY_SetRFPathSwitch(pAdapter, bMain, _FALSE);
+ }
+}
+
+//
+// Move from phycfg.c to gen.c to be code independent later
+//
+//-------------------------Move to other DIR later----------------------------*/
+#ifdef CONFIG_USB_HCI
+
+//
+// Description:
+// To dump all Tx FIFO LLT related link-list table.
+// Added by Roger, 2009.03.10.
+//
+VOID
+DumpBBDbgPort_92CU(
+ IN PADAPTER Adapter
+ )
+{
+
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"));
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("BaseBand Debug Ports:\n"));
+
+ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0000);
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
+
+ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0803);
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
+
+ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0a06);
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
+
+ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0007);
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
+
+ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);
+ PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x000f0000);
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
+
+ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);
+ PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x00150000);
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
+
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x800, PHY_QueryBBReg(Adapter, 0x0800, bMaskDWord)));
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x900, PHY_QueryBBReg(Adapter, 0x0900, bMaskDWord)));
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa00, PHY_QueryBBReg(Adapter, 0x0a00, bMaskDWord)));
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa54, PHY_QueryBBReg(Adapter, 0x0a54, bMaskDWord)));
+ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa58, PHY_QueryBBReg(Adapter, 0x0a58, bMaskDWord)));
+
+}
+#endif
+
diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_rf6052.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_rf6052.c index c86782f695e6..b6449371f5a7 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_rf6052.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_rf6052.c @@ -1,985 +1,985 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -/****************************************************************************** - * - * - * Module: rtl8192c_rf6052.c ( Source C File) - * - * Note: Provide RF 6052 series relative API. - * - * Function: - * - * Export: - * - * Abbrev: - * - * History: - * Data Who Remark - * - * 09/25/2008 MHC Create initial version. - * 11/05/2008 MHC Add API for tw power setting. - * - * -******************************************************************************/ - -#define _RTL8723A_RF6052_C_ - -#include <drv_conf.h> -#include <osdep_service.h> -#include <drv_types.h> -#include <rtw_byteorder.h> - -#include <rtl8723a_hal.h> - -/*---------------------------Define Local Constant---------------------------*/ -// Define local structure for debug!!!!! -typedef struct RF_Shadow_Compare_Map { - // Shadow register value - u32 Value; - // Compare or not flag - u8 Compare; - // Record If it had ever modified unpredicted - u8 ErrorOrNot; - // Recorver Flag - u8 Recorver; - // - u8 Driver_Write; -}RF_SHADOW_T; -/*---------------------------Define Local Constant---------------------------*/ - - -/*------------------------Define global variable-----------------------------*/ -/*------------------------Define global variable-----------------------------*/ - - -/*------------------------Define local variable------------------------------*/ -// 2008/11/20 MH For Debug only, RF -//static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0}; -static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; -/*------------------------Define local variable------------------------------*/ - - -/*----------------------------------------------------------------------------- - * Function: RF_ChangeTxPath - * - * Overview: For RL6052, we must change some RF settign for 1T or 2T. - * - * Input: u2Byte DataRate // 0x80-8f, 0x90-9f - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 09/25/2008 MHC Create Version 0. - * Firmwaer support the utility later. - * - *---------------------------------------------------------------------------*/ -void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter, - IN u16 DataRate) -{ -// We do not support gain table change inACUT now !!!! Delete later !!! -#if 0//(RTL92SE_FPGA_VERIFY == 0) - static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T - static u4Byte tx_gain_tbl1[6] - = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100}; - static u4Byte tx_gain_tbl2[6] - = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030}; - u1Byte i; - - if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7) - { - // Set TX SYNC power G2G3 loop filter - PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, - RF_TXPA_G2, bRFRegOffsetMask, 0x0f000); - PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, - RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1); - - // Change TX AGC gain table - for (i = 0; i < 6; i++) - PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, - RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]); - - // Set PA to high value - PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, - RF_TXPA_G2, bRFRegOffsetMask, 0x01e39); - } - else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8) - { - // Set TX SYNC power G2G3 loop filter - PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, - RF_TXPA_G2, bRFRegOffsetMask, 0x04440); - PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, - RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1); - - // Change TX AGC gain table - for (i = 0; i < 6; i++) - PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, - RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl2[i]); - - // Set PA low gain - PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A, - RF_TXPA_G2, bRFRegOffsetMask, 0x01e19); - } -#endif - -} /* RF_ChangeTxPath */ - - -/*----------------------------------------------------------------------------- - * Function: PHY_RF6052SetBandwidth() - * - * Overview: This function is called by SetBWModeCallback8190Pci() only - * - * Input: PADAPTER Adapter - * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M - * - * Output: NONE - * - * Return: NONE - * - * Note: For RF type 0222D - *---------------------------------------------------------------------------*/ -VOID -rtl8192c_PHY_RF6052SetBandwidth( - IN PADAPTER Adapter, - IN HT_CHANNEL_WIDTH Bandwidth) //20M or 40M -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - switch(Bandwidth) - { - case HT_CHANNEL_WIDTH_20: - pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400); - PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); - break; - - case HT_CHANNEL_WIDTH_40: - pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff)); - PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); - break; - - default: - //RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); - break; - } - -} - - -/*----------------------------------------------------------------------------- - * Function: PHY_RF6052SetCckTxPower - * - * Overview: - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 11/05/2008 MHC Simulate 8192series.. - * - *---------------------------------------------------------------------------*/ - -VOID -rtl8192c_PHY_RF6052SetCckTxPower( - IN PADAPTER Adapter, - IN u8* pPowerlevel) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; - struct dm_priv *pdmpriv = &pHalData->dmpriv; - struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; - //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; - u32 TxAGC[2]={0, 0}, tmpval=0; - BOOLEAN TurboScanOff = _FALSE; - u8 idx1, idx2; - u8* ptr; - - // 2010/10/18 MH Accorsing to SD3 eechou's suggestion, we need to disable turbo scan for RU. - // Otherwise, external PA will be broken if power index > 0x20. -#ifdef CONFIG_USB_HCI - if (pHalData->EEPROMRegulatory != 0 || pHalData->ExternalPA) -#else - if (pHalData->EEPROMRegulatory != 0) -#endif - { - //DbgPrint("TurboScanOff=1 EEPROMRegulatory=%d ExternalPA=%d\n", pHalData->EEPROMRegulatory, pHalData->ExternalPA); - TurboScanOff = _TRUE; - } - - if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS) - { - TxAGC[RF_PATH_A] = 0x3f3f3f3f; - TxAGC[RF_PATH_B] = 0x3f3f3f3f; - - TurboScanOff = _TRUE;//disable turbo scan - - if(TurboScanOff) - { - for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) - { - TxAGC[idx1] = - pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | - (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); -#ifdef CONFIG_USB_HCI - // 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. - if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA) - TxAGC[idx1] = 0x20; -#endif - } - } - } - else - { -// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. -// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. -// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. - if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) - { - TxAGC[RF_PATH_A] = 0x10101010; - TxAGC[RF_PATH_B] = 0x10101010; - } - else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) - { - TxAGC[RF_PATH_A] = 0x00000000; - TxAGC[RF_PATH_B] = 0x00000000; - } - else - { - for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) - { - TxAGC[idx1] = - pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | - (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); - } - - if(pHalData->EEPROMRegulatory==0) - { - tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) + - (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8); - TxAGC[RF_PATH_A] += tmpval; - - tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) + - (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24); - TxAGC[RF_PATH_B] += tmpval; - } - } - } - - for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++) - { - ptr = (u8*)(&(TxAGC[idx1])); - for(idx2=0; idx2<4; idx2++) - { - if(*ptr > RF6052_MAX_TX_PWR) - *ptr = RF6052_MAX_TX_PWR; - ptr++; - } - } - - // rf-A cck tx power - tmpval = TxAGC[RF_PATH_A]&0xff; - PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); - //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32)); - tmpval = TxAGC[RF_PATH_A]>>8; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); - //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11)); - - // rf-B cck tx power - tmpval = TxAGC[RF_PATH_B]>>24; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); - //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11)); - tmpval = TxAGC[RF_PATH_B]&0x00ffffff; - PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); - //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", - // tmpval, rTxAGC_B_CCK1_55_Mcs32)); - -} /* PHY_RF6052SetCckTxPower */ - -// -// powerbase0 for OFDM rates -// powerbase1 for HT MCS rates -// -static void getPowerBase( - IN PADAPTER Adapter, - IN u8* pPowerLevel, - IN u8 Channel, - IN OUT u32* OfdmBase, - IN OUT u32* MCSBase - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u32 powerBase0, powerBase1; - u8 Legacy_pwrdiff=0; - s8 HT20_pwrdiff=0; - u8 i, powerlevel[2]; - - for(i=0; i<2; i++) - { - powerlevel[i] = pPowerLevel[i]; - Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1]; - powerBase0 = powerlevel[i] + Legacy_pwrdiff; - - powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; - *(OfdmBase+i) = powerBase0; - //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i))); - } - - for(i=0; i<2; i++) - { - //Check HT20 to HT40 diff - if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) - { - HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1]; - powerlevel[i] += HT20_pwrdiff; - } - powerBase1 = powerlevel[i]; - powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; - *(MCSBase+i) = powerBase1; - //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i))); - } -} - -static void getTxPowerWriteValByRegulatory( - IN PADAPTER Adapter, - IN u8 Channel, - IN u8 index, - IN u32* powerBase0, - IN u32* powerBase1, - OUT u32* pOutWriteVal - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct dm_priv *pdmpriv = &pHalData->dmpriv; - u8 i, chnlGroup, pwr_diff_limit[4]; - u32 writeVal, customer_limit, rf; - - // - // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate - // - for(rf=0; rf<2; rf++) - { - switch(pHalData->EEPROMRegulatory) - { - case 0: // Realtek better performance - // increase power diff defined by Realtek for large power - chnlGroup = 0; - //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", - // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); - writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + - ((index<2)?powerBase0[rf]:powerBase1[rf]); - //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); - break; - case 1: // Realtek regulatory - // increase power diff defined by Realtek for regulatory - { - if(pHalData->pwrGroupCnt == 1) - chnlGroup = 0; - if(pHalData->pwrGroupCnt >= 3) - { - if(Channel <= 3) - chnlGroup = 0; - else if(Channel >= 4 && Channel <= 9) - chnlGroup = 1; - else if(Channel > 9) - chnlGroup = 2; - - if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) - chnlGroup++; - else - chnlGroup+=4; - } - //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", - //chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); - writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + - ((index<2)?powerBase0[rf]:powerBase1[rf]); - //RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); - } - break; - case 2: // Better regulatory - // don't increase any power diff - writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]); - //RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); - break; - case 3: // Customer defined power diff. - // increase power diff defined by customer. - chnlGroup = 0; - //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", - // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); - - if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) - { - //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n", - // ((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1])); - } - else - { - //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n", - // ((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1])); - } - for (i=0; i<4; i++) - { - pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8)); - if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) - { - if(pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1]) - pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1]; - } - else - { - if(pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1]) - pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1]; - } - } - customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) | - (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]); - //RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit)); - - writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]); - //RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal)); - break; - default: - chnlGroup = 0; - writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + - ((index<2)?powerBase0[rf]:powerBase1[rf]); - //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); - break; - } - -// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. -// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. -// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. - - if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) - writeVal = 0x14141414; - else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) - writeVal = 0x00000000; - - - // 20100628 Joseph: High power mode for BT-Coexist mechanism. - // This mechanism is only applied when Driver-Highpower-Mechanism is OFF. - if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1) - { - //RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n")); - writeVal = writeVal - 0x06060606; - } - else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2) - { - //RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n")); - writeVal = writeVal; - } - *(pOutWriteVal+rf) = writeVal; - } -} - -static void writeOFDMPowerReg( - IN PADAPTER Adapter, - IN u8 index, - IN u32* pValue - ) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24, - rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04, - rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12}; - u16 RegOffset_B[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24, - rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04, - rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12}; - u8 i, rf, pwr_val[4]; - u32 writeVal; - u16 RegOffset; - - for(rf=0; rf<2; rf++) - { - writeVal = pValue[rf]; - for(i=0; i<4; i++) - { - pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); - if (pwr_val[i] > RF6052_MAX_TX_PWR) - pwr_val[i] = RF6052_MAX_TX_PWR; - } - writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0]; - - if(rf == 0) - RegOffset = RegOffset_A[index]; - else - RegOffset = RegOffset_B[index]; - - PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal); - //RTPRINT(FPHY, PHY_TXPWR, ("Set 0x%x = %08x\n", RegOffset, writeVal)); - - // 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. - if(((pHalData->rf_type == RF_2T2R) && - (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))|| - ((pHalData->rf_type != RF_2T2R) && - (RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) ) - { - writeVal = pwr_val[3]; - if(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04) - RegOffset = 0xc90; - if(RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04) - RegOffset = 0xc98; - for(i=0; i<3; i++) - { - if(i!=2) - writeVal = (writeVal>8)?(writeVal-8):0; - else - writeVal = (writeVal>6)?(writeVal-6):0; - rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal); - } - } - } -} -/*----------------------------------------------------------------------------- - * Function: PHY_RF6052SetOFDMTxPower - * - * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for - * different channel and read original value in TX power register area from - * 0xe00. We increase offset and original value to be correct tx pwr. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 11/05/2008 MHC Simulate 8192 series method. - * 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to - * A/B pwr difference or legacy/HT pwr diff. - * 2. We concern with path B legacy/HT OFDM difference. - * 01/22/2009 MHC Support new EPRO format from SD3. - * - *---------------------------------------------------------------------------*/ -VOID -rtl8192c_PHY_RF6052SetOFDMTxPower( - IN PADAPTER Adapter, - IN u8* pPowerLevel, - IN u8 Channel) -{ - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - u32 writeVal[2], powerBase0[2], powerBase1[2]; - u8 index = 0; - - getPowerBase(Adapter, pPowerLevel, Channel, &powerBase0[0], &powerBase1[0]); - - for(index=0; index<6; index++) - { - getTxPowerWriteValByRegulatory(Adapter, Channel, index, - &powerBase0[0], &powerBase1[0], &writeVal[0]); - - writeOFDMPowerReg(Adapter, index, &writeVal[0]); - } - -} - - -static VOID -phy_RF6052_Config_HardCode( - IN PADAPTER Adapter - ) -{ - - // Set Default Bandwidth to 20M - //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20); - - // TODO: Set Default Channel to channel one for RTL8225 - -} - -static int -phy_RF6052_Config_ParaFile( - IN PADAPTER Adapter - ) -{ - u32 u4RegValue; - u8 eRFPath; - BB_REGISTER_DEFINITION_T *pPhyReg; - - int rtStatus = _SUCCESS; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - - static char sz8723RadioAFile[] = RTL8723_PHY_RADIO_A; - static char sz8723RadioBFile[] = RTL8723_PHY_RADIO_B; - char *pszRadioAFile, *pszRadioBFile; - - - pszRadioAFile = sz8723RadioAFile; - pszRadioBFile = sz8723RadioBFile; - - - //3//----------------------------------------------------------------- - //3// <2> Initialize RF - //3//----------------------------------------------------------------- - //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) - for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++) - { - - pPhyReg = &pHalData->PHYRegDef[eRFPath]; - - /*----Store original RFENV control type----*/ - switch(eRFPath) - { - case RF_PATH_A: - case RF_PATH_C: - u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); - break; - case RF_PATH_B : - case RF_PATH_D: - u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); - break; - } - - /*----Set RF_ENV enable----*/ - PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); - rtw_udelay_os(1);//PlatformStallExecution(1); - - /*----Set RF_ENV output high----*/ - PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); - rtw_udelay_os(1);//PlatformStallExecution(1); - - /* Set bit number of Address and Data for RF register */ - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 - rtw_udelay_os(1);//PlatformStallExecution(1); - - PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 - rtw_udelay_os(1);//PlatformStallExecution(1); - - /*----Initialize RF fom connfiguration file----*/ - switch(eRFPath) - { - case RF_PATH_A: -#ifdef CONFIG_EMBEDDED_FWIMG - #ifdef CONFIG_PHY_SETTING_WITH_ODM - if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath)) - rtStatus= _FAIL; - #else - rtStatus= rtl8723a_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath); - #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM -#else - rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath); -#endif//#ifdef CONFIG_EMBEDDED_FWIMG - break; - case RF_PATH_B: -#ifdef CONFIG_EMBEDDED_FWIMG - #ifdef CONFIG_PHY_SETTING_WITH_ODM - if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath)) - rtStatus= _FAIL; - #else - rtStatus = rtl8723a_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath); - #endif -#else - rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath); -#endif - break; - case RF_PATH_C: - break; - case RF_PATH_D: - break; - } - - /*----Restore RFENV control type----*/; - switch(eRFPath) - { - case RF_PATH_A: - case RF_PATH_C: - PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); - break; - case RF_PATH_B : - case RF_PATH_D: - PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); - break; - } - - if(rtStatus != _SUCCESS){ - //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); - goto phy_RF6052_Config_ParaFile_Fail; - } - - } - - //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); - return rtStatus; - -phy_RF6052_Config_ParaFile_Fail: - return rtStatus; -} - - -int -PHY_RF6052_Config8723A( - IN PADAPTER Adapter) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - int rtStatus = _SUCCESS; - - // - // Initialize general global value - // - // TODO: Extend RF_PATH_C and RF_PATH_D in the future - if(pHalData->rf_type == RF_1T1R) - pHalData->NumTotalRFPath = 1; - else - pHalData->NumTotalRFPath = 2; - - // - // Config BB and RF - // - rtStatus = phy_RF6052_Config_ParaFile(Adapter); - return rtStatus; - -} - - -// -// ==> RF shadow Operation API Code Section!!! -// -/*----------------------------------------------------------------------------- - * Function: PHY_RFShadowRead - * PHY_RFShadowWrite - * PHY_RFShadowCompare - * PHY_RFShadowRecorver - * PHY_RFShadowCompareAll - * PHY_RFShadowRecorverAll - * PHY_RFShadowCompareFlagSet - * PHY_RFShadowRecorverFlagSet - * - * Overview: When we set RF register, we must write shadow at first. - * When we are running, we must compare shadow abd locate error addr. - * Decide to recorver or not. - * - * Input: NONE - * - * Output: NONE - * - * Return: NONE - * - * Revised History: - * When Who Remark - * 11/20/2008 MHC Create Version 0. - * - *---------------------------------------------------------------------------*/ -u32 -PHY_RFShadowRead( - IN PADAPTER Adapter, - IN RF_RADIO_PATH_E eRFPath, - IN u32 Offset) -{ - return RF_Shadow[eRFPath][Offset].Value; - -} /* PHY_RFShadowRead */ - - -VOID -PHY_RFShadowWrite( - IN PADAPTER Adapter, - IN RF_RADIO_PATH_E eRFPath, - IN u32 Offset, - IN u32 Data) -{ - RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask); - RF_Shadow[eRFPath][Offset].Driver_Write = _TRUE; - -} /* PHY_RFShadowWrite */ - - -BOOLEAN -PHY_RFShadowCompare( - IN PADAPTER Adapter, - IN RF_RADIO_PATH_E eRFPath, - IN u32 Offset) -{ - u32 reg; - // Check if we need to check the register - if (RF_Shadow[eRFPath][Offset].Compare == _TRUE) - { - reg = PHY_QueryRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask); - // Compare shadow and real rf register for 20bits!! - if (RF_Shadow[eRFPath][Offset].Value != reg) - { - // Locate error position. - RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE; - //RT_TRACE(COMP_INIT, DBG_LOUD, - //("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n", - //eRFPath, Offset, reg)); - } - return RF_Shadow[eRFPath][Offset].ErrorOrNot ; - } - return _FALSE; -} /* PHY_RFShadowCompare */ - - -VOID -PHY_RFShadowRecorver( - IN PADAPTER Adapter, - IN RF_RADIO_PATH_E eRFPath, - IN u32 Offset) -{ - // Check if the address is error - if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE) - { - // Check if we need to recorver the register. - if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE) - { - PHY_SetRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask, - RF_Shadow[eRFPath][Offset].Value); - //RT_TRACE(COMP_INIT, DBG_LOUD, - //("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx", - //eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value)); - } - } - -} /* PHY_RFShadowRecorver */ - - -VOID -PHY_RFShadowCompareAll( - IN PADAPTER Adapter) -{ - u32 eRFPath; - u32 Offset; - - for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) - { - for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) - { - PHY_RFShadowCompare(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset); - } - } - -} /* PHY_RFShadowCompareAll */ - - -VOID -PHY_RFShadowRecorverAll( - IN PADAPTER Adapter) -{ - u32 eRFPath; - u32 Offset; - - for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) - { - for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) - { - PHY_RFShadowRecorver(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset); - } - } - -} /* PHY_RFShadowRecorverAll */ - - -VOID -PHY_RFShadowCompareFlagSet( - IN PADAPTER Adapter, - IN RF_RADIO_PATH_E eRFPath, - IN u32 Offset, - IN u8 Type) -{ - // Set True or False!!! - RF_Shadow[eRFPath][Offset].Compare = Type; - -} /* PHY_RFShadowCompareFlagSet */ - - -VOID -PHY_RFShadowRecorverFlagSet( - IN PADAPTER Adapter, - IN RF_RADIO_PATH_E eRFPath, - IN u32 Offset, - IN u8 Type) -{ - // Set True or False!!! - RF_Shadow[eRFPath][Offset].Recorver= Type; - -} /* PHY_RFShadowRecorverFlagSet */ - - -VOID -PHY_RFShadowCompareFlagSetAll( - IN PADAPTER Adapter) -{ - u32 eRFPath; - u32 Offset; - - for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) - { - for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) - { - // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! - if (Offset != 0x26 && Offset != 0x27) - PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _FALSE); - else - PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _TRUE); - } - } - -} /* PHY_RFShadowCompareFlagSetAll */ - - -VOID -PHY_RFShadowRecorverFlagSetAll( - IN PADAPTER Adapter) -{ - u32 eRFPath; - u32 Offset; - - for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) - { - for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) - { - // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! - if (Offset != 0x26 && Offset != 0x27) - PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _FALSE); - else - PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _TRUE); - } - } - -} /* PHY_RFShadowCompareFlagSetAll */ - -VOID -PHY_RFShadowRefresh( - IN PADAPTER Adapter) -{ - u32 eRFPath; - u32 Offset; - - for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) - { - for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) - { - RF_Shadow[eRFPath][Offset].Value = 0; - RF_Shadow[eRFPath][Offset].Compare = _FALSE; - RF_Shadow[eRFPath][Offset].Recorver = _FALSE; - RF_Shadow[eRFPath][Offset].ErrorOrNot = _FALSE; - RF_Shadow[eRFPath][Offset].Driver_Write = _FALSE; - } - } - -} /* PHY_RFShadowRead */ - -/* End of HalRf6052.c */ - +/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ *
+ * Module: rtl8192c_rf6052.c ( Source C File)
+ *
+ * Note: Provide RF 6052 series relative API.
+ *
+ * Function:
+ *
+ * Export:
+ *
+ * Abbrev:
+ *
+ * History:
+ * Data Who Remark
+ *
+ * 09/25/2008 MHC Create initial version.
+ * 11/05/2008 MHC Add API for tw power setting.
+ *
+ *
+******************************************************************************/
+
+#define _RTL8723A_RF6052_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtw_byteorder.h>
+
+#include <rtl8723a_hal.h>
+
+/*---------------------------Define Local Constant---------------------------*/
+// Define local structure for debug!!!!!
+typedef struct RF_Shadow_Compare_Map {
+ // Shadow register value
+ u32 Value;
+ // Compare or not flag
+ u8 Compare;
+ // Record If it had ever modified unpredicted
+ u8 ErrorOrNot;
+ // Recorver Flag
+ u8 Recorver;
+ //
+ u8 Driver_Write;
+}RF_SHADOW_T;
+/*---------------------------Define Local Constant---------------------------*/
+
+
+/*------------------------Define global variable-----------------------------*/
+/*------------------------Define global variable-----------------------------*/
+
+
+/*------------------------Define local variable------------------------------*/
+// 2008/11/20 MH For Debug only, RF
+//static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0};
+static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];
+/*------------------------Define local variable------------------------------*/
+
+
+/*-----------------------------------------------------------------------------
+ * Function: RF_ChangeTxPath
+ *
+ * Overview: For RL6052, we must change some RF settign for 1T or 2T.
+ *
+ * Input: u2Byte DataRate // 0x80-8f, 0x90-9f
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 09/25/2008 MHC Create Version 0.
+ * Firmwaer support the utility later.
+ *
+ *---------------------------------------------------------------------------*/
+void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter,
+ IN u16 DataRate)
+{
+// We do not support gain table change inACUT now !!!! Delete later !!!
+#if 0//(RTL92SE_FPGA_VERIFY == 0)
+ static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T
+ static u4Byte tx_gain_tbl1[6]
+ = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100};
+ static u4Byte tx_gain_tbl2[6]
+ = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030};
+ u1Byte i;
+
+ if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7)
+ {
+ // Set TX SYNC power G2G3 loop filter
+ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
+ RF_TXPA_G2, bRFRegOffsetMask, 0x0f000);
+ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
+ RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1);
+
+ // Change TX AGC gain table
+ for (i = 0; i < 6; i++)
+ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
+ RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]);
+
+ // Set PA to high value
+ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
+ RF_TXPA_G2, bRFRegOffsetMask, 0x01e39);
+ }
+ else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8)
+ {
+ // Set TX SYNC power G2G3 loop filter
+ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
+ RF_TXPA_G2, bRFRegOffsetMask, 0x04440);
+ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
+ RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1);
+
+ // Change TX AGC gain table
+ for (i = 0; i < 6; i++)
+ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
+ RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl2[i]);
+
+ // Set PA low gain
+ PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)RF_PATH_A,
+ RF_TXPA_G2, bRFRegOffsetMask, 0x01e19);
+ }
+#endif
+
+} /* RF_ChangeTxPath */
+
+
+/*-----------------------------------------------------------------------------
+ * Function: PHY_RF6052SetBandwidth()
+ *
+ * Overview: This function is called by SetBWModeCallback8190Pci() only
+ *
+ * Input: PADAPTER Adapter
+ * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Note: For RF type 0222D
+ *---------------------------------------------------------------------------*/
+VOID
+rtl8192c_PHY_RF6052SetBandwidth(
+ IN PADAPTER Adapter,
+ IN HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ switch(Bandwidth)
+ {
+ case HT_CHANNEL_WIDTH_20:
+ pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400);
+ PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
+ break;
+
+ case HT_CHANNEL_WIDTH_40:
+ pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff));
+ PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]);
+ break;
+
+ default:
+ //RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth ));
+ break;
+ }
+
+}
+
+
+/*-----------------------------------------------------------------------------
+ * Function: PHY_RF6052SetCckTxPower
+ *
+ * Overview:
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 11/05/2008 MHC Simulate 8192series..
+ *
+ *---------------------------------------------------------------------------*/
+
+VOID
+rtl8192c_PHY_RF6052SetCckTxPower(
+ IN PADAPTER Adapter,
+ IN u8* pPowerlevel)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv;
+ struct dm_priv *pdmpriv = &pHalData->dmpriv;
+ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
+ //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
+ u32 TxAGC[2]={0, 0}, tmpval=0;
+ BOOLEAN TurboScanOff = _FALSE;
+ u8 idx1, idx2;
+ u8* ptr;
+
+ // 2010/10/18 MH Accorsing to SD3 eechou's suggestion, we need to disable turbo scan for RU.
+ // Otherwise, external PA will be broken if power index > 0x20.
+#ifdef CONFIG_USB_HCI
+ if (pHalData->EEPROMRegulatory != 0 || pHalData->ExternalPA)
+#else
+ if (pHalData->EEPROMRegulatory != 0)
+#endif
+ {
+ //DbgPrint("TurboScanOff=1 EEPROMRegulatory=%d ExternalPA=%d\n", pHalData->EEPROMRegulatory, pHalData->ExternalPA);
+ TurboScanOff = _TRUE;
+ }
+
+ if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
+ {
+ TxAGC[RF_PATH_A] = 0x3f3f3f3f;
+ TxAGC[RF_PATH_B] = 0x3f3f3f3f;
+
+ TurboScanOff = _TRUE;//disable turbo scan
+
+ if(TurboScanOff)
+ {
+ for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
+ {
+ TxAGC[idx1] =
+ pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
+ (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
+#ifdef CONFIG_USB_HCI
+ // 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20.
+ if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA)
+ TxAGC[idx1] = 0x20;
+#endif
+ }
+ }
+ }
+ else
+ {
+// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
+// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
+// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
+ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
+ {
+ TxAGC[RF_PATH_A] = 0x10101010;
+ TxAGC[RF_PATH_B] = 0x10101010;
+ }
+ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
+ {
+ TxAGC[RF_PATH_A] = 0x00000000;
+ TxAGC[RF_PATH_B] = 0x00000000;
+ }
+ else
+ {
+ for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
+ {
+ TxAGC[idx1] =
+ pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) |
+ (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24);
+ }
+
+ if(pHalData->EEPROMRegulatory==0)
+ {
+ tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) +
+ (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8);
+ TxAGC[RF_PATH_A] += tmpval;
+
+ tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) +
+ (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24);
+ TxAGC[RF_PATH_B] += tmpval;
+ }
+ }
+ }
+
+ for(idx1=RF_PATH_A; idx1<=RF_PATH_B; idx1++)
+ {
+ ptr = (u8*)(&(TxAGC[idx1]));
+ for(idx2=0; idx2<4; idx2++)
+ {
+ if(*ptr > RF6052_MAX_TX_PWR)
+ *ptr = RF6052_MAX_TX_PWR;
+ ptr++;
+ }
+ }
+
+ // rf-A cck tx power
+ tmpval = TxAGC[RF_PATH_A]&0xff;
+ PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
+ //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32));
+ tmpval = TxAGC[RF_PATH_A]>>8;
+ PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
+ //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
+
+ // rf-B cck tx power
+ tmpval = TxAGC[RF_PATH_B]>>24;
+ PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
+ //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11));
+ tmpval = TxAGC[RF_PATH_B]&0x00ffffff;
+ PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
+ //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
+ // tmpval, rTxAGC_B_CCK1_55_Mcs32));
+
+} /* PHY_RF6052SetCckTxPower */
+
+//
+// powerbase0 for OFDM rates
+// powerbase1 for HT MCS rates
+//
+static void getPowerBase(
+ IN PADAPTER Adapter,
+ IN u8* pPowerLevel,
+ IN u8 Channel,
+ IN OUT u32* OfdmBase,
+ IN OUT u32* MCSBase
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u32 powerBase0, powerBase1;
+ u8 Legacy_pwrdiff=0;
+ s8 HT20_pwrdiff=0;
+ u8 i, powerlevel[2];
+
+ for(i=0; i<2; i++)
+ {
+ powerlevel[i] = pPowerLevel[i];
+ Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1];
+ powerBase0 = powerlevel[i] + Legacy_pwrdiff;
+
+ powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
+ *(OfdmBase+i) = powerBase0;
+ //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i)));
+ }
+
+ for(i=0; i<2; i++)
+ {
+ //Check HT20 to HT40 diff
+ if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
+ {
+ HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1];
+ powerlevel[i] += HT20_pwrdiff;
+ }
+ powerBase1 = powerlevel[i];
+ powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
+ *(MCSBase+i) = powerBase1;
+ //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i)));
+ }
+}
+
+static void getTxPowerWriteValByRegulatory(
+ IN PADAPTER Adapter,
+ IN u8 Channel,
+ IN u8 index,
+ IN u32* powerBase0,
+ IN u32* powerBase1,
+ OUT u32* pOutWriteVal
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ struct dm_priv *pdmpriv = &pHalData->dmpriv;
+ u8 i, chnlGroup, pwr_diff_limit[4];
+ u32 writeVal, customer_limit, rf;
+
+ //
+ // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
+ //
+ for(rf=0; rf<2; rf++)
+ {
+ switch(pHalData->EEPROMRegulatory)
+ {
+ case 0: // Realtek better performance
+ // increase power diff defined by Realtek for large power
+ chnlGroup = 0;
+ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
+ // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
+ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
+ ((index<2)?powerBase0[rf]:powerBase1[rf]);
+ //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
+ break;
+ case 1: // Realtek regulatory
+ // increase power diff defined by Realtek for regulatory
+ {
+ if(pHalData->pwrGroupCnt == 1)
+ chnlGroup = 0;
+ if(pHalData->pwrGroupCnt >= 3)
+ {
+ if(Channel <= 3)
+ chnlGroup = 0;
+ else if(Channel >= 4 && Channel <= 9)
+ chnlGroup = 1;
+ else if(Channel > 9)
+ chnlGroup = 2;
+
+ if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
+ chnlGroup++;
+ else
+ chnlGroup+=4;
+ }
+ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
+ //chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
+ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
+ ((index<2)?powerBase0[rf]:powerBase1[rf]);
+ //RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
+ }
+ break;
+ case 2: // Better regulatory
+ // don't increase any power diff
+ writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]);
+ //RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
+ break;
+ case 3: // Customer defined power diff.
+ // increase power diff defined by customer.
+ chnlGroup = 0;
+ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n",
+ // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]));
+
+ if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
+ {
+ //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n",
+ // ((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1]));
+ }
+ else
+ {
+ //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n",
+ // ((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1]));
+ }
+ for (i=0; i<4; i++)
+ {
+ pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8));
+ if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
+ {
+ if(pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1])
+ pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1];
+ }
+ else
+ {
+ if(pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1])
+ pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1];
+ }
+ }
+ customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) |
+ (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]);
+ //RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit));
+
+ writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]);
+ //RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal));
+ break;
+ default:
+ chnlGroup = 0;
+ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] +
+ ((index<2)?powerBase0[rf]:powerBase1[rf]);
+ //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal));
+ break;
+ }
+
+// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism.
+// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism.
+// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder.
+
+ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
+ writeVal = 0x14141414;
+ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
+ writeVal = 0x00000000;
+
+
+ // 20100628 Joseph: High power mode for BT-Coexist mechanism.
+ // This mechanism is only applied when Driver-Highpower-Mechanism is OFF.
+ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1)
+ {
+ //RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n"));
+ writeVal = writeVal - 0x06060606;
+ }
+ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2)
+ {
+ //RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n"));
+ writeVal = writeVal;
+ }
+ *(pOutWriteVal+rf) = writeVal;
+ }
+}
+
+static void writeOFDMPowerReg(
+ IN PADAPTER Adapter,
+ IN u8 index,
+ IN u32* pValue
+ )
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
+ rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
+ rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12};
+ u16 RegOffset_B[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
+ rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
+ rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12};
+ u8 i, rf, pwr_val[4];
+ u32 writeVal;
+ u16 RegOffset;
+
+ for(rf=0; rf<2; rf++)
+ {
+ writeVal = pValue[rf];
+ for(i=0; i<4; i++)
+ {
+ pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
+ if (pwr_val[i] > RF6052_MAX_TX_PWR)
+ pwr_val[i] = RF6052_MAX_TX_PWR;
+ }
+ writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0];
+
+ if(rf == 0)
+ RegOffset = RegOffset_A[index];
+ else
+ RegOffset = RegOffset_B[index];
+
+ PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal);
+ //RTPRINT(FPHY, PHY_TXPWR, ("Set 0x%x = %08x\n", RegOffset, writeVal));
+
+ // 201005115 Joseph: Set Tx Power diff for Tx power training mechanism.
+ if(((pHalData->rf_type == RF_2T2R) &&
+ (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))||
+ ((pHalData->rf_type != RF_2T2R) &&
+ (RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) )
+ {
+ writeVal = pwr_val[3];
+ if(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04)
+ RegOffset = 0xc90;
+ if(RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04)
+ RegOffset = 0xc98;
+ for(i=0; i<3; i++)
+ {
+ if(i!=2)
+ writeVal = (writeVal>8)?(writeVal-8):0;
+ else
+ writeVal = (writeVal>6)?(writeVal-6):0;
+ rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal);
+ }
+ }
+ }
+}
+/*-----------------------------------------------------------------------------
+ * Function: PHY_RF6052SetOFDMTxPower
+ *
+ * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for
+ * different channel and read original value in TX power register area from
+ * 0xe00. We increase offset and original value to be correct tx pwr.
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 11/05/2008 MHC Simulate 8192 series method.
+ * 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to
+ * A/B pwr difference or legacy/HT pwr diff.
+ * 2. We concern with path B legacy/HT OFDM difference.
+ * 01/22/2009 MHC Support new EPRO format from SD3.
+ *
+ *---------------------------------------------------------------------------*/
+VOID
+rtl8192c_PHY_RF6052SetOFDMTxPower(
+ IN PADAPTER Adapter,
+ IN u8* pPowerLevel,
+ IN u8 Channel)
+{
+ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ u32 writeVal[2], powerBase0[2], powerBase1[2];
+ u8 index = 0;
+
+ getPowerBase(Adapter, pPowerLevel, Channel, &powerBase0[0], &powerBase1[0]);
+
+ for(index=0; index<6; index++)
+ {
+ getTxPowerWriteValByRegulatory(Adapter, Channel, index,
+ &powerBase0[0], &powerBase1[0], &writeVal[0]);
+
+ writeOFDMPowerReg(Adapter, index, &writeVal[0]);
+ }
+
+}
+
+
+static VOID
+phy_RF6052_Config_HardCode(
+ IN PADAPTER Adapter
+ )
+{
+
+ // Set Default Bandwidth to 20M
+ //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
+
+ // TODO: Set Default Channel to channel one for RTL8225
+
+}
+
+static int
+phy_RF6052_Config_ParaFile(
+ IN PADAPTER Adapter
+ )
+{
+ u32 u4RegValue;
+ u8 eRFPath;
+ BB_REGISTER_DEFINITION_T *pPhyReg;
+
+ int rtStatus = _SUCCESS;
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+
+ static char sz8723RadioAFile[] = RTL8723_PHY_RADIO_A;
+ static char sz8723RadioBFile[] = RTL8723_PHY_RADIO_B;
+ char *pszRadioAFile, *pszRadioBFile;
+
+
+ pszRadioAFile = sz8723RadioAFile;
+ pszRadioBFile = sz8723RadioBFile;
+
+
+ //3//-----------------------------------------------------------------
+ //3// <2> Initialize RF
+ //3//-----------------------------------------------------------------
+ //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
+ for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
+ {
+
+ pPhyReg = &pHalData->PHYRegDef[eRFPath];
+
+ /*----Store original RFENV control type----*/
+ switch(eRFPath)
+ {
+ case RF_PATH_A:
+ case RF_PATH_C:
+ u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV);
+ break;
+ case RF_PATH_B :
+ case RF_PATH_D:
+ u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16);
+ break;
+ }
+
+ /*----Set RF_ENV enable----*/
+ PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
+ rtw_udelay_os(1);//PlatformStallExecution(1);
+
+ /*----Set RF_ENV output high----*/
+ PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
+ rtw_udelay_os(1);//PlatformStallExecution(1);
+
+ /* Set bit number of Address and Data for RF register */
+ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255
+ rtw_udelay_os(1);//PlatformStallExecution(1);
+
+ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255
+ rtw_udelay_os(1);//PlatformStallExecution(1);
+
+ /*----Initialize RF fom connfiguration file----*/
+ switch(eRFPath)
+ {
+ case RF_PATH_A:
+#ifdef CONFIG_EMBEDDED_FWIMG
+ #ifdef CONFIG_PHY_SETTING_WITH_ODM
+ if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath))
+ rtStatus= _FAIL;
+ #else
+ rtStatus= rtl8723a_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
+ #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM
+#else
+ rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF_RADIO_PATH_E)eRFPath);
+#endif//#ifdef CONFIG_EMBEDDED_FWIMG
+ break;
+ case RF_PATH_B:
+#ifdef CONFIG_EMBEDDED_FWIMG
+ #ifdef CONFIG_PHY_SETTING_WITH_ODM
+ if(HAL_STATUS_FAILURE ==ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv,(ODM_RF_RADIO_PATH_E)eRFPath, (ODM_RF_RADIO_PATH_E)eRFPath))
+ rtStatus= _FAIL;
+ #else
+ rtStatus = rtl8723a_PHY_ConfigRFWithHeaderFile(Adapter,(RF_RADIO_PATH_E)eRFPath);
+ #endif
+#else
+ rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF_RADIO_PATH_E)eRFPath);
+#endif
+ break;
+ case RF_PATH_C:
+ break;
+ case RF_PATH_D:
+ break;
+ }
+
+ /*----Restore RFENV control type----*/;
+ switch(eRFPath)
+ {
+ case RF_PATH_A:
+ case RF_PATH_C:
+ PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
+ break;
+ case RF_PATH_B :
+ case RF_PATH_D:
+ PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
+ break;
+ }
+
+ if(rtStatus != _SUCCESS){
+ //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath));
+ goto phy_RF6052_Config_ParaFile_Fail;
+ }
+
+ }
+
+ //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n"));
+ return rtStatus;
+
+phy_RF6052_Config_ParaFile_Fail:
+ return rtStatus;
+}
+
+
+int
+PHY_RF6052_Config8723A(
+ IN PADAPTER Adapter)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
+ int rtStatus = _SUCCESS;
+
+ //
+ // Initialize general global value
+ //
+ // TODO: Extend RF_PATH_C and RF_PATH_D in the future
+ if(pHalData->rf_type == RF_1T1R)
+ pHalData->NumTotalRFPath = 1;
+ else
+ pHalData->NumTotalRFPath = 2;
+
+ //
+ // Config BB and RF
+ //
+ rtStatus = phy_RF6052_Config_ParaFile(Adapter);
+ return rtStatus;
+
+}
+
+
+//
+// ==> RF shadow Operation API Code Section!!!
+//
+/*-----------------------------------------------------------------------------
+ * Function: PHY_RFShadowRead
+ * PHY_RFShadowWrite
+ * PHY_RFShadowCompare
+ * PHY_RFShadowRecorver
+ * PHY_RFShadowCompareAll
+ * PHY_RFShadowRecorverAll
+ * PHY_RFShadowCompareFlagSet
+ * PHY_RFShadowRecorverFlagSet
+ *
+ * Overview: When we set RF register, we must write shadow at first.
+ * When we are running, we must compare shadow abd locate error addr.
+ * Decide to recorver or not.
+ *
+ * Input: NONE
+ *
+ * Output: NONE
+ *
+ * Return: NONE
+ *
+ * Revised History:
+ * When Who Remark
+ * 11/20/2008 MHC Create Version 0.
+ *
+ *---------------------------------------------------------------------------*/
+u32
+PHY_RFShadowRead(
+ IN PADAPTER Adapter,
+ IN RF_RADIO_PATH_E eRFPath,
+ IN u32 Offset)
+{
+ return RF_Shadow[eRFPath][Offset].Value;
+
+} /* PHY_RFShadowRead */
+
+
+VOID
+PHY_RFShadowWrite(
+ IN PADAPTER Adapter,
+ IN RF_RADIO_PATH_E eRFPath,
+ IN u32 Offset,
+ IN u32 Data)
+{
+ RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
+ RF_Shadow[eRFPath][Offset].Driver_Write = _TRUE;
+
+} /* PHY_RFShadowWrite */
+
+
+BOOLEAN
+PHY_RFShadowCompare(
+ IN PADAPTER Adapter,
+ IN RF_RADIO_PATH_E eRFPath,
+ IN u32 Offset)
+{
+ u32 reg;
+ // Check if we need to check the register
+ if (RF_Shadow[eRFPath][Offset].Compare == _TRUE)
+ {
+ reg = PHY_QueryRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask);
+ // Compare shadow and real rf register for 20bits!!
+ if (RF_Shadow[eRFPath][Offset].Value != reg)
+ {
+ // Locate error position.
+ RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE;
+ //RT_TRACE(COMP_INIT, DBG_LOUD,
+ //("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n",
+ //eRFPath, Offset, reg));
+ }
+ return RF_Shadow[eRFPath][Offset].ErrorOrNot ;
+ }
+ return _FALSE;
+} /* PHY_RFShadowCompare */
+
+
+VOID
+PHY_RFShadowRecorver(
+ IN PADAPTER Adapter,
+ IN RF_RADIO_PATH_E eRFPath,
+ IN u32 Offset)
+{
+ // Check if the address is error
+ if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE)
+ {
+ // Check if we need to recorver the register.
+ if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE)
+ {
+ PHY_SetRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask,
+ RF_Shadow[eRFPath][Offset].Value);
+ //RT_TRACE(COMP_INIT, DBG_LOUD,
+ //("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx",
+ //eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value));
+ }
+ }
+
+} /* PHY_RFShadowRecorver */
+
+
+VOID
+PHY_RFShadowCompareAll(
+ IN PADAPTER Adapter)
+{
+ u32 eRFPath;
+ u32 Offset;
+
+ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
+ {
+ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
+ {
+ PHY_RFShadowCompare(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset);
+ }
+ }
+
+} /* PHY_RFShadowCompareAll */
+
+
+VOID
+PHY_RFShadowRecorverAll(
+ IN PADAPTER Adapter)
+{
+ u32 eRFPath;
+ u32 Offset;
+
+ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
+ {
+ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
+ {
+ PHY_RFShadowRecorver(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset);
+ }
+ }
+
+} /* PHY_RFShadowRecorverAll */
+
+
+VOID
+PHY_RFShadowCompareFlagSet(
+ IN PADAPTER Adapter,
+ IN RF_RADIO_PATH_E eRFPath,
+ IN u32 Offset,
+ IN u8 Type)
+{
+ // Set True or False!!!
+ RF_Shadow[eRFPath][Offset].Compare = Type;
+
+} /* PHY_RFShadowCompareFlagSet */
+
+
+VOID
+PHY_RFShadowRecorverFlagSet(
+ IN PADAPTER Adapter,
+ IN RF_RADIO_PATH_E eRFPath,
+ IN u32 Offset,
+ IN u8 Type)
+{
+ // Set True or False!!!
+ RF_Shadow[eRFPath][Offset].Recorver= Type;
+
+} /* PHY_RFShadowRecorverFlagSet */
+
+
+VOID
+PHY_RFShadowCompareFlagSetAll(
+ IN PADAPTER Adapter)
+{
+ u32 eRFPath;
+ u32 Offset;
+
+ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
+ {
+ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
+ {
+ // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
+ if (Offset != 0x26 && Offset != 0x27)
+ PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _FALSE);
+ else
+ PHY_RFShadowCompareFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _TRUE);
+ }
+ }
+
+} /* PHY_RFShadowCompareFlagSetAll */
+
+
+VOID
+PHY_RFShadowRecorverFlagSetAll(
+ IN PADAPTER Adapter)
+{
+ u32 eRFPath;
+ u32 Offset;
+
+ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
+ {
+ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
+ {
+ // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
+ if (Offset != 0x26 && Offset != 0x27)
+ PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _FALSE);
+ else
+ PHY_RFShadowRecorverFlagSet(Adapter, (RF_RADIO_PATH_E)eRFPath, Offset, _TRUE);
+ }
+ }
+
+} /* PHY_RFShadowCompareFlagSetAll */
+
+VOID
+PHY_RFShadowRefresh(
+ IN PADAPTER Adapter)
+{
+ u32 eRFPath;
+ u32 Offset;
+
+ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
+ {
+ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
+ {
+ RF_Shadow[eRFPath][Offset].Value = 0;
+ RF_Shadow[eRFPath][Offset].Compare = _FALSE;
+ RF_Shadow[eRFPath][Offset].Recorver = _FALSE;
+ RF_Shadow[eRFPath][Offset].ErrorOrNot = _FALSE;
+ RF_Shadow[eRFPath][Offset].Driver_Write = _FALSE;
+ }
+ }
+
+} /* PHY_RFShadowRead */
+
+/* End of HalRf6052.c */
+
diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_rxdesc.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_rxdesc.c index a94370cd1a75..f030eb821291 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_rxdesc.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_rxdesc.c @@ -245,7 +245,7 @@ void rtl8192c_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pp // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) // - if(padapter->pwrctrlpriv.rf_pwrstate == rf_on) + if(adapter_to_pwrctl(padapter)->rf_pwrstate == rf_on) cck_highpwr = (u8)pHalData->bCckHighPower; else cck_highpwr = _FALSE; diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_sreset.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_sreset.c index 3edd244c0825..24028a36508d 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_sreset.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_sreset.c @@ -1,104 +1,111 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#define _RTL8723A_SRESET_C_ - -#include <rtl8723a_sreset.h> -#include <rtl8723a_hal.h> - - -#ifdef DBG_CONFIG_ERROR_DETECT -void rtl8723a_sreset_xmit_status_check(_adapter *padapter) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct sreset_priv *psrtpriv = &pHalData->srestpriv; - - unsigned long current_time; - struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - unsigned int diff_time; - u32 txdma_status; - - - if( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){ - DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status); - rtw_hal_sreset_reset(padapter); - } - -#ifdef CONFIG_USB_HCI - //total xmit irp = 4 - //DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt); - //if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1) - current_time = rtw_get_current_time(); - - if(0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) { - - diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time); - - if (diff_time > 2000) { - if (psrtpriv->last_tx_complete_time == 0) { - psrtpriv->last_tx_complete_time = current_time; - } - else{ - diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time); - if (diff_time > 4000) { - //padapter->Wifi_Error_Status = WIFI_TX_HANG; - DBG_871X("%s tx hang\n", __FUNCTION__); - rtw_hal_sreset_reset(padapter); - } - } - } - } -#endif // #ifdef CONFIG_USB_HCI - - if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) { - psrtpriv->dbg_trigger_point = SRESET_TGP_NULL; - rtw_hal_sreset_reset(padapter); - return; - } -} - -void rtl8723a_sreset_linked_status_check(_adapter *padapter) -{ - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - struct sreset_priv *psrtpriv = &pHalData->srestpriv; -#if 0 - u32 regc50,regc58,reg824,reg800; - regc50 = rtw_read32(padapter,0xc50); - regc58 = rtw_read32(padapter,0xc58); - reg824 = rtw_read32(padapter,0x824); - reg800 = rtw_read32(padapter,0x800); - if( ((regc50&0xFFFFFF00)!= 0x69543400)|| - ((regc58&0xFFFFFF00)!= 0x69543400)|| - (((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))|| - ( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000))) - { - DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__, - regc50, regc58, reg824, reg800); - rtw_hal_sreset_reset(padapter); - } -#endif - - if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) { - psrtpriv->dbg_trigger_point = SRESET_TGP_NULL; - rtw_hal_sreset_reset(padapter); - return; - } -} -#endif - +/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8723A_SRESET_C_
+
+#include <rtl8723a_sreset.h>
+#include <rtl8723a_hal.h>
+
+
+#ifdef DBG_CONFIG_ERROR_DETECT
+void rtl8723a_sreset_xmit_status_check(_adapter *padapter)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+
+ unsigned long current_time;
+ struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
+ unsigned int diff_time;
+ u32 txdma_status;
+
+
+ if( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){
+ DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
+ rtw_hal_sreset_reset(padapter);
+ }
+
+#ifdef CONFIG_USB_HCI
+ //total xmit irp = 4
+ //DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt);
+ //if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1)
+ current_time = rtw_get_current_time();
+
+ if(0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
+
+ diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);
+
+ if (diff_time > 2000) {
+ if (psrtpriv->last_tx_complete_time == 0) {
+ psrtpriv->last_tx_complete_time = current_time;
+ }
+ else{
+ diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
+ if (diff_time > 4000) {
+ u32 ability;
+
+ //padapter->Wifi_Error_Status = WIFI_TX_HANG;
+ rtw_hal_get_def_var(padapter, HAL_DEF_DBG_DM_FUNC, &ability);
+
+ DBG_871X("%s tx hang %s\n", __FUNCTION__,
+ (ability & ODM_BB_ADAPTIVITY)? "ODM_BB_ADAPTIVITY" : "");
+
+ if (!(ability & ODM_BB_ADAPTIVITY))
+ rtw_hal_sreset_reset(padapter);
+ }
+ }
+ }
+ }
+#endif // #ifdef CONFIG_USB_HCI
+
+ if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
+ psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
+ rtw_hal_sreset_reset(padapter);
+ return;
+ }
+}
+
+void rtl8723a_sreset_linked_status_check(_adapter *padapter)
+{
+ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+ struct sreset_priv *psrtpriv = &pHalData->srestpriv;
+#if 0
+ u32 regc50,regc58,reg824,reg800;
+ regc50 = rtw_read32(padapter,0xc50);
+ regc58 = rtw_read32(padapter,0xc58);
+ reg824 = rtw_read32(padapter,0x824);
+ reg800 = rtw_read32(padapter,0x800);
+ if( ((regc50&0xFFFFFF00)!= 0x69543400)||
+ ((regc58&0xFFFFFF00)!= 0x69543400)||
+ (((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
+ ( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
+ {
+ DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
+ regc50, regc58, reg824, reg800);
+ rtw_hal_sreset_reset(padapter);
+ }
+#endif
+
+ if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
+ psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
+ rtw_hal_sreset_reset(padapter);
+ return;
+ }
+}
+#endif
+
diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_xmit.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_xmit.c index d2dc99074f20..7f705a93c118 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_xmit.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/rtl8723a_xmit.c @@ -1,65 +1,65 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#define _RTL8723A_XMIT_C_ - -#include <drv_conf.h> -#include <osdep_service.h> -#include <drv_types.h> -#include <rtl8723a_hal.h> - -#ifdef CONFIG_XMIT_ACK -void dump_txrpt_ccx_8723a(void *buf) -{ - struct txrpt_ccx_8723a *txrpt_ccx = buf; - - DBG_871X("%s:\n" - "tag1:%u, rsvd:%u, int_bt:%u, int_tri:%u, int_ccx:%u\n" - "mac_id:%u, pkt_drop:%u, pkt_ok:%u, bmc:%u\n" - "retry_cnt:%u, lifetime_over:%u, retry_over:%u\n" - "ccx_qtime:%u\n" - "final_data_rate:0x%02x\n" - "qsel:%u, sw:0x%03x\n" - , __func__ - , txrpt_ccx->tag1, txrpt_ccx->rsvd, txrpt_ccx->int_bt, txrpt_ccx->int_tri, txrpt_ccx->int_ccx - , txrpt_ccx->mac_id, txrpt_ccx->pkt_drop, txrpt_ccx->pkt_ok, txrpt_ccx->bmc - , txrpt_ccx->retry_cnt, txrpt_ccx->lifetime_over, txrpt_ccx->retry_over - , txrpt_ccx_qtime_8723a(txrpt_ccx) - , txrpt_ccx->final_data_rate - , txrpt_ccx->qsel, txrpt_ccx_sw_8723a(txrpt_ccx) - ); -} - -void handle_txrpt_ccx_8723a(_adapter *adapter, void *buf) -{ - struct txrpt_ccx_8723a *txrpt_ccx = buf; - - #ifdef DBG_CCX - dump_txrpt_ccx_8723a(buf); - #endif - - if (txrpt_ccx->int_ccx) { - if (txrpt_ccx->pkt_ok) - rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_SUCCESS); - else - rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); - } -} -#endif //CONFIG_XMIT_ACK - +/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8723A_XMIT_C_
+
+#include <drv_conf.h>
+#include <osdep_service.h>
+#include <drv_types.h>
+#include <rtl8723a_hal.h>
+
+#ifdef CONFIG_XMIT_ACK
+void dump_txrpt_ccx_8723a(void *buf)
+{
+ struct txrpt_ccx_8723a *txrpt_ccx = buf;
+
+ DBG_871X("%s:\n"
+ "tag1:%u, rsvd:%u, int_bt:%u, int_tri:%u, int_ccx:%u\n"
+ "mac_id:%u, pkt_drop:%u, pkt_ok:%u, bmc:%u\n"
+ "retry_cnt:%u, lifetime_over:%u, retry_over:%u\n"
+ "ccx_qtime:%u\n"
+ "final_data_rate:0x%02x\n"
+ "qsel:%u, sw:0x%03x\n"
+ , __func__
+ , txrpt_ccx->tag1, txrpt_ccx->rsvd, txrpt_ccx->int_bt, txrpt_ccx->int_tri, txrpt_ccx->int_ccx
+ , txrpt_ccx->mac_id, txrpt_ccx->pkt_drop, txrpt_ccx->pkt_ok, txrpt_ccx->bmc
+ , txrpt_ccx->retry_cnt, txrpt_ccx->lifetime_over, txrpt_ccx->retry_over
+ , txrpt_ccx_qtime_8723a(txrpt_ccx)
+ , txrpt_ccx->final_data_rate
+ , txrpt_ccx->qsel, txrpt_ccx_sw_8723a(txrpt_ccx)
+ );
+}
+
+void handle_txrpt_ccx_8723a(_adapter *adapter, void *buf)
+{
+ struct txrpt_ccx_8723a *txrpt_ccx = buf;
+
+ #ifdef DBG_CCX
+ dump_txrpt_ccx_8723a(buf);
+ #endif
+
+ if (txrpt_ccx->int_ccx) {
+ if (txrpt_ccx->pkt_ok)
+ rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_SUCCESS);
+ else
+ rtw_ack_tx_done(&adapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL);
+ }
+}
+#endif //CONFIG_XMIT_ACK
+
diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/rtl8723as_led.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/rtl8723as_led.c index b7511deaf49f..597bb30261d8 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/rtl8723as_led.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/rtl8723as_led.c @@ -1,129 +1,129 @@ -/****************************************************************************** - * - * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of version 2 of the GNU General Public License as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA - * - * - ******************************************************************************/ -#define _RTL8723AS_LED_C_ - -#include "drv_types.h" -#include "rtl8723a_hal.h" - -//================================================================================ -// LED object. -//================================================================================ - - -//================================================================================ -// Prototype of protected function. -//================================================================================ - -//================================================================================ -// LED_819xUsb routines. -//================================================================================ - -// -// Description: -// Turn on LED according to LedPin specified. -// -void -SwLedOn( - _adapter *padapter, - PLED_871x pLed -) -{ - u8 LedCfg; - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - - if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) - { - return; - } - - pLed->bLedOn = _TRUE; - -} - - -// -// Description: -// Turn off LED according to LedPin specified. -// -void -SwLedOff( - _adapter *padapter, - PLED_871x pLed -) -{ - u8 LedCfg; - //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); - - if((padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) - { - goto exit; - } - -exit: - pLed->bLedOn = _FALSE; - -} - -//================================================================================ -// Interface to manipulate LED objects. -//================================================================================ - -//================================================================================ -// Default LED behavior. -//================================================================================ - -// -// Description: -// Initialize all LED_871x objects. -// -void -rtl8723as_InitSwLeds( - _adapter *padapter - ) -{ - struct led_priv *pledpriv = &(padapter->ledpriv); - - pledpriv->LedControlHandler = LedControl871x; -#if 0 - - InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0); - - InitLed871x(padapter,&(pledpriv->SwLed1), LED_PIN_LED1); -#endif -} - - -// -// Description: -// DeInitialize all LED_819xUsb objects. -// -void -rtl8723as_DeInitSwLeds( - _adapter *padapter - ) -{ -#if 0 - struct led_priv *ledpriv = &(padapter->ledpriv); - - DeInitLed871x( &(ledpriv->SwLed0) ); - DeInitLed871x( &(ledpriv->SwLed1) ); -#endif -} - +/******************************************************************************
+ *
+ * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
+ *
+ *
+ ******************************************************************************/
+#define _RTL8723AS_LED_C_
+
+#include "drv_types.h"
+#include "rtl8723a_hal.h"
+
+//================================================================================
+// LED object.
+//================================================================================
+
+
+//================================================================================
+// Prototype of protected function.
+//================================================================================
+
+//================================================================================
+// LED_819xUsb routines.
+//================================================================================
+
+//
+// Description:
+// Turn on LED according to LedPin specified.
+//
+void
+SwLedOn(
+ _adapter *padapter,
+ PLED_871x pLed
+)
+{
+ u8 LedCfg;
+ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))
+ {
+ return;
+ }
+
+ pLed->bLedOn = _TRUE;
+
+}
+
+
+//
+// Description:
+// Turn off LED according to LedPin specified.
+//
+void
+SwLedOff(
+ _adapter *padapter,
+ PLED_871x pLed
+)
+{
+ u8 LedCfg;
+ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
+
+ if((padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))
+ {
+ goto exit;
+ }
+
+exit:
+ pLed->bLedOn = _FALSE;
+
+}
+
+//================================================================================
+// Interface to manipulate LED objects.
+//================================================================================
+
+//================================================================================
+// Default LED behavior.
+//================================================================================
+
+//
+// Description:
+// Initialize all LED_871x objects.
+//
+void
+rtl8723as_InitSwLeds(
+ _adapter *padapter
+ )
+{
+ struct led_priv *pledpriv = &(padapter->ledpriv);
+
+ pledpriv->LedControlHandler = LedControl871x;
+#if 0
+
+ InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0);
+
+ InitLed871x(padapter,&(pledpriv->SwLed1), LED_PIN_LED1);
+#endif
+}
+
+
+//
+// Description:
+// DeInitialize all LED_819xUsb objects.
+//
+void
+rtl8723as_DeInitSwLeds(
+ _adapter *padapter
+ )
+{
+#if 0
+ struct led_priv *ledpriv = &(padapter->ledpriv);
+
+ DeInitLed871x( &(ledpriv->SwLed0) );
+ DeInitLed871x( &(ledpriv->SwLed1) );
+#endif
+}
+
diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/rtl8723as_recv.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/rtl8723as_recv.c index d2baae9e28ca..ad2066fe9610 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/rtl8723as_recv.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/rtl8723as_recv.c @@ -155,12 +155,7 @@ void update_recvframe_phyinfo( } pkt_info.Rate = pattrib->mcs_rate; - #ifdef CONFIG_CONCURRENT_MODE - //get Primary adapter's odmpriv - if(padapter->adapter_type > PRIMARY_ADAPTER){ - pHalData = GET_HAL_DATA(padapter->pbuddy_adapter); - } - #endif + //rtl8192c_query_rx_phy_status(precvframe, pphy_status); //_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); ODM_PhyStatusQuery(&pHalData->odmpriv,pPHYInfo,(u8 *)pphy_status,&(pkt_info)); @@ -234,24 +229,24 @@ static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_buf *precvbu _rtw_memcpy(&precvframe_if2->u.hdr.attrib, &precvframe->u.hdr.attrib, sizeof(struct rx_pkt_attrib)); pattrib = &precvframe_if2->u.hdr.attrib; - //driver need to set skb len for skb_copy(). - //If skb->len is zero, skb_copy() will not copy data from original skb. + //driver need to set skb len for rtw_skb_copy(). + //If skb->len is zero, rtw_skb_copy() will not copy data from original skb. skb_put(precvframe->u.hdr.pkt, pattrib->pkt_len); - pkt_copy = skb_copy( precvframe->u.hdr.pkt, GFP_ATOMIC); + pkt_copy = rtw_skb_copy(precvframe->u.hdr.pkt); if (pkt_copy == NULL) { if((pattrib->mfrag == 1)&&(pattrib->frag_num == 0)) { - DBG_8192C("pre_recv_entry(): skb_copy fail , drop frag frame \n"); + DBG_8192C("pre_recv_entry(): rtw_skb_copy fail , drop frag frame \n"); rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); return ret; } - pkt_copy = skb_clone( precvframe->u.hdr.pkt, GFP_ATOMIC); + pkt_copy = rtw_skb_clone(precvframe->u.hdr.pkt); if(pkt_copy == NULL) { - DBG_8192C("pre_recv_entry(): skb_clone fail , drop frame\n"); + DBG_8192C("pre_recv_entry(): rtw_skb_clone fail , drop frame\n"); rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); return ret; } @@ -330,9 +325,11 @@ void rtl8723as_recv(PADAPTER padapter, struct recv_buf *precvbuf) // fix Hardware RX data error, drop whole recv_buffer if ((!(pHalData->ReceiveConfig & RCR_ACRC32)) && pattrib->crc_err) { - #if !(MP_DRIVER==1) - DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__); - #endif + if (padapter->registrypriv.mp_mode == 1) + padapter->mppriv.rx_crcerrpktcount++; + else + DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__); + rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); break; } @@ -352,6 +349,7 @@ void rtl8723as_recv(PADAPTER padapter, struct recv_buf *precvbuf) if ((pattrib->crc_err) || (pattrib->icv_err)) { + if (padapter->registrypriv.mp_mode == 0) DBG_8192C("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err); rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); } @@ -386,11 +384,8 @@ void rtl8723as_recv(PADAPTER padapter, struct recv_buf *precvbuf) alloc_sz += 14; } -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html - pkt_copy = __dev_alloc_skb(alloc_sz, GFP_KERNEL); -#else - pkt_copy = __netdev_alloc_skb(padapter->pnetdev, alloc_sz, GFP_KERNEL); -#endif + pkt_copy = rtw_skb_alloc(alloc_sz); + if(pkt_copy) { pkt_copy->dev = padapter->pnetdev; @@ -411,7 +406,7 @@ void rtl8723as_recv(PADAPTER padapter, struct recv_buf *precvbuf) break; } - precvframe->u.hdr.pkt = skb_clone(precvbuf->pskb, GFP_ATOMIC); + precvframe->u.hdr.pkt = rtw_skb_clone(precvbuf->pskb); if(precvframe->u.hdr.pkt) { _pkt *pkt_clone = precvframe->u.hdr.pkt; @@ -424,7 +419,7 @@ void rtl8723as_recv(PADAPTER padapter, struct recv_buf *precvbuf) } else { - DBG_8192C("rtl8723as_recv_tasklet: skb_clone fail\n"); + DBG_8192C("rtl8723as_recv_tasklet: rtw_skb_clone fail\n"); rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); break; } @@ -531,9 +526,11 @@ static void rtl8723as_recv_tasklet(void *priv) // fix Hardware RX data error, drop whole recv_buffer if ((!(pHalData->ReceiveConfig & RCR_ACRC32)) && pattrib->crc_err) { - #if !(MP_DRIVER==1) - DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__); - #endif + if (padapter->registrypriv.mp_mode == 1) + padapter->mppriv.rx_crcerrpktcount++; + else + DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__); + rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); break; } @@ -553,6 +550,7 @@ static void rtl8723as_recv_tasklet(void *priv) if ((pattrib->crc_err) || (pattrib->icv_err)) { + if (padapter->registrypriv.mp_mode == 0) DBG_8192C("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err); rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); } @@ -587,11 +585,8 @@ static void rtl8723as_recv_tasklet(void *priv) alloc_sz += 14; } -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html - pkt_copy = dev_alloc_skb(alloc_sz); -#else - pkt_copy = netdev_alloc_skb(padapter->pnetdev, alloc_sz); -#endif + pkt_copy = rtw_skb_alloc(alloc_sz); + if(pkt_copy) { pkt_copy->dev = padapter->pnetdev; @@ -612,7 +607,7 @@ static void rtl8723as_recv_tasklet(void *priv) break; } - precvframe->u.hdr.pkt = skb_clone(precvbuf->pskb, GFP_ATOMIC); + precvframe->u.hdr.pkt = rtw_skb_clone(precvbuf->pskb); if(precvframe->u.hdr.pkt) { _pkt *pkt_clone = precvframe->u.hdr.pkt; @@ -625,7 +620,7 @@ static void rtl8723as_recv_tasklet(void *priv) } else { - DBG_8192C("rtl8723as_recv_tasklet: skb_clone fail\n"); + DBG_8192C("rtl8723as_recv_tasklet: rtw_skb_clone fail\n"); rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); break; } @@ -730,7 +725,10 @@ static void rtl8723as_recv_tasklet(void *priv) // fix Hardware RX data error, drop whole recv_buffer if ((!(pHalData->ReceiveConfig & RCR_ACRC32)) && pattrib->crc_err) { - DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__); + if (padapter->registrypriv.mp_mode == 1) + padapter->mppriv.rx_crcerrpktcount++; + else + DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__); rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); break; } @@ -748,12 +746,13 @@ static void rtl8723as_recv_tasklet(void *priv) if ((pattrib->crc_err) || (pattrib->icv_err)) { + if (padapter->registrypriv.mp_mode == 0) DBG_8192C("%s: crc_err=%d icv_err=%d, skip!\n", __FUNCTION__, pattrib->crc_err, pattrib->icv_err); rtw_free_recvframe(precvframe, &precvpriv->free_recv_queue); } else { - ppkt = skb_clone(precvbuf->pskb, GFP_ATOMIC); + ppkt = rtw_skb_clone(precvbuf->pskb); if (ppkt == NULL) { RT_TRACE(_module_rtl871x_recv_c_, _drv_crit_, ("rtl8723as_recv_tasklet: no enough memory to allocate SKB!\n")); @@ -819,7 +818,7 @@ static void rtl8723as_recv_tasklet(void *priv) ptr = precvbuf->pdata; } - dev_kfree_skb_any(precvbuf->pskb); + rtw_skb_free(precvbuf->pskb); precvbuf->pskb = NULL; rtw_enqueue_recvbuf(precvbuf, &precvpriv->free_recv_buf_queue); } while (1); @@ -876,11 +875,7 @@ s32 rtl8723as_init_recv_priv(PADAPTER padapter) SIZE_PTR tmpaddr=0; SIZE_PTR alignment=0; -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html - precvbuf->pskb = __dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL); -#else - precvbuf->pskb = __netdev_alloc_skb(padapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL); -#endif + precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); if(precvbuf->pskb) { diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/rtl8723as_xmit.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/rtl8723as_xmit.c index eb7e41af96c1..a07063a16bba 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/rtl8723as_xmit.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/rtl8723as_xmit.c @@ -105,7 +105,13 @@ s32 rtl8723_dequeue_writeport(PADAPTER padapter, u8 *freePage) } // _exit_critical_bh(&phal->SdioTxFIFOFreePageLock, &irql); - ret = (padapter->bDriverStopped == _TRUE) || (padapter->bSurpriseRemoved == _TRUE); + ret = (padapter->bDriverStopped == _TRUE) || (padapter->bSurpriseRemoved == _TRUE) +#ifdef CONFIG_CONCURRENT_MODE + ||((padapter->pbuddy_adapter) + && ((padapter->pbuddy_adapter->bSurpriseRemoved) ||(padapter->pbuddy_adapter->bDriverStopped))) +#endif + ; + if (ret) { RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s: bSurpriseRemoved(update TX FIFO page)\n", __func__)); @@ -114,11 +120,27 @@ s32 rtl8723_dequeue_writeport(PADAPTER padapter, u8 *freePage) n++; //if ((n & 0x3FF) == 0) - if ((n % 2) == 0) + if ((n % 100) == 0) { - if (n > 5000) { + if (n >= 5000) { + u8 reg_value_1 = 0; + u8 reg_value_2 = 0; + u8 reg_value_3 = 0; + DBG_8192C(KERN_NOTICE "%s: FIFO starvation!(%d) len=%d agg=%d page=(R)%d(A)%d\n", __func__, n, pxmitbuf->len, pxmitbuf->agg_num, pxmitbuf->pg_num, freePage[PageIdx] + freePage[PUBLIC_QUEUE_IDX]); + + //try to recover the transmission + reg_value_1 = rtw_read8(padapter, REG_SYS_FUNC_EN); + reg_value_2 = rtw_read8(padapter, REG_CR); + reg_value_3 = rtw_read8(padapter, REG_TXPAUSE); + DBG_871X("Before recovery: REG_SYS_FUNC_EN = 0x%X, REG_CR = 0x%X, REG_TXPAUSE = 0x%X\n", reg_value_1, reg_value_2, reg_value_3); + + rtw_write8(padapter, REG_SYS_FUNC_EN, reg_value_1 | 0x01); + rtw_write8(padapter, REG_CR, reg_value_2 | 0xC0); + rtw_write8(padapter, REG_TXPAUSE, 0); + DBG_871X("After recovery: REG_SYS_FUNC_EN = 0x%X, REG_CR = 0x%X, REG_TXPAUSE = 0x%X\n", + rtw_read8(padapter, REG_SYS_FUNC_EN), rtw_read8(padapter, REG_CR), rtw_read8(padapter, REG_TXPAUSE)); } else { //RT_TRACE(_module_hal_xmit_c_, _drv_notice_, // ("%s: FIFO starvation!(%d) len=%d agg=%d page=(R)%d(A)%d\n", @@ -348,6 +370,7 @@ static s32 xmit_xmitframes(PADAPTER padapter, struct xmit_priv *pxmitpriv) if (ret == _FAIL) { RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: coalesce FAIL!", __FUNCTION__)); // Todo: error handler + DBG_871X("%s: coalesce FAIL!", __FUNCTION__); } else { k++; if (k != 1) @@ -421,16 +444,14 @@ static s32 xmit_xmitframes(PADAPTER padapter, struct xmit_priv *pxmitpriv) s32 rtl8723as_xmit_handler(PADAPTER padapter) { struct xmit_priv *pxmitpriv; - PHAL_DATA_TYPE phal; s32 ret; _irqL irql; pxmitpriv = &padapter->xmitpriv; - phal = GET_HAL_DATA(padapter); wait: - ret = _rtw_down_sema(&phal->SdioXmitSema); + ret = _rtw_down_sema(&pxmitpriv->SdioXmitSema); if (_FAIL == ret) { RT_TRACE(_module_hal_xmit_c_, _drv_emerg_, ("%s: down sema fail!\n", __FUNCTION__)); return _FAIL; @@ -475,13 +496,11 @@ thread_return rtl8723as_xmit_thread(thread_context context) { PADAPTER padapter; struct xmit_priv *pxmitpriv; - PHAL_DATA_TYPE phal; s32 ret; padapter = (PADAPTER)context; pxmitpriv = &padapter->xmitpriv; - phal = GET_HAL_DATA(padapter); ret = _SUCCESS; thread_enter("RTWHALXT"); @@ -493,7 +512,7 @@ thread_return rtl8723as_xmit_thread(thread_context context) } } while (_SUCCESS == ret); - _rtw_up_sema(&phal->SdioXmitTerminateSema); + _rtw_up_sema(&pxmitpriv->SdioXmitTerminateSema); RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("-%s\n", __FUNCTION__)); @@ -556,14 +575,12 @@ s32 rtl8723as_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe) s32 rtl8723as_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe) { struct xmit_priv *pxmitpriv; - PHAL_DATA_TYPE phal; _irqL irql; s32 err; pxmitframe->attrib.qsel = pxmitframe->attrib.priority; pxmitpriv = &padapter->xmitpriv; - phal = GET_HAL_DATA(padapter); #ifdef CONFIG_80211N_HT if ((pxmitframe->frame_tag == DATA_FRAMETAG) && @@ -589,7 +606,7 @@ s32 rtl8723as_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe) return _TRUE; } - _rtw_up_sema(&phal->SdioXmitSema); + _rtw_up_sema(&pxmitpriv->SdioXmitSema); return _FALSE; } @@ -597,7 +614,6 @@ s32 rtl8723as_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe) s32 rtl8723as_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) { struct xmit_priv *pxmitpriv = &padapter->xmitpriv; - HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); s32 err; if ((err=rtw_xmitframe_enqueue(padapter, pxmitframe)) != _SUCCESS) @@ -613,7 +629,7 @@ s32 rtl8723as_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmit #ifdef CONFIG_SDIO_TX_TASKLET tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); #else - _rtw_up_sema(&pHalData->SdioXmitSema); + _rtw_up_sema(&pxmitpriv->SdioXmitSema); #endif } @@ -629,14 +645,15 @@ s32 rtl8723as_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmit */ s32 rtl8723as_init_xmit_priv(PADAPTER padapter) { + struct xmit_priv *xmitpriv = &padapter->xmitpriv; PHAL_DATA_TYPE phal; phal = GET_HAL_DATA(padapter); _rtw_spinlock_init(&phal->SdioTxFIFOFreePageLock); - _rtw_init_sema(&phal->SdioXmitSema, 0); - _rtw_init_sema(&phal->SdioXmitTerminateSema, 0); + _rtw_init_sema(&xmitpriv->SdioXmitSema, 0); + _rtw_init_sema(&xmitpriv->SdioXmitTerminateSema, 0); return _SUCCESS; } diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/sdio_halinit.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/sdio_halinit.c index f02e85a9c44e..bd4429d3e11c 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/sdio_halinit.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/sdio_halinit.c @@ -823,7 +823,7 @@ static void _RfPowerSave(PADAPTER padapter) pHalData = GET_HAL_DATA(padapter); // pMgntInfo = &padapter->MgntInfo; - pwrctrlpriv = &padapter->pwrctrlpriv; + pwrctrlpriv = adapter_to_pwrctl(padapter); // // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status @@ -989,7 +989,7 @@ static BOOLEAN HalDetectPwrDownMode(PADAPTER Adapter) { u8 tmpvalue; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter); EFUSE_ShadowRead(Adapter, 1, 0x7B/*EEPROM_RF_OPT3_92C*/, (u32 *)&tmpvalue); @@ -1024,7 +1024,7 @@ static u32 rtl8723as_hal_init(PADAPTER padapter) pHalData = GET_HAL_DATA(padapter); - pwrctrlpriv = &padapter->pwrctrlpriv; + pwrctrlpriv = adapter_to_pwrctl(padapter); pregistrypriv = &padapter->registrypriv; is92C = IS_92C_SERIAL(pHalData->VersionID); @@ -1112,7 +1112,7 @@ static u32 rtl8723as_hal_init(PADAPTER padapter) } else #endif - rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0); + //rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0); #if (MP_DRIVER == 1) if (padapter->registrypriv.mp_mode == 1) @@ -1121,7 +1121,7 @@ static u32 rtl8723as_hal_init(PADAPTER padapter) //RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("%s: Don't Download Firmware!!\n", __FUNCTION__)); //padapter->bFWReady = _FALSE; } - else +// else #endif { ret = rtl8723a_FirmwareDownload(padapter); @@ -1841,7 +1841,7 @@ static u32 Hal_readPGDataFromConfigFile( temp[2] = 0; // add end of string '\0' - fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDWR, 0644); + fp = filp_open("/system/etc/wifi/wifi_efuse.map", O_RDONLY, 0); if (IS_ERR(fp)) { pEEPROM->bloadfile_fail_flag = _TRUE; DBG_871X("Error, Efuse configure file doesn't exist.\n"); @@ -1981,6 +1981,11 @@ readAdapterInfo( Hal_InitChannelPlan(padapter); Hal_CustomizeByCustomerID_8723AS(padapter); +#ifdef CONFIG_RF_GAIN_OFFSET + Hal_ReadRFGainOffset(padapter, hwinfo, pEEPROM->bautoload_fail_flag); +#endif //CONFIG_RF_GAIN_OFFSET + + RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<==== readpadapterInfo_8723S()\n")); } @@ -2102,6 +2107,9 @@ _func_enter_; switch (variable) { + case HW_VAR_GET_CPWM: + *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1); + break; default: GetHwReg8723A(padapter, variable, val); break; @@ -2142,22 +2150,11 @@ GetHalDefVar8723ASDIO( case HAL_DEF_DBG_DUMP_RXPKT: *(( u8*)pValue) = pHalData->bDumpRxPkt; break; - case HAL_DEF_DBG_DM_FUNC: - *(( u32*)pValue) =pHalData->odmpriv.SupportAbility; - break; case HW_VAR_MAX_RX_AMPDU_FACTOR: *(( u32*)pValue) = MAX_AMPDU_FACTOR_64K; - break; - case HW_DEF_ODM_DBG_FLAG: - { - u8Byte DebugComponents = *((u32*)pValue); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - printk("pDM_Odm->DebugComponents = 0x%llx \n",pDM_Odm->DebugComponents ); - } break; default: - //RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8723ASDIO(): Unkown variable: %d!\n", eVariable)); - bResult = _FAIL; + bResult = GetHalDefVar(Adapter, eVariable, pValue); break; } @@ -2222,27 +2219,8 @@ SetHalDefVar8723ASDIO( } } break; - case HW_DEF_FA_CNT_DUMP: - { - u8 bRSSIDump = *((u8*)pValue); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - if(bRSSIDump) - pDM_Odm->DebugComponents = ODM_COMP_DIG|ODM_COMP_FA_CNT ; - else - pDM_Odm->DebugComponents = 0; - - } - break; - case HW_DEF_ODM_DBG_FLAG: - { - u8Byte DebugComponents = *((u8Byte*)pValue); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - pDM_Odm->DebugComponents = DebugComponents; - } - break; default: - //RT_TRACE(COMP_INIT, DBG_TRACE, ("SetHalDefVar819xUsb(): Unkown variable: %d!\n", eVariable)); - bResult = _FAIL; + bResult = SetHalDefVar(Adapter, eVariable, pValue); break; } @@ -2263,10 +2241,7 @@ void UpdateHalRAMask8192CUsb(PADAPTER padapter, u32 mac_id, u8 rssi_level) struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); -#ifdef CONFIG_CONCURRENT_MODE - if(rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER) - pHalData = GET_HAL_DATA(padapter->pbuddy_adapter); -#endif //CONFIG_CONCURRENT_MODE + if (mac_id >= NUM_STA) //CAM_SIZE { @@ -2378,14 +2353,21 @@ void rtl8723as_set_hal_ops(PADAPTER padapter) _func_enter_; - //set hardware operation functions - padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE)); - if (padapter->HalData == NULL) { - RT_TRACE(_module_hci_hal_init_c_, _drv_err_, - ("can't alloc memory for HAL DATA\n")); + +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->isprimary) +#endif //CONFIG_CONCURRENT_MODE + { + //set hardware operation functions + padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE)); + if(padapter->HalData == NULL){ + DBG_8192C("cant not alloc memory for HAL DATA \n"); + } } + + //_rtw_memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE)); + padapter->hal_data_sz = sizeof(HAL_DATA_TYPE); - padapter->hal_data_sz = sizeof(HAL_DATA_TYPE); rtl8723a_set_hal_ops(pHalFunc); diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/sdio_ops.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/sdio_ops.c index a5e60de92085..c319fb5ec643 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/sdio_ops.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/sdio/sdio_ops.c @@ -19,34 +19,12 @@ #define _SDIO_OPS_C_ #include <drv_types.h> +#include <sdio_ops.h> #include <rtl8723a_spec.h> #include <rtl8723a_hal.h> //#define SDIO_DEBUG_IO 1 -#define SDIO_ERR_VAL8 0xEA -#define SDIO_ERR_VAL16 0xEAEA -#define SDIO_ERR_VAL32 0xEAEAEAEA - -extern u8 sd_f0_read8(PSDIO_DATA psdio, u32 addr, s32 *err); -extern void sd_f0_write8(PSDIO_DATA psdio, u32 addr, s32 *err); - -extern s32 _sd_cmd52_read(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata); -extern s32 _sd_cmd52_write(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata); -extern s32 sd_cmd52_read(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata); -extern s32 sd_cmd52_write(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata); - -extern u8 sd_read8(PSDIO_DATA psdio, u32 addr, s32 *err); -extern u16 sd_read16(PSDIO_DATA psdio, u32 addr, s32 *err); -extern u32 sd_read32(PSDIO_DATA psdio, u32 addr, s32 *err); -extern s32 _sd_read(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata); -extern s32 sd_read(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata); -extern void sd_write8(PSDIO_DATA psdio, u32 addr, u8 v, s32 *err); -extern void sd_write16(PSDIO_DATA psdio, u32 addr, u16 v, s32 *err); -extern void sd_write32(PSDIO_DATA psdio, u32 addr, u32 v, s32 *err); -extern s32 _sd_write(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata); -extern s32 sd_write(PSDIO_DATA psdio, u32 addr, u32 cnt, void *pdata); - // // Description: // The following mapping is for SDIO host local register space. @@ -183,18 +161,12 @@ static u32 _cvrt2ftaddr(const u32 addr, u8 *pdeviceId, u16 *poffset) u8 sdio_read8(struct intf_hdl *pintfhdl, u32 addr) { - struct dvobj_priv *psdiodev; - PSDIO_DATA psdio; u32 ftaddr; u8 val; _func_enter_; - - psdiodev = pintfhdl->pintf_dev; - psdio = &psdiodev->intf_data; - ftaddr = _cvrt2ftaddr(addr, NULL, NULL); - val = sd_read8(psdio, ftaddr, NULL); + val = sd_read8(pintfhdl, ftaddr, NULL); _func_exit_; @@ -203,18 +175,13 @@ _func_exit_; u16 sdio_read16(struct intf_hdl *pintfhdl, u32 addr) { - struct dvobj_priv *psdiodev; - PSDIO_DATA psdio; u32 ftaddr; u16 val; _func_enter_; - psdiodev = pintfhdl->pintf_dev; - psdio = &psdiodev->intf_data; - ftaddr = _cvrt2ftaddr(addr, NULL, NULL); - sd_cmd52_read(psdio, ftaddr, 2, (u8*)&val); + sd_cmd52_read(pintfhdl, ftaddr, 2, (u8*)&val); val = le16_to_cpu(val); _func_exit_; @@ -225,8 +192,6 @@ _func_exit_; u32 sdio_read32(struct intf_hdl *pintfhdl, u32 addr) { PADAPTER padapter; - struct dvobj_priv *psdiodev; - PSDIO_DATA psdio; u8 bMacPwrCtrlOn; u8 deviceId; u16 offset; @@ -238,8 +203,6 @@ u32 sdio_read32(struct intf_hdl *pintfhdl, u32 addr) _func_enter_; padapter = pintfhdl->padapter; - psdiodev = pintfhdl->pintf_dev; - psdio = &psdiodev->intf_data; ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset); @@ -247,11 +210,11 @@ _func_enter_; if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100)) || (_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK - || (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode) + || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) #endif ) { - err = sd_cmd52_read(psdio, ftaddr, 4, (u8*)&val); + err = sd_cmd52_read(pintfhdl, ftaddr, 4, (u8*)&val); #ifdef SDIO_DEBUG_IO if (!err) { #endif @@ -268,7 +231,7 @@ _func_enter_; // 4 bytes alignment shift = ftaddr & 0x3; if (shift == 0) { - val = sd_read32(psdio, ftaddr, NULL); + val = sd_read32(pintfhdl, ftaddr, NULL); } else { u8 *ptmpbuf; @@ -279,7 +242,7 @@ _func_enter_; } ftaddr &= ~(u16)0x3; - sd_read(psdio, ftaddr, 8, ptmpbuf); + sd_read(pintfhdl, ftaddr, 8, ptmpbuf); _rtw_memcpy(&val, ptmpbuf+shift, 4); val = le32_to_cpu(val); @@ -294,8 +257,6 @@ _func_exit_; s32 sdio_readN(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pbuf) { PADAPTER padapter; - struct dvobj_priv *psdiodev; - PSDIO_DATA psdio; u8 bMacPwrCtrlOn; u8 deviceId; u16 offset; @@ -306,8 +267,6 @@ s32 sdio_readN(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pbuf) _func_enter_; padapter = pintfhdl->padapter; - psdiodev = pintfhdl->pintf_dev; - psdio = &psdiodev->intf_data; err = 0; ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset); @@ -316,18 +275,18 @@ _func_enter_; if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100)) || (_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK - || (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode) + || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) #endif ) { - err = sd_cmd52_read(psdio, ftaddr, cnt, pbuf); + err = sd_cmd52_read(pintfhdl, ftaddr, cnt, pbuf); return err; } // 4 bytes alignment shift = ftaddr & 0x3; if (shift == 0) { - err = sd_read(psdio, ftaddr, cnt, pbuf); + err = sd_read(pintfhdl, ftaddr, cnt, pbuf); } else { u8 *ptmpbuf; u32 n; @@ -336,7 +295,7 @@ _func_enter_; n = cnt + shift; ptmpbuf = rtw_malloc(n); if (NULL == ptmpbuf) return -1; - err = sd_read(psdio, ftaddr, n, ptmpbuf); + err = sd_read(pintfhdl, ftaddr, n, ptmpbuf); if (!err) _rtw_memcpy(pbuf, ptmpbuf+shift, cnt); rtw_mfree(ptmpbuf, n); @@ -349,18 +308,13 @@ _func_exit_; s32 sdio_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val) { - struct dvobj_priv *psdiodev; - PSDIO_DATA psdio; u32 ftaddr; s32 err; _func_enter_; - psdiodev = pintfhdl->pintf_dev; - psdio = &psdiodev->intf_data; - ftaddr = _cvrt2ftaddr(addr, NULL, NULL); - sd_write8(psdio, ftaddr, val, &err); + sd_write8(pintfhdl, ftaddr, val, &err); _func_exit_; @@ -369,20 +323,15 @@ _func_exit_; s32 sdio_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val) { - struct dvobj_priv *psdiodev; - PSDIO_DATA psdio; u32 ftaddr; u8 shift; s32 err; _func_enter_; - psdiodev = pintfhdl->pintf_dev; - psdio = &psdiodev->intf_data; - ftaddr = _cvrt2ftaddr(addr, NULL, NULL); val = cpu_to_le16(val); - err = sd_cmd52_write(psdio, ftaddr, 2, (u8*)&val); + err = sd_cmd52_write(pintfhdl, ftaddr, 2, (u8*)&val); _func_exit_; @@ -392,8 +341,6 @@ _func_exit_; s32 sdio_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) { PADAPTER padapter; - struct dvobj_priv *psdiodev; - PSDIO_DATA psdio; u8 bMacPwrCtrlOn; u8 deviceId; u16 offset; @@ -404,8 +351,6 @@ s32 sdio_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) _func_enter_; padapter = pintfhdl->padapter; - psdiodev = pintfhdl->pintf_dev; - psdio = &psdiodev->intf_data; err = 0; ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset); @@ -414,12 +359,12 @@ _func_enter_; if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100)) || (_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK - || (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode) + || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) #endif ) { val = cpu_to_le32(val); - err = sd_cmd52_write(psdio, ftaddr, 4, (u8*)&val); + err = sd_cmd52_write(pintfhdl, ftaddr, 4, (u8*)&val); return err; } @@ -428,16 +373,16 @@ _func_enter_; #if 1 if (shift == 0) { - sd_write32(psdio, ftaddr, val, &err); + sd_write32(pintfhdl, ftaddr, val, &err); } else { val = cpu_to_le32(val); - err = sd_cmd52_write(psdio, ftaddr, 4, (u8*)&val); + err = sd_cmd52_write(pintfhdl, ftaddr, 4, (u8*)&val); } #else if (shift == 0) { - sd_write32(psdio, ftaddr, val, &err); + sd_write32(pintfhdl, ftaddr, val, &err); } else { u8 *ptmpbuf; @@ -445,14 +390,14 @@ _func_enter_; if (NULL == ptmpbuf) return (-1); ftaddr &= ~(u16)0x3; - err = sd_read(psdio, ftaddr, 8, ptmpbuf); + err = sd_read(pintfhdl, ftaddr, 8, ptmpbuf); if (err) { rtw_mfree(ptmpbuf, 8); return err; } val = cpu_to_le32(val); _rtw_memcpy(ptmpbuf+shift, &val, 4); - err = sd_write(psdio, ftaddr, 8, ptmpbuf); + err = sd_write(pintfhdl, ftaddr, 8, ptmpbuf); rtw_mfree(ptmpbuf, 8); } @@ -466,8 +411,6 @@ _func_exit_; s32 sdio_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8* pbuf) { PADAPTER padapter; - struct dvobj_priv *psdiodev; - PSDIO_DATA psdio; u8 bMacPwrCtrlOn; u8 deviceId; u16 offset; @@ -478,8 +421,6 @@ s32 sdio_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8* pbuf) _func_enter_; padapter = pintfhdl->padapter; - psdiodev = pintfhdl->pintf_dev; - psdio = &psdiodev->intf_data; err = 0; ftaddr = _cvrt2ftaddr(addr, &deviceId, &offset); @@ -488,17 +429,17 @@ _func_enter_; if (((deviceId == WLAN_IOREG_DEVICE_ID) && (offset < 0x100)) || (_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK - || (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode) + || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) #endif ) { - err = sd_cmd52_write(psdio, ftaddr, cnt, pbuf); + err = sd_cmd52_write(pintfhdl, ftaddr, cnt, pbuf); return err; } shift = ftaddr & 0x3; if (shift == 0) { - err = sd_write(psdio, ftaddr, cnt, pbuf); + err = sd_write(pintfhdl, ftaddr, cnt, pbuf); } else { u8 *ptmpbuf; u32 n; @@ -507,13 +448,13 @@ _func_enter_; n = cnt + shift; ptmpbuf = rtw_malloc(n); if (NULL == ptmpbuf) return -1; - err = sd_read(psdio, ftaddr, 4, ptmpbuf); + err = sd_read(pintfhdl, ftaddr, 4, ptmpbuf); if (err) { rtw_mfree(ptmpbuf, n); return err; } _rtw_memcpy(ptmpbuf+shift, pbuf, cnt); - err = sd_write(psdio, ftaddr, n, ptmpbuf); + err = sd_write(pintfhdl, ftaddr, n, ptmpbuf); rtw_mfree(ptmpbuf, n); } @@ -600,7 +541,7 @@ static u32 sdio_read_port( #endif } - err = _sd_read(psdio, addr, cnt, mem); + err = _sd_read(pintfhdl, addr, cnt, mem); #ifdef SDIO_DYNAMIC_ALLOC_MEM if ((oldcnt != cnt) && (oldmem)) { @@ -643,6 +584,12 @@ static u32 sdio_write_port( padapter = pintfhdl->padapter; psdio = &adapter_to_dvobj(padapter)->intf_data; + if(padapter->hw_init_completed == _FALSE) + { + DBG_871X("%s [addr=0x%x cnt=%d] padapter->hw_init_completed == _FALSE \n",__func__,addr,cnt); + return _FAIL; + } + cnt = _RND4(cnt); HalSdioGetCmdAddr8723ASdio(padapter, addr, cnt >> 2, &addr); @@ -650,7 +597,7 @@ static u32 sdio_write_port( cnt = _RND(cnt, psdio->block_transfer_len); // cnt = sdio_align_size(cnt); - err = sd_write(psdio, addr, cnt, xmitbuf->pdata); + err = sd_write(pintfhdl, addr, cnt, xmitbuf->pdata); rtw_sctx_done_err(&xmitbuf->sctx, err ? RTW_SCTX_DONE_WRITE_PORT_ERR : RTW_SCTX_DONE_SUCCESS); @@ -688,21 +635,20 @@ s32 _sdio_local_read( u32 cnt, u8 *pbuf) { - PSDIO_DATA psdio; + struct intf_hdl * pintfhdl; u8 bMacPwrCtrlOn; s32 err; u8 *ptmpbuf; u32 n; - - psdio = &adapter_to_dvobj(padapter)->intf_data; - + pintfhdl=&padapter->iopriv.intf; + HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if (_FALSE == bMacPwrCtrlOn) { - err = _sd_cmd52_read(psdio, addr, cnt, pbuf); + err = _sd_cmd52_read(pintfhdl, addr, cnt, pbuf); return err; } @@ -711,7 +657,7 @@ s32 _sdio_local_read( if (!ptmpbuf) return (-1); - err = _sd_read(psdio, addr, n, ptmpbuf); + err = _sd_read(pintfhdl, addr, n, ptmpbuf); if (!err) _rtw_memcpy(pbuf, ptmpbuf, cnt); @@ -730,25 +676,23 @@ s32 sdio_local_read( u32 cnt, u8 *pbuf) { - PSDIO_DATA psdio; + struct intf_hdl * pintfhdl; u8 bMacPwrCtrlOn; s32 err; u8 *ptmpbuf; u32 n; - - psdio = &adapter_to_dvobj(padapter)->intf_data; - + pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if ((_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK - || (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode) + || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) #endif ) { - err = sd_cmd52_read(psdio, addr, cnt, pbuf); + err = sd_cmd52_read(pintfhdl, addr, cnt, pbuf); return err; } @@ -757,7 +701,7 @@ s32 sdio_local_read( if (!ptmpbuf) return (-1); - err = sd_read(psdio, addr, n, ptmpbuf); + err = sd_read(pintfhdl, addr, n, ptmpbuf); if (!err) _rtw_memcpy(pbuf, ptmpbuf, cnt); @@ -776,7 +720,7 @@ s32 _sdio_local_write( u32 cnt, u8 *pbuf) { - PSDIO_DATA psdio; + struct intf_hdl * pintfhdl; u8 bMacPwrCtrlOn; s32 err; u8 *ptmpbuf; @@ -787,18 +731,17 @@ s32 _sdio_local_write( if(cnt & 0x3) DBG_8192C("%s, size must be the multiple of 4 \n", __FUNCTION__); - psdio = &adapter_to_dvobj(padapter)->intf_data; - + pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if ((_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK - || (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode) + || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) #endif ) { - err = _sd_cmd52_write(psdio, addr, cnt, pbuf); + err = _sd_cmd52_write(pintfhdl, addr, cnt, pbuf); return err; } @@ -808,7 +751,7 @@ s32 _sdio_local_write( _rtw_memcpy(ptmpbuf, pbuf, cnt); - err = _sd_write(psdio, addr, cnt, ptmpbuf); + err = _sd_write(pintfhdl, addr, cnt, ptmpbuf); if (ptmpbuf) rtw_mfree(ptmpbuf, cnt); @@ -825,7 +768,7 @@ s32 sdio_local_write( u32 cnt, u8 *pbuf) { - PSDIO_DATA psdio; + struct intf_hdl * pintfhdl; u8 bMacPwrCtrlOn; s32 err; u8 *ptmpbuf; @@ -836,18 +779,18 @@ s32 sdio_local_write( if(cnt & 0x3) DBG_8192C("%s, size must be the multiple of 4 \n", __FUNCTION__); - psdio = &adapter_to_dvobj(padapter)->intf_data; - + pintfhdl=&padapter->iopriv.intf; + HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if ((_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK - || (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode) + || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) #endif ) { - err = sd_cmd52_write(psdio, addr, cnt, pbuf); + err = sd_cmd52_write(pintfhdl, addr, cnt, pbuf); return err; } @@ -857,7 +800,7 @@ s32 sdio_local_write( _rtw_memcpy(ptmpbuf, pbuf, cnt); - err = sd_write(psdio, addr, cnt, ptmpbuf); + err = sd_write(pintfhdl, addr, cnt, ptmpbuf); if (ptmpbuf) rtw_mfree(ptmpbuf, cnt); @@ -867,26 +810,24 @@ s32 sdio_local_write( u8 SdioLocalCmd52Read1Byte(PADAPTER padapter, u32 addr) { - PSDIO_DATA psdio; + struct intf_hdl * pintfhdl; u8 val = 0; - - psdio = &adapter_to_dvobj(padapter)->intf_data; + pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); - sd_cmd52_read(psdio, addr, 1, &val); + sd_cmd52_read(pintfhdl, addr, 1, &val); return val; } u16 SdioLocalCmd52Read2Byte(PADAPTER padapter, u32 addr) { - PSDIO_DATA psdio; + struct intf_hdl * pintfhdl; u16 val = 0; - - psdio = &adapter_to_dvobj(padapter)->intf_data; + pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); - sd_cmd52_read(psdio, addr, 2, (u8*)&val); + sd_cmd52_read(pintfhdl, addr, 2, (u8*)&val); val = le16_to_cpu(val); @@ -895,13 +836,12 @@ u16 SdioLocalCmd52Read2Byte(PADAPTER padapter, u32 addr) u32 SdioLocalCmd52Read4Byte(PADAPTER padapter, u32 addr) { - PSDIO_DATA psdio; + struct intf_hdl * pintfhdl; u32 val = 0; - - psdio = &adapter_to_dvobj(padapter)->intf_data; + pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); - sd_cmd52_read(psdio, addr, 4, (u8*)&val); + sd_cmd52_read(pintfhdl, addr, 4, (u8*)&val); val = le32_to_cpu(val); @@ -910,60 +850,55 @@ u32 SdioLocalCmd52Read4Byte(PADAPTER padapter, u32 addr) u32 SdioLocalCmd53Read4Byte(PADAPTER padapter, u32 addr) { - PSDIO_DATA psdio; + struct intf_hdl * pintfhdl; u8 bMacPwrCtrlOn; - u32 val; + u32 val=0; - - val = 0; - psdio = &adapter_to_dvobj(padapter)->intf_data; + pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); if ((_FALSE == bMacPwrCtrlOn) #ifdef CONFIG_LPS_LCLK - || (_TRUE == padapter->pwrctrlpriv.bFwCurrentInPSMode) + || (_TRUE == adapter_to_pwrctl(padapter)->bFwCurrentInPSMode) #endif ) { - sd_cmd52_read(psdio, addr, 4, (u8*)&val); + sd_cmd52_read(pintfhdl, addr, 4, (u8*)&val); val = le32_to_cpu(val); } else - val = sd_read32(psdio, addr, NULL); + val = sd_read32(pintfhdl, addr, NULL); return val; } void SdioLocalCmd52Write1Byte(PADAPTER padapter, u32 addr, u8 v) { - PSDIO_DATA psdio; - + struct intf_hdl * pintfhdl; - psdio = &adapter_to_dvobj(padapter)->intf_data; + pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); - sd_cmd52_write(psdio, addr, 1, &v); + sd_cmd52_write(pintfhdl, addr, 1, &v); } void SdioLocalCmd52Write2Byte(PADAPTER padapter, u32 addr, u16 v) { - PSDIO_DATA psdio; + struct intf_hdl * pintfhdl; - - psdio = &adapter_to_dvobj(padapter)->intf_data; + pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); v = cpu_to_le16(v); - sd_cmd52_write(psdio, addr, 2, (u8*)&v); + sd_cmd52_write(pintfhdl, addr, 2, (u8*)&v); } void SdioLocalCmd52Write4Byte(PADAPTER padapter, u32 addr, u32 v) { - PSDIO_DATA psdio; - + struct intf_hdl * pintfhdl; - psdio = &adapter_to_dvobj(padapter)->intf_data; + pintfhdl=&padapter->iopriv.intf; HalSdioGetCmdAddr8723ASdio(padapter, SDIO_LOCAL_DEVICE_ID, addr, &addr); v = cpu_to_le32(v); - sd_cmd52_write(psdio, addr, 4, (u8*)&v); + sd_cmd52_write(pintfhdl, addr, 4, (u8*)&v); } #if 0 @@ -1147,13 +1082,17 @@ void InitInterrupt8723ASdio(PADAPTER padapter) // SDIO_HIMR_TXBCNOK_MSK | // SDIO_HIMR_TXBCNERR_MSK | // SDIO_HIMR_BCNERLY_INT_MSK | +#ifndef CONFIG_DETECT_C2H_BY_POLLING #if defined( CONFIG_BT_COEXIST) || defined(CONFIG_MP_INCLUDED) SDIO_HIMR_C2HCMD_MSK | #endif +#endif +#ifndef CONFIG_DETECT_CPWM_BY_POLLING #ifdef CONFIG_LPS_LCLK SDIO_HIMR_CPWM1_MSK | // SDIO_HIMR_CPWM2_MSK | #endif +#endif // SDIO_HIMR_HSISR_IND_MSK | // SDIO_HIMR_GTINT3_IND_MSK | // SDIO_HIMR_GTINT4_IND_MSK | @@ -1412,11 +1351,8 @@ static struct recv_buf* sd_recv_rxfifo(PADAPTER padapter, u32 size) SIZE_PTR tmpaddr=0; SIZE_PTR alignment=0; -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html - precvbuf->pskb = __dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL); -#else - precvbuf->pskb = __netdev_alloc_skb(padapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL); -#endif + precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); + if(precvbuf->pskb) { precvbuf->pskb->dev = padapter->pnetdev; @@ -1467,11 +1403,9 @@ static struct recv_buf* sd_recv_rxfifo(PADAPTER padapter, u32 size) //3 1. alloc skb // align to block size allocsize = _RND(readsize, adapter_to_dvobj(padapter)->intf_data.block_transfer_len); -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html - ppkt = __dev_alloc_skb(allocsize, GFP_KERNEL); -#else - ppkt = __netdev_alloc_skb(padapter->pnetdev, allocsize, GFP_KERNEL); -#endif + + ppkt = rtw_skb_alloc(allocsize); + if (ppkt == NULL) { RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: alloc_skb fail! alloc=%d read=%d\n", __FUNCTION__, allocsize, readsize)); return NULL; @@ -1482,7 +1416,7 @@ static struct recv_buf* sd_recv_rxfifo(PADAPTER padapter, u32 size) // rtw_read_port(padapter, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); ret = sdio_read_port(&padapter->iopriv.intf, WLAN_RX0FF_DEVICE_ID, readsize, preadbuf); if (ret == _FAIL) { - dev_kfree_skb_any(ppkt); + rtw_skb_free(ppkt); RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: read port FAIL!\n", __FUNCTION__)); return NULL; } @@ -1491,7 +1425,7 @@ static struct recv_buf* sd_recv_rxfifo(PADAPTER padapter, u32 size) precvpriv = &padapter->recvpriv; precvbuf = rtw_dequeue_recvbuf(&precvpriv->free_recv_buf_queue); if (precvbuf == NULL) { - dev_kfree_skb_any(ppkt); + rtw_skb_free(ppkt); RT_TRACE(_module_hci_ops_os_c_, _drv_err_, ("%s: alloc recvbuf FAIL!\n", __FUNCTION__)); return NULL; } @@ -1538,6 +1472,7 @@ void sd_int_dpc(PADAPTER padapter) HAL_DATA_TYPE *phal; struct dvobj_priv *dvobj = adapter_to_dvobj(padapter); + struct intf_hdl * pintfhdl=&padapter->iopriv.intf; phal = GET_HAL_DATA(padapter); if (phal->sdio_hisr & SDIO_HISR_CPWM1) @@ -1546,14 +1481,14 @@ void sd_int_dpc(PADAPTER padapter) #ifdef CONFIG_LPS_RPWM_TIMER u8 bcancelled; - _cancel_timer(&padapter->pwrctrlpriv.pwr_rpwm_timer, &bcancelled); + _cancel_timer(&(adapter_to_pwrctl(padapter)->pwr_rpwm_timer), &bcancelled); #endif // CONFIG_LPS_RPWM_TIMER _sdio_local_read(padapter, SDIO_REG_HCPWM1, 1, &report.state); #ifdef CONFIG_LPS_LCLK //cpwm_int_hdl(padapter, &report); - _set_workitem(&padapter->pwrctrlpriv.cpwm_event); + _set_workitem(&(adapter_to_pwrctl(padapter)->cpwm_event)); #endif } @@ -1567,8 +1502,8 @@ void sd_int_dpc(PADAPTER padapter) { addr = REG_TXDMA_STATUS; HalSdioGetCmdAddr8723ASdio(padapter, WLAN_IOREG_DEVICE_ID, addr, &addr); - _sd_read(&dvobj->intf_data, addr, 4, status); - _sd_write(&dvobj->intf_data, addr, 4, status); + _sd_read(pintfhdl, addr, 4, status); + _sd_write(pintfhdl, addr, 4, status); DBG_8192C("%s: SDIO_HISR_TXERR (0x%08x)\n", __func__, le32_to_cpu(*(u32*)status)); rtw_mfree(status, 4); } else { @@ -1595,10 +1530,15 @@ void sd_int_dpc(PADAPTER padapter) if (c2h_id_filter_ccx_8723a(c2h_evt->id)) { /* Handle CCX report here */ rtw_hal_c2h_handler(padapter, c2h_evt); + rtw_mfree((u8*)c2h_evt, 16); } else { rtw_c2h_wk_cmd(padapter, (u8 *)c2h_evt); } } + else + { + rtw_mfree((u8*)c2h_evt, 16); + } } else { /* Error handling for malloc fail */ if (rtw_cbuf_push(padapter->evtpriv.c2h_queue, (void*)NULL) != _SUCCESS) diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/rtl8723au_recv.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/rtl8723au_recv.c index e09d04fdb8b9..330c41c8f044 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/rtl8723au_recv.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/rtl8723au_recv.c @@ -149,12 +149,7 @@ int rtl8192cu_init_recv_priv(_adapter *padapter) for(i=0; i<NR_PREALLOC_RECV_SKB; i++) { - - #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html - pskb = __dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL); - #else - pskb = __netdev_alloc_skb(padapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ, GFP_KERNEL); - #endif + pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); if(pskb) { @@ -215,7 +210,7 @@ void rtl8192cu_free_recv_priv (_adapter *padapter) DBG_8192C(KERN_WARNING "rx_skb_queue not empty\n"); } - skb_queue_purge(&precvpriv->rx_skb_queue); + rtw_skb_queue_purge(&precvpriv->rx_skb_queue); #ifdef CONFIG_PREALLOC_RECV_SKB @@ -223,7 +218,7 @@ void rtl8192cu_free_recv_priv (_adapter *padapter) DBG_8192C(KERN_WARNING "free_recv_skb_queue not empty, %d\n", skb_queue_len(&precvpriv->free_recv_skb_queue)); } - skb_queue_purge(&precvpriv->free_recv_skb_queue); + rtw_skb_queue_purge(&precvpriv->free_recv_skb_queue); #endif @@ -340,13 +335,6 @@ void update_recvframe_phyinfo( } pkt_info.Rate = pattrib->mcs_rate; - #ifdef CONFIG_CONCURRENT_MODE - //get Primary adapter's odmpriv - if(padapter->adapter_type > PRIMARY_ADAPTER){ - pHalData = GET_HAL_DATA(padapter->pbuddy_adapter); - } - #endif - //rtl8192c_query_rx_phy_status(precvframe, pphy_status); //_enter_critical_bh(&pHalData->odm_stainfo_lock, &irqL); ODM_PhyStatusQuery(&pHalData->odmpriv,pPHYInfo,(u8 *)pphy_status,&(pkt_info)); diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/rtl8723au_xmit.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/rtl8723au_xmit.c index d53be6245199..1ab9bafb7338 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/rtl8723au_xmit.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/rtl8723au_xmit.c @@ -673,15 +673,11 @@ s32 rtl8192cu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv //pxmitframe->agg_num = 1; // alloc xmitframe should assign to 1. pxmitframe->pkt_offset = 1; // first frame of aggregation, reserve offset -#ifdef IDEA_CONDITION - rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); -#else - res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); - if (res == _FALSE) { -// rtw_free_xmitframe(pxmitpriv, pxmitframe); + if (rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe) == _FALSE) { + DBG_871X("%s coalesce 1st xmitframe failed \n",__FUNCTION__); continue; } -#endif + // always return ndis_packet after rtw_xmitframe_coalesce rtw_os_xmit_complete(padapter, pxmitframe); @@ -777,15 +773,12 @@ s32 rtl8192cu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv pxmitframe->agg_num = 0; // not first frame of aggregation pxmitframe->pkt_offset = 0; // not first frame of aggregation, no need to reserve offset -#ifdef IDEA_CONDITION - rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); -#else - res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); - if (res == _FALSE) { + if (rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe) == _FALSE) { + DBG_871X("%s coalesce failed \n",__FUNCTION__); rtw_free_xmitframe(pxmitpriv, pxmitframe); continue; } -#endif + // always return ndis_packet after rtw_xmitframe_coalesce rtw_os_xmit_complete(padapter, pxmitframe); @@ -1112,7 +1105,7 @@ static void rtl8192cu_hostap_mgnt_xmit_cb(struct urb *urb) //DBG_8192C("%s\n", __FUNCTION__); - dev_kfree_skb_any(skb); + rtw_skb_free(skb); #endif } @@ -1145,11 +1138,7 @@ s32 rtl8192cu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt) if ((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_MGMT) goto _exit; -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html - pxmit_skb = dev_alloc_skb(len + TXDESC_SIZE); -#else - pxmit_skb = netdev_alloc_skb(pnetdev, len + TXDESC_SIZE); -#endif + pxmit_skb = rtw_skb_alloc(len + TXDESC_SIZE); if(!pxmit_skb) goto _exit; @@ -1230,7 +1219,7 @@ s32 rtl8192cu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt) _exit: - dev_kfree_skb_any(skb); + rtw_skb_free(skb); #endif diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/usb_halinit.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/usb_halinit.c index 2a200ff69d46..01726d1f5d40 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/usb_halinit.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/usb_halinit.c @@ -343,7 +343,10 @@ _InitQueueReservedPage( u8 value8; BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec; //u32 txQPageNum, txQPageUnit,txQRemainPage; - + + if( (pregistrypriv->wifi_spec==_TRUE) ||(pregistrypriv->qos_opt_enable==_TRUE)) + bWiFiConfig = _TRUE; + { //for WMM //RT_ASSERT((outEPNum>=2), ("for WMM ,number of out-ep must more than or equal to 2!\n")); @@ -591,9 +594,11 @@ _InitHardwareDropIncorrectBulkOut( IN PADAPTER Adapter ) { +#ifdef ENABLE_USB_DROP_INCORRECT_OUT u32 value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK); value32 |= DROP_DATA_EN; rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32); +#endif } static VOID @@ -1178,9 +1183,8 @@ static VOID _BBTurnOnBlock( #define MgntActSet_RF_State(...) static void _RfPowerSave(PADAPTER padapter) { -#if 0 - PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); - struct pwrctrl_priv *ppwrctrl = &padapter->pwrctrlpriv; + PHAL_DATA_TYPE pHalData; + struct pwrctrl_priv *pwrctrl; rt_rf_power_state eRfPowerStateToSet; u8 u1bTmp; @@ -1188,6 +1192,10 @@ static void _RfPowerSave(PADAPTER padapter) #if (DISABLE_BB_RF) return; #endif + + pHalData = GET_HAL_DATA(padapter); + pwrctrl = adapter_to_pwrctl(padapter); + // // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status // and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not @@ -1197,35 +1205,38 @@ static void _RfPowerSave(PADAPTER padapter) // in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState // is the same as eRfOff, we should change it to eRfOn after we config RF parameters. // Added by tynli. 2010.03.30. - ppwrctrl->rf_pwrstate = rf_on; - RT_CLEAR_PS_LEVEL(ppwrctrl, RT_RF_OFF_LEVL_HALT_NIC); + pwrctrl->rf_pwrstate = rf_on; + RT_CLEAR_PS_LEVEL(pwrctrl, RT_RF_OFF_LEVL_HALT_NIC); //Added by chiyokolin, 2011.10.12 for Tx rtw_write8(padapter, REG_TXPAUSE, 0x00); // 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off. // 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization. - +#if 1 + pwrctrl->b_hw_radio_off = _FALSE; + eRfPowerStateToSet = rf_on; +#else eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(padapter); - ppwrctrl->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW; - ppwrctrl->rfoff_reason |= (ppwrctrl->reg_rfoff) ? RF_CHANGE_BY_SW : 0; + pwrctrl->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW; + pwrctrl->rfoff_reason |= (pwrctrl->reg_rfoff) ? RF_CHANGE_BY_SW : 0; - if (ppwrctrl->rfoff_reason & RF_CHANGE_BY_HW) - ppwrctrl->b_hw_radio_off = _TRUE; + if (pwrctrl->rfoff_reason & RF_CHANGE_BY_HW) + pwrctrl->b_hw_radio_off = _TRUE; - if (ppwrctrl->reg_rfoff == _TRUE) + if (pwrctrl->reg_rfoff == _TRUE) { // User disable RF via registry. - RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n")); + RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s: Turn off RF for RegRfOff\n", __FUNCTION__)); MgntActSet_RF_State(padapter, rf_off, RF_CHANGE_BY_SW, _TRUE); // if (padapter->bSlaveOfDMSP) // return; } - else if (ppwrctrl->rfoff_reason > RF_CHANGE_BY_PS) + else if (pwrctrl->rfoff_reason > RF_CHANGE_BY_PS) { // H/W or S/W RF OFF before sleep. RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason)); - MgntActSet_RF_State(padapter, rf_off, ppwrctrl->rfoff_reason, _TRUE); + MgntActSet_RF_State(padapter, rf_off, pwrctrl->rfoff_reason, _TRUE); } else { @@ -1252,22 +1263,23 @@ static void _RfPowerSave(PADAPTER padapter) else #endif { - ppwrctrl->rf_pwrstate = rf_off; - ppwrctrl->rfoff_reason = RF_CHANGE_BY_INIT; - MgntActSet_RF_State(padapter, rf_on, ppwrctrl->rfoff_reason, _TRUE); + pwrctrl->rf_pwrstate = rf_off; + pwrctrl->rfoff_reason = RF_CHANGE_BY_INIT; + MgntActSet_RF_State(padapter, rf_on, pwrctrl->rfoff_reason, _TRUE); } - ppwrctrl->rfoff_reason = 0; - ppwrctrl->b_hw_radio_off = _FALSE; - ppwrctrl->rf_pwrstate = rf_on; + pwrctrl->rfoff_reason = 0; + pwrctrl->b_hw_radio_off = _FALSE; + pwrctrl->rf_pwrstate = rf_on; if (padapter->ledpriv.LedControlHandler) padapter->ledpriv.LedControlHandler(padapter, LED_CTL_POWER_ON); } - +#endif // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. if (pHalData->pwrdown && eRfPowerStateToSet == rf_off) { + DBG_871X("%s pwrdown\n", __FUNCTION__); // Enable register area 0x0-0xc. rtw_write8(padapter, REG_RSV_CTRL, 0x0); @@ -1280,7 +1292,6 @@ static void _RfPowerSave(PADAPTER padapter) u1bTmp |= WL_HWPDN_EN; rtw_write8(padapter, REG_MULTI_FUNC_CTRL, u1bTmp); } -#endif } enum { @@ -1298,7 +1309,7 @@ HalDetectPwrDownMode( { u8 tmpvalue; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter); EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_OPT3, (u32 *)&tmpvalue); @@ -1423,7 +1434,7 @@ rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter ) u8 val8; rt_rf_power_state rfpowerstate = rf_off; - if(pAdapter->pwrctrlpriv.bHWPowerdown) + if(adapter_to_pwrctl(pAdapter)->bHWPowerdown) { val8 = rtw_read8(pAdapter, REG_HSISR); DBG_8192C("pwrdown, 0x5c(BIT7)=%02x\n", val8); @@ -1446,7 +1457,7 @@ u32 rtl8723au_hal_init(PADAPTER Adapter) u8 val8 = 0; u32 boundary, status = _SUCCESS; HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); - struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv; + struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter); struct registry_priv *pregistrypriv = &Adapter->registrypriv; u8 is92C = IS_92C_SERIAL(pHalData->VersionID); rt_rf_power_state eRfPowerStateToSet; @@ -1530,7 +1541,7 @@ u32 rtl8723au_hal_init(PADAPTER Adapter) _func_enter_; HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BEGIN); - if(Adapter->pwrctrlpriv.bkeepfwalive) + if(pwrctrlpriv->bkeepfwalive) { _ps_open_RF(Adapter); @@ -1825,13 +1836,15 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02); _InitAdhocWorkaroundParams(Adapter); #endif -#if ENABLE_USB_DROP_INCORRECT_OUT _InitHardwareDropIncorrectBulkOut(Adapter); -#endif #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI) + +#ifdef CONFIG_CHECK_AC_LIFETIME // Enable lifetime check for the four ACs rtw_write8(Adapter, REG_LIFETIME_EN, 0x0F); +#endif // CONFIG_CHECK_AC_LIFETIME + #ifdef CONFIG_TX_MCAST2UNI rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); // unit: 256us. 256ms rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); // unit: 256us. 256ms @@ -2027,6 +2040,7 @@ phy_SsPwrSwitch92CU( IN int bRegSSPwrLvl ) { + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter); HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); u8 value8; @@ -2152,9 +2166,9 @@ phy_SsPwrSwitch92CU( // (2)Reg878[21:19]= 0 //Turn off RF-B // (3) RegC04[7:4]= 0 // turn off all paths for packet detection // (4) Reg800[1] = 1 // enable preamble power saving - Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord); - Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord); - Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord); + pwrctl->PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord); + pwrctl->PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord); + pwrctl->PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord); if (pHalData->rf_type == RF_2T2R) { PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0); @@ -2167,7 +2181,7 @@ phy_SsPwrSwitch92CU( PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1); // 2 .AFE control register to power down. bit[30:22] - Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord); + pwrctl->PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord); if (pHalData->rf_type == RF_2T2R) PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0); else if (pHalData->rf_type == RF_1T1R) @@ -2216,9 +2230,9 @@ phy_SsPwrSwitch92CU( // (2)Reg878[21:19]= 0 //Turn off RF-B // (3) RegC04[7:4]= 0 // turn off all paths for packet detection // (4) Reg800[1] = 1 // enable preamble power saving - Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord); - Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord); - Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord); + pwrctl->PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord); + pwrctl->PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord); + pwrctl->PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord); if (pHalData->rf_type == RF_2T2R) { PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0); @@ -2231,7 +2245,7 @@ phy_SsPwrSwitch92CU( PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1); // 2 .AFE control register to power down. bit[30:22] - Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord); + pwrctl->PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord); if (pHalData->rf_type == RF_2T2R) PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0); else if (pHalData->rf_type == RF_1T1R) @@ -3153,33 +3167,35 @@ readAntennaDiversity( // Read HW power down mode selection static void _ReadPSSetting(IN PADAPTER Adapter,IN u8*PROMContent,IN u8 AutoloadFail) { + struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(Adapter); + if(AutoloadFail){ - Adapter->pwrctrlpriv.bHWPowerdown = _FALSE; - Adapter->pwrctrlpriv.bSupportRemoteWakeup = _FALSE; + pwrctl->bHWPowerdown = _FALSE; + pwrctl->bSupportRemoteWakeup = _FALSE; } else { //if(SUPPORT_HW_RADIO_DETECT(Adapter)) - Adapter->pwrctrlpriv.bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect; + pwrctl->bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect; //else - //Adapter->pwrctrlpriv.bHWPwrPindetect = _FALSE;//dongle not support new + //pwrctl->bHWPwrPindetect = _FALSE;//dongle not support new //hw power down mode selection , 0:rf-off / 1:power down if(Adapter->registrypriv.hwpdn_mode==2) - Adapter->pwrctrlpriv.bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4); + pwrctl->bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4); else - Adapter->pwrctrlpriv.bHWPowerdown = Adapter->registrypriv.hwpdn_mode; + pwrctl->bHWPowerdown = Adapter->registrypriv.hwpdn_mode; // decide hw if support remote wakeup function // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume - Adapter->pwrctrlpriv.bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE; + pwrctl->bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE; //if(SUPPORT_HW_RADIO_DETECT(Adapter)) - //Adapter->registrypriv.usbss_enable = Adapter->pwrctrlpriv.bSupportRemoteWakeup ; + //Adapter->registrypriv.usbss_enable = pwrctl->bSupportRemoteWakeup ; DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__, - Adapter->pwrctrlpriv.bHWPwrPindetect,Adapter->pwrctrlpriv.bHWPowerdown ,Adapter->pwrctrlpriv.bSupportRemoteWakeup); + pwrctl->bHWPwrPindetect, pwrctl->bHWPowerdown, pwrctl->bSupportRemoteWakeup); DBG_8192C("### PS params=> power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable); @@ -3651,6 +3667,9 @@ _func_enter_; switch (variable) { + case HW_VAR_GET_CPWM: + *val = rtw_read8(Adapter, REG_USB_HCPWM); + break; default: GetHwReg8723A(Adapter, variable, val); break; @@ -3700,22 +3719,11 @@ GetHalDefVar8192CUsb( case HAL_DEF_DBG_DUMP_RXPKT: *(( u8*)pValue) = pHalData->bDumpRxPkt; break; - case HAL_DEF_DBG_DM_FUNC: - *(( u32*)pValue) =pHalData->odmpriv.SupportAbility; - break; case HW_VAR_MAX_RX_AMPDU_FACTOR: *(( u32*)pValue) = MAX_AMPDU_FACTOR_64K; break; - case HW_DEF_ODM_DBG_FLAG: - { - u8Byte DebugComponents = *((u32*)pValue); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - printk("pDM_Odm->DebugComponents = 0x%llx \n",pDM_Odm->DebugComponents ); - } - break; default: - //RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8192CUsb(): Unkown variable: %d!\n", eVariable)); - bResult = _FAIL; + bResult = GetHalDefVar(Adapter, eVariable, pValue); break; } @@ -3783,27 +3791,8 @@ SetHalDefVar8192CUsb( } } break; - case HW_DEF_FA_CNT_DUMP: - { - u8 bRSSIDump = *((u8*)pValue); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - if(bRSSIDump) - pDM_Odm->DebugComponents = ODM_COMP_DIG|ODM_COMP_FA_CNT ; - else - pDM_Odm->DebugComponents = 0; - - } - break; - case HW_DEF_ODM_DBG_FLAG: - { - u8Byte DebugComponents = *((u8Byte*)pValue); - PDM_ODM_T pDM_Odm = &(pHalData->odmpriv); - pDM_Odm->DebugComponents = DebugComponents; - } - break; default: - //RT_TRACE(COMP_INIT, DBG_TRACE, ("SetHalDefVar819xUsb(): Unkown variable: %d!\n", eVariable)); - bResult = _FAIL; + bResult = SetHalDefVar(Adapter, eVariable, pValue); break; } @@ -3857,10 +3846,6 @@ void UpdateHalRAMask8192CUsb(PADAPTER padapter, u32 mac_id,u8 rssi_level ) struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); -#ifdef CONFIG_CONCURRENT_MODE - if(rtw_buddy_adapter_up(padapter) && padapter->adapter_type > PRIMARY_ADAPTER) - pHalData = GET_HAL_DATA(padapter->pbuddy_adapter); -#endif //CONFIG_CONCURRENT_MODE if (mac_id >= NUM_STA) //CAM_SIZE { @@ -4002,10 +3987,17 @@ void rtl8723au_set_hal_ops(_adapter * padapter) _func_enter_; - padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE)); - if(padapter->HalData == NULL){ - DBG_8192C("cant not alloc memory for HAL DATA \n"); +#ifdef CONFIG_CONCURRENT_MODE + if(padapter->isprimary) +#endif //CONFIG_CONCURRENT_MODE + { + //set hardware operation functions + padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE)); + if(padapter->HalData == NULL){ + DBG_8192C("cant not alloc memory for HAL DATA \n"); + } } + //_rtw_memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE)); padapter->hal_data_sz = sizeof(HAL_DATA_TYPE); diff --git a/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/usb_ops_linux.c b/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/usb_ops_linux.c index 78c429248a85..375e87f9b618 100755 --- a/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/usb_ops_linux.c +++ b/drivers/net/wireless/rtl8723as/hal/rtl8723a/usb/usb_ops_linux.c @@ -66,8 +66,8 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u //DBG_871X("%s %s:%d\n",__FUNCTION__, current->comm, current->pid); - if((padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx)){ - RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq:(padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n")); + if((padapter->bSurpriseRemoved) ||(dvobj_to_pwrctl(pdvobjpriv)->pnp_bstop_trx)){ + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq:(padapter->bSurpriseRemoved ||pwrctl->pnp_bstop_trx)!!!\n")); status = -EPERM; goto exit; } @@ -133,7 +133,7 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u if ( status == len) // Success this control transfer. { - rtw_reset_continual_urb_error(pdvobjpriv); + rtw_reset_continual_io_error(pdvobjpriv); if ( requesttype == 0x01 ) { // For Control read transfer, we have to copy the read data from pIo_buf to pdata. _rtw_memcpy( pdata, pIo_buf, len ); @@ -166,7 +166,7 @@ static int usbctrl_vendorreq(struct intf_hdl *pintfhdl, u8 request, u16 value, u } } - if(rtw_inc_and_chk_continual_urb_error(pdvobjpriv) == _TRUE ){ + if(rtw_inc_and_chk_continual_io_error(pdvobjpriv) == _TRUE ){ padapter->bSurpriseRemoved = _TRUE; break; } @@ -526,7 +526,7 @@ InterruptRecognized8723AU( if( ((pHalData->IntArray[0])&UHIMR_CPWM)){ // DBG_8192C("%s HIMR=0x%x\n",__func__,pHalData->IntArray[0]); //cpwm_int_hdl(Adapter, &report); - _set_workitem(&Adapter->pwrctrlpriv.cpwm_event); + _set_workitem(&(adapter_to_pwrctl(Adapter)->cpwm_event)); pHalData->IntArray[0]&= ~UHIMR_CPWM; // DBG_8192C("%s HIMR=0x%x\n",__func__,pHalData->IntArray[0]); } @@ -710,7 +710,10 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf) pattrib = &precvframe->u.hdr.attrib; if(pattrib->crc_err){ - DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__); + if (padapter->registrypriv.mp_mode == 1) + padapter->mppriv.rx_crcerrpktcount++; + else + DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__); rtw_free_recvframe(precvframe, pfree_recv_queue); goto _exit_recvbuf2recvframe; } @@ -754,11 +757,8 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf) alloc_sz += 14; } -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html - pkt_copy = dev_alloc_skb(alloc_sz); -#else - pkt_copy = netdev_alloc_skb(padapter->pnetdev, alloc_sz); -#endif + pkt_copy = rtw_skb_alloc(alloc_sz); + if(pkt_copy) { pkt_copy->dev = padapter->pnetdev; @@ -773,7 +773,7 @@ static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf) else { DBG_8192C("recvbuf2recvframe:can not allocate memory for skb copy\n"); - //precvframe->u.hdr.pkt = skb_clone(pskb, GFP_ATOMIC); + //precvframe->u.hdr.pkt = rtw_skb_clone(pskb); //precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf; //precvframe->u.hdr.rx_end = pbuf + (pkt_offset>1612?pkt_offset:1612); @@ -879,7 +879,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) } else { - rtw_reset_continual_urb_error(adapter_to_dvobj(padapter)); + rtw_reset_continual_io_error(adapter_to_dvobj(padapter)); precvbuf->transfer_len = purb->actual_length; @@ -895,7 +895,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status); - if(rtw_inc_and_chk_continual_urb_error(adapter_to_dvobj(padapter)) == _TRUE ){ + if(rtw_inc_and_chk_continual_io_error(adapter_to_dvobj(padapter)) == _TRUE ){ padapter->bSurpriseRemoved = _TRUE; } @@ -911,6 +911,9 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n")); break; case -EPROTO: + case -EILSEQ: + case -ETIME: + case -ECOMM: case -EOVERFLOW: #ifdef DBG_CONFIG_ERROR_DETECT { @@ -949,9 +952,9 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) _func_enter_; - if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx) + if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||dvobj_to_pwrctl(pdvobj)->pnp_bstop_trx) { - RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n")); + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||pwrctl->pnp_bstop_trx)!!!\n")); return _FAIL; } @@ -1158,11 +1161,8 @@ static s32 pre_recv_entry(union recv_frame *precvframe, struct recv_stat *prxsta alloc_sz += 14; } -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html - pkt_copy = dev_alloc_skb(alloc_sz); -#else - pkt_copy = netdev_alloc_skb(secondary_padapter->pnetdev, alloc_sz); -#endif + pkt_copy = rtw_skb_alloc(alloc_sz); + if(pkt_copy) { pkt_copy->dev = secondary_padapter->pnetdev; @@ -1257,7 +1257,10 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb) pattrib = &precvframe->u.hdr.attrib; if(pattrib->crc_err){ - DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__); + if (padapter->registrypriv.mp_mode == 1) + padapter->mppriv.rx_crcerrpktcount++; + else + DBG_8192C("%s()-%d: RX Warning! rx CRC ERROR !!\n", __FUNCTION__, __LINE__); rtw_free_recvframe(precvframe, pfree_recv_queue); goto _exit_recvbuf2recvframe; } @@ -1301,11 +1304,8 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb) alloc_sz += 14; } -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html - pkt_copy = dev_alloc_skb(alloc_sz); -#else - pkt_copy = netdev_alloc_skb(padapter->pnetdev, alloc_sz); -#endif + pkt_copy = rtw_skb_alloc(alloc_sz); + if(pkt_copy) { pkt_copy->dev = padapter->pnetdev; @@ -1326,7 +1326,7 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb) goto _exit_recvbuf2recvframe; } - precvframe->u.hdr.pkt = skb_clone(pskb, GFP_ATOMIC); + precvframe->u.hdr.pkt = rtw_skb_clone(pskb); if(precvframe->u.hdr.pkt) { precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail @@ -1335,7 +1335,7 @@ static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb) } else { - DBG_8192C("recvbuf2recvframe: skb_clone fail\n"); + DBG_8192C("recvbuf2recvframe: rtw_skb_clone fail\n"); rtw_free_recvframe(precvframe, pfree_recv_queue); goto _exit_recvbuf2recvframe; } @@ -1406,7 +1406,7 @@ void rtl8192cu_recv_tasklet(void *priv) if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE)) { DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n"); - dev_kfree_skb_any(pskb); + rtw_skb_free(pskb); break; } @@ -1421,7 +1421,7 @@ void rtl8192cu_recv_tasklet(void *priv) skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb); #else - dev_kfree_skb_any(pskb); + rtw_skb_free(pskb); #endif } @@ -1461,7 +1461,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) #else if(precvbuf->pskb){ DBG_8192C("==> free skb(%p)\n",precvbuf->pskb); - dev_kfree_skb_any(precvbuf->pskb); + rtw_skb_free(precvbuf->pskb); } #endif DBG_8192C("%s()-%d: RX Warning! bDriverStopped(%d) OR bSurpriseRemoved(%d) bReadPortCancel(%d)\n", @@ -1480,7 +1480,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) } else { - rtw_reset_continual_urb_error(adapter_to_dvobj(padapter)); + rtw_reset_continual_io_error(adapter_to_dvobj(padapter)); precvbuf->transfer_len = purb->actual_length; skb_put(precvbuf->pskb, purb->actual_length); @@ -1500,7 +1500,7 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status); - if(rtw_inc_and_chk_continual_urb_error(adapter_to_dvobj(padapter)) == _TRUE ){ + if(rtw_inc_and_chk_continual_io_error(adapter_to_dvobj(padapter)) == _TRUE ){ padapter->bSurpriseRemoved = _TRUE; } @@ -1516,6 +1516,9 @@ static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n")); break; case -EPROTO: + case -EILSEQ: + case -ETIME: + case -ECOMM: case -EOVERFLOW: #ifdef DBG_CONFIG_ERROR_DETECT { @@ -1559,9 +1562,9 @@ static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) _func_enter_; - if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx) + if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||dvobj_to_pwrctl(pdvobj)->pnp_bstop_trx) { - RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n")); + RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||pwrctl->pnp_bstop_trx)!!!\n")); return _FAIL; } @@ -1583,12 +1586,8 @@ _func_enter_; //re-assign for linux based on skb if((precvbuf->reuse == _FALSE) || (precvbuf->pskb == NULL)) { - //precvbuf->pskb = alloc_skb(MAX_RECVBUF_SZ, GFP_ATOMIC);//don't use this after v2.6.25 -#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html - precvbuf->pskb = dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); -#else - precvbuf->pskb = netdev_alloc_skb(adapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); -#endif + precvbuf->pskb = rtw_skb_alloc(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); + if(precvbuf->pskb == NULL) { RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("init_recvbuf(): alloc_skb fail!\n")); |