ENGR00117389 Port 5.0.0 release to 2.6.31

This is i.MX BSP 5.0.0 release ported to 2.6.31

Signed-off-by: Rob Herring <r.herring@freescale.com>
Signed-off-by: Alan Tull <r80115@freescale.com>
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>

12 files changed, 3752 insertions, 3 deletions

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 5ce7cbabd7a7..f5544c33b915 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -1439,7 +1439,7 @@ config FORCEDETH_NAPI
 config CS89x0
 	tristate "CS89x0 support"
 	depends on NET_ETHERNET && (ISA || EISA || MACH_IXDP2351 \
-		|| ARCH_IXDP2X01 || ARCH_PNX010X || MACH_MX31ADS)
+		|| ARCH_IXDP2X01 || ARCH_PNX010X || ARCH_MXC)
 	---help---
 	  Support for CS89x0 chipset based Ethernet cards. If you have a
 	  network (Ethernet) card of this type, say Y and read the
@@ -1453,7 +1453,7 @@ config CS89x0
 config CS89x0_NONISA_IRQ
 	def_bool y
 	depends on CS89x0 != n
-	depends on MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X || MACH_MX31ADS
+	depends on MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X || ARCH_MXC
 
 config TC35815
 	tristate "TOSHIBA TC35815 Ethernet support"
@@ -1875,7 +1875,7 @@ config 68360_ENET
 
 config FEC
 	bool "FEC ethernet controller (of ColdFire and some i.MX CPUs)"
-	depends on M523x || M527x || M5272 || M528x || M520x || M532x || MACH_MX27 || ARCH_MX35
+	depends on M523x || M527x || M5272 || M528x || M520x || M532x || ARCH_MX25 || MACH_MX27 || ARCH_MX35 || ARCH_MX51
 	help
 	  Say Y here if you want to use the built-in 10/100 Fast ethernet
 	  controller on some Motorola ColdFire and Freescale i.MX processors.
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 33821a81cbf8..b7b101e3a884 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -84,4 +84,13 @@ config CAN_DEBUG_DEVICES
 	  a problem with CAN support and want to see more of what is going
 	  on.
 
+config CAN_FLEXCAN
+        tristate "Freescale FlexCAN"
+        depends on CAN && (ARCH_MX25 || ARCH_MX35)
+        default m
+        ---help---
+          This select the support of Freescale CAN(FlexCAN).
+          This driver can also be built as a module.
+          If unsure, say N.
+
 endmenu
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 523a941b358b..22ea529fb46e 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -3,6 +3,7 @@
 #
 
 obj-$(CONFIG_CAN_VCAN)		+= vcan.o
+obj-$(CONFIG_CAN_FLEXCAN)	+= flexcan/
 
 obj-$(CONFIG_CAN_DEV)		+= can-dev.o
 can-dev-y			:= dev.o
diff --git a/drivers/net/can/flexcan/Makefile b/drivers/net/can/flexcan/Makefile
new file mode 100644
index 000000000000..b2dbb4fb2793
--- /dev/null
+++ b/drivers/net/can/flexcan/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_CAN_FLEXCAN)	+= flexcan.o
+
+flexcan-y := dev.o drv.o mbm.o
diff --git a/drivers/net/can/flexcan/dev.c b/drivers/net/can/flexcan/dev.c
new file mode 100644
index 000000000000..f8386e5effa9
--- /dev/null
+++ b/drivers/net/can/flexcan/dev.c
@@ -0,0 +1,619 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file dev.c
+ *
+ * @brief Driver for Freescale CAN Controller FlexCAN.
+ *
+ * @ingroup can
+ */
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/unistd.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/spinlock.h>
+#include <linux/device.h>
+
+#include <linux/module.h>
+#include <mach/hardware.h>
+#include "flexcan.h"
+
+enum {
+	FLEXCAN_ATTR_STATE = 0,
+	FLEXCAN_ATTR_BITRATE,
+	FLEXCAN_ATTR_BR_PRESDIV,
+	FLEXCAN_ATTR_BR_RJW,
+	FLEXCAN_ATTR_BR_PROPSEG,
+	FLEXCAN_ATTR_BR_PSEG1,
+	FLEXCAN_ATTR_BR_PSEG2,
+	FLEXCAN_ATTR_BR_CLKSRC,
+	FLEXCAN_ATTR_MAXMB,
+	FLEXCAN_ATTR_XMIT_MAXMB,
+	FLEXCAN_ATTR_FIFO,
+	FLEXCAN_ATTR_WAKEUP,
+	FLEXCAN_ATTR_SRX_DIS,
+	FLEXCAN_ATTR_WAK_SRC,
+	FLEXCAN_ATTR_BCC,
+	FLEXCAN_ATTR_LOCAL_PRIORITY,
+	FLEXCAN_ATTR_ABORT,
+	FLEXCAN_ATTR_LOOPBACK,
+	FLEXCAN_ATTR_SMP,
+	FLEXCAN_ATTR_BOFF_REC,
+	FLEXCAN_ATTR_TSYN,
+	FLEXCAN_ATTR_LISTEN,
+	FLEXCAN_ATTR_EXTEND_MSG,
+	FLEXCAN_ATTR_STANDARD_MSG,
+#ifdef CONFIG_CAN_DEBUG_DEVICES
+	FLEXCAN_ATTR_DUMP_REG,
+	FLEXCAN_ATTR_DUMP_XMIT_MB,
+	FLEXCAN_ATTR_DUMP_RX_MB,
+#endif
+	FLEXCAN_ATTR_MAX
+};
+
+static ssize_t flexcan_show_attr(struct device *dev,
+				 struct device_attribute *attr, char *buf);
+static ssize_t flexcan_set_attr(struct device *dev,
+				struct device_attribute *attr, const char *buf,
+				size_t count);
+
+static struct device_attribute flexcan_dev_attr[FLEXCAN_ATTR_MAX] = {
+	[FLEXCAN_ATTR_STATE] = __ATTR(state, 0444, flexcan_show_attr, NULL),
+	[FLEXCAN_ATTR_BITRATE] =
+	    __ATTR(bitrate, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BR_PRESDIV] =
+	    __ATTR(br_presdiv, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BR_RJW] =
+	    __ATTR(br_rjw, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BR_PROPSEG] =
+	    __ATTR(br_propseg, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BR_PSEG1] =
+	    __ATTR(br_pseg1, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BR_PSEG2] =
+	    __ATTR(br_pseg2, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BR_CLKSRC] =
+	    __ATTR(br_clksrc, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_MAXMB] =
+	    __ATTR(maxmb, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_XMIT_MAXMB] =
+	    __ATTR(xmit_maxmb, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_FIFO] =
+	    __ATTR(fifo, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_WAKEUP] =
+	    __ATTR(wakeup, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_SRX_DIS] =
+	    __ATTR(srx_dis, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_WAK_SRC] =
+	    __ATTR(wak_src, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BCC] =
+	    __ATTR(bcc, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_LOCAL_PRIORITY] =
+	    __ATTR(local_priority, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_ABORT] =
+	    __ATTR(abort, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_LOOPBACK] =
+	    __ATTR(loopback, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_SMP] =
+	    __ATTR(smp, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_BOFF_REC] =
+	    __ATTR(boff_rec, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_TSYN] =
+	    __ATTR(tsyn, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_LISTEN] =
+	    __ATTR(listen, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_EXTEND_MSG] =
+	    __ATTR(ext_msg, 0644, flexcan_show_attr, flexcan_set_attr),
+	[FLEXCAN_ATTR_STANDARD_MSG] =
+	    __ATTR(std_msg, 0644, flexcan_show_attr, flexcan_set_attr),
+#ifdef CONFIG_CAN_DEBUG_DEVICES
+	[FLEXCAN_ATTR_DUMP_REG] =
+	    __ATTR(dump_reg, 0444, flexcan_show_attr, NULL),
+	[FLEXCAN_ATTR_DUMP_XMIT_MB] =
+	    __ATTR(dump_xmit_mb, 0444, flexcan_show_attr, NULL),
+	[FLEXCAN_ATTR_DUMP_RX_MB] =
+	    __ATTR(dump_rx_mb, 0444, flexcan_show_attr, NULL),
+#endif
+};
+
+static void flexcan_set_bitrate(struct flexcan_device *flexcan, int bitrate)
+{
+	/* TODO:: implement in future
+	 * based on the bitrate to get the timing of
+	 * presdiv, pseg1, pseg2, propseg
+	 */
+}
+
+static void flexcan_update_bitrate(struct flexcan_device *flexcan)
+{
+	int rate, div;
+
+	if (flexcan->br_clksrc)
+		rate = clk_get_rate(flexcan->clk);
+	else {
+		struct clk *clk;
+		clk = clk_get(NULL, "ckih");
+		if (!clk)
+			return;
+		rate = clk_get_rate(clk);
+		clk_put(clk);
+	}
+	if (!rate)
+		return;
+
+	div = (flexcan->br_presdiv + 1);
+	div *=
+	    (flexcan->br_propseg + flexcan->br_pseg1 + flexcan->br_pseg2 + 4);
+	flexcan->bitrate = (rate + div - 1) / div;
+}
+
+#ifdef CONFIG_CAN_DEBUG_DEVICES
+static int flexcan_dump_reg(struct flexcan_device *flexcan, char *buf)
+{
+	int ret = 0;
+	unsigned int reg;
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	ret += sprintf(buf + ret, "MCR::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_CTRL);
+	ret += sprintf(buf + ret, "CTRL::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_RXGMASK);
+	ret += sprintf(buf + ret, "RXGMASK::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_RX14MASK);
+	ret += sprintf(buf + ret, "RX14MASK::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_RX15MASK);
+	ret += sprintf(buf + ret, "RX15MASK::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_ECR);
+	ret += sprintf(buf + ret, "ECR::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR);
+	ret += sprintf(buf + ret, "ESR::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK2);
+	ret += sprintf(buf + ret, "IMASK2::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK1);
+	ret += sprintf(buf + ret, "IMASK1::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG2);
+	ret += sprintf(buf + ret, "IFLAG2::0x%x\n", reg);
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG1);
+	ret += sprintf(buf + ret, "IFLAG1::0x%x\n", reg);
+	return ret;
+}
+
+static int flexcan_dump_xmit_mb(struct flexcan_device *flexcan, char *buf)
+{
+	int ret = 0, i;
+	i = flexcan->xmit_maxmb + 1;
+	for (; i <= flexcan->maxmb; i++)
+		ret +=
+		    sprintf(buf + ret,
+			    "mb[%d]::CS:0x%x ID:0x%x DATA[1~2]:0x%02x,0x%02x\n",
+			    i, flexcan->hwmb[i].mb_cs.data,
+			    flexcan->hwmb[i].mb_id, flexcan->hwmb[i].mb_data[1],
+			    flexcan->hwmb[i].mb_data[2]);
+	return ret;
+}
+
+static int flexcan_dump_rx_mb(struct flexcan_device *flexcan, char *buf)
+{
+	int ret = 0, i;
+	for (i = 0; i <= flexcan->xmit_maxmb; i++)
+		ret +=
+		    sprintf(buf + ret,
+			    "mb[%d]::CS:0x%x ID:0x%x DATA[1~2]:0x%02x,0x%02x\n",
+			    i, flexcan->hwmb[i].mb_cs.data,
+			    flexcan->hwmb[i].mb_id, flexcan->hwmb[i].mb_data[1],
+			    flexcan->hwmb[i].mb_data[2]);
+	return ret;
+}
+#endif
+
+static ssize_t flexcan_show_state(struct net_device *net, char *buf)
+{
+	int ret, esr;
+	struct flexcan_device *flexcan = netdev_priv(net);
+	ret = sprintf(buf, "%s::", netif_running(net) ? "Start" : "Stop");
+	if (netif_carrier_ok(net)) {
+		esr = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR);
+		switch ((esr & __ESR_FLT_CONF_MASK) >> __ESR_FLT_CONF_OFF) {
+		case 0:
+			ret += sprintf(buf + ret, "normal\n");
+			break;
+		case 1:
+			ret += sprintf(buf + ret, "error passive\n");
+			break;
+		default:
+			ret += sprintf(buf + ret, "bus off\n");
+		}
+	} else
+		ret += sprintf(buf + ret, "bus off\n");
+	return ret;
+}
+
+static ssize_t flexcan_show_attr(struct device *dev,
+				 struct device_attribute *attr, char *buf)
+{
+	int attr_id;
+	struct net_device *net;
+	struct flexcan_device *flexcan;
+
+	net = dev_get_drvdata(dev);
+	BUG_ON(!net);
+	flexcan = netdev_priv(net);
+	BUG_ON(!flexcan);
+
+	attr_id = attr - flexcan_dev_attr;
+	switch (attr_id) {
+	case FLEXCAN_ATTR_STATE:
+		return flexcan_show_state(net, buf);
+	case FLEXCAN_ATTR_BITRATE:
+		return sprintf(buf, "%d\n", flexcan->bitrate);
+	case FLEXCAN_ATTR_BR_PRESDIV:
+		return sprintf(buf, "%d\n", flexcan->br_presdiv + 1);
+	case FLEXCAN_ATTR_BR_RJW:
+		return sprintf(buf, "%d\n", flexcan->br_rjw);
+	case FLEXCAN_ATTR_BR_PROPSEG:
+		return sprintf(buf, "%d\n", flexcan->br_propseg + 1);
+	case FLEXCAN_ATTR_BR_PSEG1:
+		return sprintf(buf, "%d\n", flexcan->br_pseg1 + 1);
+	case FLEXCAN_ATTR_BR_PSEG2:
+		return sprintf(buf, "%d\n", flexcan->br_pseg2 + 1);
+	case FLEXCAN_ATTR_BR_CLKSRC:
+		return sprintf(buf, "%s\n", flexcan->br_clksrc ? "bus" : "osc");
+	case FLEXCAN_ATTR_MAXMB:
+		return sprintf(buf, "%d\n", flexcan->maxmb + 1);
+	case FLEXCAN_ATTR_XMIT_MAXMB:
+		return sprintf(buf, "%d\n", flexcan->xmit_maxmb + 1);
+	case FLEXCAN_ATTR_FIFO:
+		return sprintf(buf, "%d\n", flexcan->fifo);
+	case FLEXCAN_ATTR_WAKEUP:
+		return sprintf(buf, "%d\n", flexcan->wakeup);
+	case FLEXCAN_ATTR_SRX_DIS:
+		return sprintf(buf, "%d\n", flexcan->srx_dis);
+	case FLEXCAN_ATTR_WAK_SRC:
+		return sprintf(buf, "%d\n", flexcan->wak_src);
+	case FLEXCAN_ATTR_BCC:
+		return sprintf(buf, "%d\n", flexcan->bcc);
+	case FLEXCAN_ATTR_LOCAL_PRIORITY:
+		return sprintf(buf, "%d\n", flexcan->lprio);
+	case FLEXCAN_ATTR_ABORT:
+		return sprintf(buf, "%d\n", flexcan->abort);
+	case FLEXCAN_ATTR_LOOPBACK:
+		return sprintf(buf, "%d\n", flexcan->loopback);
+	case FLEXCAN_ATTR_SMP:
+		return sprintf(buf, "%d\n", flexcan->smp);
+	case FLEXCAN_ATTR_BOFF_REC:
+		return sprintf(buf, "%d\n", flexcan->boff_rec);
+	case FLEXCAN_ATTR_TSYN:
+		return sprintf(buf, "%d\n", flexcan->tsyn);
+	case FLEXCAN_ATTR_LISTEN:
+		return sprintf(buf, "%d\n", flexcan->listen);
+	case FLEXCAN_ATTR_EXTEND_MSG:
+		return sprintf(buf, "%d\n", flexcan->ext_msg);
+	case FLEXCAN_ATTR_STANDARD_MSG:
+		return sprintf(buf, "%d\n", flexcan->std_msg);
+#ifdef CONFIG_CAN_DEBUG_DEVICES
+	case FLEXCAN_ATTR_DUMP_REG:
+		return flexcan_dump_reg(flexcan, buf);
+	case FLEXCAN_ATTR_DUMP_XMIT_MB:
+		return flexcan_dump_xmit_mb(flexcan, buf);
+	case FLEXCAN_ATTR_DUMP_RX_MB:
+		return flexcan_dump_rx_mb(flexcan, buf);
+#endif
+	default:
+		return sprintf(buf, "%s:%p->%p\n", __func__, flexcan_dev_attr,
+			       attr);
+	}
+}
+
+static ssize_t flexcan_set_attr(struct device *dev,
+				struct device_attribute *attr, const char *buf,
+				size_t count)
+{
+	int attr_id, tmp;
+	struct net_device *net;
+	struct flexcan_device *flexcan;
+
+	net = dev_get_drvdata(dev);
+	BUG_ON(!net);
+	flexcan = netdev_priv(net);
+	BUG_ON(!flexcan);
+
+	attr_id = attr - flexcan_dev_attr;
+
+	if (mutex_lock_interruptible(&flexcan->mutex))
+		return count;
+
+	if (netif_running(net))
+		goto set_finish;
+
+	if (attr_id == FLEXCAN_ATTR_BR_CLKSRC) {
+		if (!strcasecmp(buf, "bus"))
+			flexcan->br_clksrc = 1;
+		else if (!strcasecmp(buf, "osc"))
+			flexcan->br_clksrc = 0;
+		goto set_finish;
+	}
+
+	tmp = simple_strtoul(buf, NULL, 0);
+	switch (attr_id) {
+	case FLEXCAN_ATTR_BITRATE:
+		flexcan_set_bitrate(flexcan, tmp);
+		break;
+	case FLEXCAN_ATTR_BR_PRESDIV:
+		if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PRESDIV)) {
+			flexcan->br_presdiv = tmp - 1;
+			flexcan_update_bitrate(flexcan);
+		}
+		break;
+	case FLEXCAN_ATTR_BR_RJW:
+		if ((tmp > 0) && (tmp <= FLEXCAN_MAX_RJW))
+			flexcan->br_rjw = tmp - 1;
+		break;
+	case FLEXCAN_ATTR_BR_PROPSEG:
+		if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PROPSEG)) {
+			flexcan->br_propseg = tmp - 1;
+			flexcan_update_bitrate(flexcan);
+		}
+		break;
+	case FLEXCAN_ATTR_BR_PSEG1:
+		if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PSEG1)) {
+			flexcan->br_pseg1 = tmp - 1;
+			flexcan_update_bitrate(flexcan);
+		}
+		break;
+	case FLEXCAN_ATTR_BR_PSEG2:
+		if ((tmp > 0) && (tmp <= FLEXCAN_MAX_PSEG2)) {
+			flexcan->br_pseg2 = tmp - 1;
+			flexcan_update_bitrate(flexcan);
+		}
+		break;
+	case FLEXCAN_ATTR_MAXMB:
+		if ((tmp > 0) && (tmp <= FLEXCAN_MAX_MB)) {
+			if (flexcan->maxmb != (tmp - 1)) {
+				flexcan->maxmb = tmp - 1;
+				if (flexcan->xmit_maxmb < flexcan->maxmb)
+					flexcan->xmit_maxmb = flexcan->maxmb;
+			}
+		}
+		break;
+	case FLEXCAN_ATTR_XMIT_MAXMB:
+		if ((tmp > 0) && (tmp <= (flexcan->maxmb + 1))) {
+			if (flexcan->xmit_maxmb != (tmp - 1))
+				flexcan->xmit_maxmb = tmp - 1;
+		}
+		break;
+	case FLEXCAN_ATTR_FIFO:
+		flexcan->fifo = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_WAKEUP:
+		flexcan->wakeup = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_SRX_DIS:
+		flexcan->srx_dis = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_WAK_SRC:
+		flexcan->wak_src = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_BCC:
+		flexcan->bcc = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_LOCAL_PRIORITY:
+		flexcan->lprio = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_ABORT:
+		flexcan->abort = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_LOOPBACK:
+		flexcan->loopback = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_SMP:
+		flexcan->smp = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_BOFF_REC:
+		flexcan->boff_rec = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_TSYN:
+		flexcan->tsyn = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_LISTEN:
+		flexcan->listen = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_EXTEND_MSG:
+		flexcan->ext_msg = tmp ? 1 : 0;
+		break;
+	case FLEXCAN_ATTR_STANDARD_MSG:
+		flexcan->std_msg = tmp ? 1 : 0;
+		break;
+	}
+      set_finish:
+	mutex_unlock(&flexcan->mutex);
+	return count;
+}
+
+static void flexcan_device_default(struct flexcan_device *dev)
+{
+	dev->br_clksrc = 1;
+	dev->br_rjw = 2;
+	dev->br_presdiv = 6;
+	dev->br_propseg = 4;
+	dev->br_pseg1 = 4;
+	dev->br_pseg2 = 7;
+
+	dev->bcc = 1;
+	dev->srx_dis = 1;
+	dev->smp = 1;
+	dev->boff_rec = 1;
+
+	dev->maxmb = FLEXCAN_MAX_MB - 1;
+	dev->xmit_maxmb = (FLEXCAN_MAX_MB >> 1) - 1;
+	dev->xmit_mb = dev->maxmb - dev->xmit_maxmb;
+
+	dev->ext_msg = 1;
+	dev->std_msg = 1;
+}
+
+static int flexcan_device_attach(struct flexcan_device *flexcan)
+{
+	int ret;
+	struct resource *res;
+	struct platform_device *pdev = flexcan->dev;
+	struct flexcan_platform_data *plat_data = (pdev->dev).platform_data;
+
+	res = platform_get_resource(flexcan->dev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	flexcan->io_base = ioremap(res->start, res->end - res->start + 1);
+	if (!flexcan->io_base)
+		return -ENOMEM;
+
+	flexcan->irq = platform_get_irq(flexcan->dev, 0);
+	if (!flexcan->irq) {
+		ret = -ENODEV;
+		goto no_irq_err;
+	}
+
+	ret = -EINVAL;
+	if (plat_data) {
+		if (plat_data->core_reg) {
+			flexcan->core_reg = regulator_get(&pdev->dev,
+							  plat_data->core_reg);
+			if (!flexcan->core_reg)
+				goto plat_err;
+		}
+
+		if (plat_data->io_reg) {
+			flexcan->io_reg = regulator_get(&pdev->dev,
+							plat_data->io_reg);
+			if (!flexcan->io_reg)
+				goto plat_err;
+		}
+	}
+	flexcan->clk = clk_get(&(flexcan->dev)->dev, "can_clk");
+	flexcan->hwmb = (struct can_hw_mb *)(flexcan->io_base + CAN_MB_BASE);
+	flexcan->rx_mask = (unsigned int *)(flexcan->io_base + CAN_RXMASK_BASE);
+
+	return 0;
+      plat_err:
+	if (flexcan->core_reg) {
+		regulator_put(flexcan->core_reg);
+		flexcan->core_reg = NULL;
+	}
+      no_irq_err:
+	if (flexcan->io_base)
+		iounmap(flexcan->io_base);
+	return ret;
+}
+
+static void flexcan_device_detach(struct flexcan_device *flexcan)
+{
+	if (flexcan->clk) {
+		clk_put(flexcan->clk);
+		flexcan->clk = NULL;
+	}
+
+	if (flexcan->io_reg) {
+		regulator_put(flexcan->io_reg);
+		flexcan->io_reg = NULL;
+	}
+
+	if (flexcan->core_reg) {
+		regulator_put(flexcan->core_reg);
+		flexcan->core_reg = NULL;
+	}
+
+	if (flexcan->io_base)
+		iounmap(flexcan->io_base);
+}
+
+/*!
+ * @brief The function allocates can device.
+ *
+ * @param pdev	the pointer of platform device.
+ * @param setup	the initial function pointer of network device.
+ *
+ * @return none
+ */
+struct net_device *flexcan_device_alloc(struct platform_device *pdev,
+					void (*setup) (struct net_device *dev))
+{
+	struct flexcan_device *flexcan;
+	struct net_device *net;
+	int i, num;
+
+	net = alloc_netdev(sizeof(*flexcan), "can%d", setup);
+	if (net == NULL) {
+		printk(KERN_ERR "Allocate netdevice for FlexCAN fail!\n");
+		return NULL;
+	}
+	flexcan = netdev_priv(net);
+	memset(flexcan, 0, sizeof(*flexcan));
+
+	mutex_init(&flexcan->mutex);
+	init_timer(&flexcan->timer);
+
+	flexcan->dev = pdev;
+	if (flexcan_device_attach(flexcan)) {
+		printk(KERN_ERR "Attach FlexCAN fail!\n");
+		free_netdev(net);
+		return NULL;
+	}
+	flexcan_device_default(flexcan);
+	flexcan_update_bitrate(flexcan);
+
+	num = ARRAY_SIZE(flexcan_dev_attr);
+
+	for (i = 0; i < num; i++) {
+		if (device_create_file(&pdev->dev, flexcan_dev_attr + i)) {
+			printk(KERN_ERR "Create attribute file fail!\n");
+			break;
+		}
+	}
+
+	if (i != num) {
+		for (; i >= 0; i--)
+			device_remove_file(&pdev->dev, flexcan_dev_attr + i);
+		free_netdev(net);
+		return NULL;
+	}
+	dev_set_drvdata(&pdev->dev, net);
+	return net;
+}
+
+/*!
+ * @brief The function frees can device.
+ *
+ * @param pdev	the pointer of platform device.
+ *
+ * @return none
+ */
+void flexcan_device_free(struct platform_device *pdev)
+{
+	struct net_device *net;
+	struct flexcan_device *flexcan;
+	int i, num;
+	net = (struct net_device *)dev_get_drvdata(&pdev->dev);
+
+	unregister_netdev(net);
+	flexcan = netdev_priv(net);
+	del_timer(&flexcan->timer);
+
+	num = ARRAY_SIZE(flexcan_dev_attr);
+
+	for (i = 0; i < num; i++)
+		device_remove_file(&pdev->dev, flexcan_dev_attr + i);
+
+	flexcan_device_detach(netdev_priv(net));
+	free_netdev(net);
+}
diff --git a/drivers/net/can/flexcan/drv.c b/drivers/net/can/flexcan/drv.c
new file mode 100644
index 000000000000..342b52a129c2
--- /dev/null
+++ b/drivers/net/can/flexcan/drv.c
@@ -0,0 +1,628 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file drv.c
+ *
+ * @brief Driver for Freescale CAN Controller FlexCAN.
+ *
+ * @ingroup can
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/netdevice.h>
+#include <linux/if_arp.h>
+#include <linux/if_ether.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include "flexcan.h"
+
+static void flexcan_hw_start(struct flexcan_device *flexcan)
+{
+	unsigned int reg;
+	if ((flexcan->maxmb + 1) > 32) {
+		__raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IMASK1);
+		reg = (1 << (flexcan->maxmb - 31)) - 1;
+		__raw_writel(reg, flexcan->io_base + CAN_HW_REG_IMASK2);
+	} else {
+		reg = (1 << (flexcan->maxmb + 1)) - 1;
+		__raw_writel(reg, flexcan->io_base + CAN_HW_REG_IMASK1);
+		__raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK2);
+	}
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR) & (~__MCR_HALT);
+	__raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR);
+}
+
+static void flexcan_hw_stop(struct flexcan_device *flexcan)
+{
+	unsigned int reg;
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	__raw_writel(reg | __MCR_HALT, flexcan->io_base + CAN_HW_REG_MCR);
+}
+
+static int flexcan_hw_reset(struct flexcan_device *flexcan)
+{
+	unsigned int reg;
+	int timeout = 100000;
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	__raw_writel(reg | __MCR_MDIS, flexcan->io_base + CAN_HW_REG_MCR);
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_CTRL);
+	if (flexcan->br_clksrc)
+		reg |= __CTRL_CLK_SRC;
+	else
+		reg &= ~__CTRL_CLK_SRC;
+	__raw_writel(reg, flexcan->io_base + CAN_HW_REG_CTRL);
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR) & (~__MCR_MDIS);
+	__raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR);
+	reg |= __MCR_SOFT_RST;
+	__raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR);
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	while (reg & __MCR_SOFT_RST) {
+		if (--timeout <= 0) {
+			printk(KERN_ERR "Flexcan software Reset Timeouted\n");
+			return -1;
+		}
+		udelay(10);
+		reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	}
+	return 0;
+}
+
+static inline void flexcan_mcr_setup(struct flexcan_device *flexcan)
+{
+	unsigned int reg;
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	reg &= ~(__MCR_MAX_MB_MASK | __MCR_WAK_MSK | __MCR_MAX_IDAM_MASK);
+
+	if (flexcan->fifo)
+		reg |= __MCR_FEN;
+	else
+		reg &= ~__MCR_FEN;
+
+	if (flexcan->wakeup)
+		reg |= __MCR_SLF_WAK | __MCR_WAK_MSK;
+	else
+		reg &= ~(__MCR_SLF_WAK | __MCR_WAK_MSK);
+
+	if (flexcan->wak_src)
+		reg |= __MCR_WAK_SRC;
+	else
+		reg &= ~__MCR_WAK_SRC;
+
+	if (flexcan->srx_dis)
+		reg |= __MCR_SRX_DIS;
+	else
+		reg &= ~__MCR_SRX_DIS;
+
+	if (flexcan->bcc)
+		reg |= __MCR_BCC;
+	else
+		reg &= ~__MCR_BCC;
+
+	if (flexcan->lprio)
+		reg |= __MCR_LPRIO_EN;
+	else
+		reg &= ~__MCR_LPRIO_EN;
+
+	if (flexcan->abort)
+		reg |= __MCR_AEN;
+	else
+		reg &= ~__MCR_AEN;
+
+	reg |= (flexcan->maxmb << __MCR_MAX_MB_OFFSET);
+	reg |= __MCR_DOZE | __MCR_MAX_IDAM_C;
+	__raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR);
+}
+
+static inline void flexcan_ctrl_setup(struct flexcan_device *flexcan)
+{
+	unsigned int reg;
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_CTRL);
+	reg &= ~(__CTRL_PRESDIV_MASK | __CTRL_RJW_MASK | __CTRL_PSEG1_MASK |
+		 __CTRL_PSEG2_MASK | __CTRL_PROPSEG_MASK);
+
+	if (flexcan->loopback)
+		reg |= __CTRL_LPB;
+	else
+		reg &= ~__CTRL_LPB;
+
+	if (flexcan->smp)
+		reg |= __CTRL_SMP;
+	else
+		reg &= ~__CTRL_SMP;
+
+	if (flexcan->boff_rec)
+		reg |= __CTRL_BOFF_REC;
+	else
+		reg &= ~__CTRL_BOFF_REC;
+
+	if (flexcan->tsyn)
+		reg |= __CTRL_TSYN;
+	else
+		reg &= ~__CTRL_TSYN;
+
+	if (flexcan->listen)
+		reg |= __CTRL_LOM;
+	else
+		reg &= ~__CTRL_LOM;
+
+	reg |= (flexcan->br_presdiv << __CTRL_PRESDIV_OFFSET) |
+	    (flexcan->br_rjw << __CTRL_RJW_OFFSET) |
+	    (flexcan->br_pseg1 << __CTRL_PSEG1_OFFSET) |
+	    (flexcan->br_pseg2 << __CTRL_PSEG2_OFFSET) |
+	    (flexcan->br_propseg << __CTRL_PROPSEG_OFFSET);
+
+	reg &= ~__CTRL_LBUF;
+
+	reg |= __CTRL_TWRN_MSK | __CTRL_RWRN_MSK | __CTRL_BOFF_MSK |
+	    __CTRL_ERR_MSK;
+
+	__raw_writel(reg, flexcan->io_base + CAN_HW_REG_CTRL);
+}
+
+static int flexcan_hw_restart(struct net_device *dev)
+{
+	unsigned int reg;
+	struct flexcan_device *flexcan = netdev_priv(dev);
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	if (reg & __MCR_SOFT_RST)
+		return 1;
+
+	flexcan_mcr_setup(flexcan);
+
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK2);
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK1);
+
+	__raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG2);
+	__raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG1);
+
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_ECR);
+
+	flexcan_mbm_init(flexcan);
+	netif_carrier_on(dev);
+	flexcan_hw_start(flexcan);
+
+	if (netif_queue_stopped(dev))
+		netif_start_queue(dev);
+
+	return 0;
+}
+
+static void flexcan_hw_watch(unsigned long data)
+{
+	unsigned int reg, ecr;
+	struct net_device *dev = (struct net_device *)data;
+	struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL;
+
+	BUG_ON(!flexcan);
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	if (reg & __MCR_MDIS) {
+		if (flexcan_hw_restart(dev))
+			mod_timer(&flexcan->timer, HZ / 20);
+		return;
+	}
+	ecr = __raw_readl(flexcan->io_base + CAN_HW_REG_ECR);
+	if (flexcan->boff_rec) {
+		if (((reg & __ESR_FLT_CONF_MASK) >> __ESR_FLT_CONF_OFF) > 1) {
+			reg |= __MCR_SOFT_RST;
+			__raw_writel(reg, flexcan->io_base + CAN_HW_REG_MCR);
+			mod_timer(&flexcan->timer, HZ / 20);
+			return;
+		}
+		netif_carrier_on(dev);
+	}
+}
+
+static void flexcan_hw_busoff(struct net_device *dev)
+{
+	struct flexcan_device *flexcan = netdev_priv(dev);
+	unsigned int reg;
+
+	netif_carrier_off(dev);
+
+	flexcan->timer.function = flexcan_hw_watch;
+	flexcan->timer.data = (unsigned long)dev;
+
+	if (flexcan->boff_rec) {
+		mod_timer(&flexcan->timer, HZ / 10);
+		return;
+	}
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_MCR);
+	__raw_writel(reg | __MCR_SOFT_RST, flexcan->io_base + CAN_HW_REG_MCR);
+	mod_timer(&flexcan->timer, HZ / 20);
+}
+
+static int flexcan_hw_open(struct flexcan_device *flexcan)
+{
+	if (flexcan_hw_reset(flexcan))
+		return -EFAULT;
+
+	flexcan_mcr_setup(flexcan);
+	flexcan_ctrl_setup(flexcan);
+
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK2);
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_IMASK1);
+
+	__raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG2);
+	__raw_writel(0xFFFFFFFF, flexcan->io_base + CAN_HW_REG_IFLAG1);
+
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_ECR);
+	return 0;
+}
+
+static void flexcan_err_handler(struct net_device *dev)
+{
+	struct flexcan_device *flexcan = netdev_priv(dev);
+	struct sk_buff *skb;
+	struct can_frame *frame;
+	unsigned int esr, ecr;
+
+	esr = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR);
+	__raw_writel(esr & __ESR_INTERRUPTS, flexcan->io_base + CAN_HW_REG_ESR);
+
+	if (esr & __ESR_WAK_INT)
+		return;
+
+	skb = dev_alloc_skb(sizeof(struct can_frame));
+	if (!skb) {
+		printk(KERN_ERR "%s: allocates skb fail in\n", __func__);
+		return;
+	}
+	frame = (struct can_frame *)skb_put(skb, sizeof(*frame));
+	memset(frame, 0, sizeof(*frame));
+	frame->can_id = CAN_ERR_FLAG | CAN_ERR_CRTL;
+	frame->can_dlc = CAN_ERR_DLC;
+
+	if (esr & __ESR_TWRN_INT)
+		frame->data[1] |= CAN_ERR_CRTL_TX_WARNING;
+
+	if (esr & __ESR_RWRN_INT)
+		frame->data[1] |= CAN_ERR_CRTL_RX_WARNING;
+
+	if (esr & __ESR_BOFF_INT)
+		frame->can_id |= CAN_ERR_BUSOFF;
+
+	if (esr & __ESR_ERR_INT) {
+		if (esr & __ESR_BIT1_ERR)
+			frame->data[2] |= CAN_ERR_PROT_BIT1;
+
+		if (esr & __ESR_BIT0_ERR)
+			frame->data[2] |= CAN_ERR_PROT_BIT0;
+
+		if (esr & __ESR_ACK_ERR)
+			frame->can_id |= CAN_ERR_ACK;
+
+		/*TODO:// if (esr & __ESR_CRC_ERR) */
+
+		if (esr & __ESR_FRM_ERR)
+			frame->data[2] |= CAN_ERR_PROT_FORM;
+
+		if (esr & __ESR_STF_ERR)
+			frame->data[2] |= CAN_ERR_PROT_STUFF;
+
+		ecr = __raw_readl(flexcan->io_base + CAN_HW_REG_ECR);
+		switch ((esr & __ESR_FLT_CONF_MASK) >> __ESR_FLT_CONF_OFF) {
+		case 0:
+			if (__ECR_TX_ERR_COUNTER(ecr) >= __ECR_ACTIVE_THRESHOLD)
+				frame->data[1] |= CAN_ERR_CRTL_TX_WARNING;
+			if (__ECR_RX_ERR_COUNTER(ecr) >= __ECR_ACTIVE_THRESHOLD)
+				frame->data[1] |= CAN_ERR_CRTL_RX_WARNING;
+			break;
+		case 1:
+			if (__ECR_TX_ERR_COUNTER(ecr) >=
+			    __ECR_PASSIVE_THRESHOLD)
+				frame->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
+
+			if (__ECR_RX_ERR_COUNTER(ecr) >=
+			    __ECR_PASSIVE_THRESHOLD)
+				frame->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
+			break;
+		default:
+			frame->can_id |= CAN_ERR_BUSOFF;
+		}
+	}
+
+	if (frame->can_id & CAN_ERR_BUSOFF)
+		flexcan_hw_busoff(dev);
+
+	skb->dev = dev;
+	skb->ip_summed = CHECKSUM_UNNECESSARY;
+	netif_receive_skb(skb);
+}
+
+static irqreturn_t flexcan_irq_handler(int irq, void *data)
+{
+	struct net_device *dev = (struct net_device *)data;
+	struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL;
+	unsigned int reg;
+
+	BUG_ON(!flexcan);
+
+	reg = __raw_readl(flexcan->io_base + CAN_HW_REG_ESR);
+	if (reg & __ESR_INTERRUPTS) {
+		flexcan_err_handler(dev);
+		return IRQ_HANDLED;
+	}
+
+	flexcan_mbm_isr(dev);
+	return IRQ_HANDLED;
+}
+
+static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct can_frame *frame = (struct can_frame *)skb->data;
+	struct flexcan_device *flexcan = netdev_priv(dev);
+	struct net_device_stats *stats = &dev->stats;
+
+	BUG_ON(!flexcan);
+
+	if (frame->can_dlc > 8)
+		return -EINVAL;
+
+	if (!flexcan_mbm_xmit(flexcan, frame)) {
+		dev_kfree_skb(skb);
+		stats->tx_bytes += frame->can_dlc;
+		stats->tx_packets++;
+		dev->trans_start = jiffies;
+		return NETDEV_TX_OK;
+	}
+	netif_stop_queue(dev);
+	return NETDEV_TX_BUSY;
+}
+
+static int flexcan_open(struct net_device *dev)
+{
+	struct flexcan_device *flexcan;
+	struct platform_device *pdev;
+	struct flexcan_platform_data *plat_data;
+
+	flexcan = netdev_priv(dev);
+	BUG_ON(!flexcan);
+
+	pdev = flexcan->dev;
+	plat_data = (pdev->dev).platform_data;
+	if (plat_data && plat_data->active)
+		plat_data->active(pdev->id);
+
+	if (flexcan->clk)
+		if (clk_enable(flexcan->clk))
+			goto clk_err;
+
+	if (flexcan->core_reg)
+		if (regulator_enable(flexcan->core_reg))
+			goto core_reg_err;
+
+	if (flexcan->io_reg)
+		if (regulator_enable(flexcan->io_reg))
+			goto io_reg_err;
+
+	if (plat_data && plat_data->xcvr_enable)
+		plat_data->xcvr_enable(pdev->id, 1);
+
+	if (request_irq(flexcan->irq, flexcan_irq_handler, IRQF_SAMPLE_RANDOM,
+			dev->name, dev))
+		goto irq_err;
+
+	if (flexcan_hw_open(flexcan))
+		goto open_err;
+
+	flexcan_mbm_init(flexcan);
+	netif_carrier_on(dev);
+	flexcan_hw_start(flexcan);
+	return 0;
+      open_err:
+	free_irq(flexcan->irq, dev);
+      irq_err:
+	if (plat_data && plat_data->xcvr_enable)
+		plat_data->xcvr_enable(pdev->id, 0);
+
+	if (flexcan->io_reg)
+		regulator_disable(flexcan->io_reg);
+      io_reg_err:
+	if (flexcan->core_reg)
+		regulator_disable(flexcan->core_reg);
+      core_reg_err:
+	if (flexcan->clk)
+		clk_disable(flexcan->clk);
+      clk_err:
+	if (plat_data && plat_data->inactive)
+		plat_data->inactive(pdev->id);
+	return -ENODEV;
+}
+
+static int flexcan_stop(struct net_device *dev)
+{
+	struct flexcan_device *flexcan;
+	struct platform_device *pdev;
+	struct flexcan_platform_data *plat_data;
+
+	flexcan = netdev_priv(dev);
+
+	BUG_ON(!flexcan);
+
+	pdev = flexcan->dev;
+	plat_data = (pdev->dev).platform_data;
+
+	flexcan_hw_stop(flexcan);
+
+	free_irq(flexcan->irq, dev);
+
+	if (plat_data && plat_data->xcvr_enable)
+		plat_data->xcvr_enable(pdev->id, 0);
+
+	if (flexcan->io_reg)
+		regulator_disable(flexcan->io_reg);
+	if (flexcan->core_reg)
+		regulator_disable(flexcan->core_reg);
+	if (flexcan->clk)
+		clk_disable(flexcan->clk);
+	if (plat_data && plat_data->inactive)
+		plat_data->inactive(pdev->id);
+	return 0;
+}
+
+static struct net_device_ops flexcan_netdev_ops = {
+	.ndo_open = flexcan_open,
+	.ndo_stop = flexcan_stop,
+	.ndo_start_xmit = flexcan_start_xmit,
+};
+
+static void flexcan_setup(struct net_device *dev)
+{
+	dev->type = ARPHRD_CAN;
+	dev->mtu = sizeof(struct can_frame);
+	dev->hard_header_len = 0;
+	dev->addr_len = 0;
+	dev->tx_queue_len = FLEXCAN_MAX_MB;
+	dev->flags = IFF_NOARP;
+	dev->features = NETIF_F_NO_CSUM;
+
+	dev->netdev_ops = &flexcan_netdev_ops;
+}
+
+static int flexcan_probe(struct platform_device *pdev)
+{
+	struct net_device *net;
+	net = flexcan_device_alloc(pdev, flexcan_setup);
+	if (!net)
+		return -ENOMEM;
+
+	if (register_netdev(net)) {
+		flexcan_device_free(pdev);
+		return -ENODEV;
+	}
+	return 0;
+}
+
+static int flexcan_remove(struct platform_device *pdev)
+{
+	flexcan_device_free(pdev);
+	return 0;
+}
+
+static int flexcan_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct net_device *net;
+	struct flexcan_device *flexcan;
+	struct flexcan_platform_data *plat_data;
+	net = (struct net_device *)dev_get_drvdata(&pdev->dev);
+	flexcan = netdev_priv(net);
+
+	BUG_ON(!flexcan);
+
+	if (!(net->flags & IFF_UP))
+		return 0;
+	if (flexcan->wakeup)
+		set_irq_wake(flexcan->irq, 1);
+	else {
+		plat_data = (pdev->dev).platform_data;
+
+		if (plat_data && plat_data->xcvr_enable)
+			plat_data->xcvr_enable(pdev->id, 0);
+
+		if (flexcan->io_reg)
+			regulator_disable(flexcan->io_reg);
+		if (flexcan->core_reg)
+			regulator_disable(flexcan->core_reg);
+		if (flexcan->clk)
+			clk_disable(flexcan->clk);
+		if (plat_data && plat_data->inactive)
+			plat_data->inactive(pdev->id);
+	}
+	return 0;
+}
+
+static int flexcan_resume(struct platform_device *pdev)
+{
+	struct net_device *net;
+	struct flexcan_device *flexcan;
+	struct flexcan_platform_data *plat_data;
+	net = (struct net_device *)dev_get_drvdata(&pdev->dev);
+	flexcan = netdev_priv(net);
+
+	BUG_ON(!flexcan);
+
+	if (!(net->flags & IFF_UP))
+		return 0;
+
+	if (flexcan->wakeup)
+		set_irq_wake(flexcan->irq, 0);
+	else {
+		plat_data = (pdev->dev).platform_data;
+		if (plat_data && plat_data->active)
+			plat_data->active(pdev->id);
+
+		if (flexcan->clk) {
+			if (clk_enable(flexcan->clk))
+				printk(KERN_ERR "%s:enable clock fail\n",
+				       __func__);
+		}
+
+		if (flexcan->core_reg) {
+			if (regulator_enable(flexcan->core_reg))
+				printk(KERN_ERR "%s:enable core voltage\n",
+				       __func__);
+		}
+		if (flexcan->io_reg) {
+			if (regulator_enable(flexcan->io_reg))
+				printk(KERN_ERR "%s:enable io voltage\n",
+				       __func__);
+		}
+
+		if (plat_data && plat_data->xcvr_enable)
+			plat_data->xcvr_enable(pdev->id, 1);
+	}
+	return 0;
+}
+
+static struct platform_driver flexcan_driver = {
+	.driver = {
+		   .name = FLEXCAN_DEVICE_NAME,
+		   },
+	.probe = flexcan_probe,
+	.remove = flexcan_remove,
+	.suspend = flexcan_suspend,
+	.resume = flexcan_resume,
+};
+
+static __init int flexcan_init(void)
+{
+	pr_info("Freescale FlexCAN Driver \n");
+	return platform_driver_register(&flexcan_driver);
+}
+
+static __exit void flexcan_exit(void)
+{
+	return platform_driver_unregister(&flexcan_driver);
+}
+
+module_init(flexcan_init);
+module_exit(flexcan_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/can/flexcan/flexcan.h b/drivers/net/can/flexcan/flexcan.h
new file mode 100644
index 000000000000..d19cc1ee0620
--- /dev/null
+++ b/drivers/net/can/flexcan/flexcan.h
@@ -0,0 +1,223 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file flexcan.h
+ *
+ * @brief FlexCan definitions.
+ *
+ * @ingroup can
+ */
+
+#ifndef __CAN_FLEXCAN_H__
+#define __CAN_FLEXCAN_H__
+
+#include <linux/list.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/clk.h>
+#include <linux/can.h>
+#include <linux/can/core.h>
+#include <linux/can/error.h>
+
+#define FLEXCAN_DEVICE_NAME	"FlexCAN"
+
+struct can_mb_cs {
+	unsigned int time_stamp:16;
+	unsigned int length:4;
+	unsigned int rtr:1;
+	unsigned int ide:1;
+	unsigned int srr:1;
+	unsigned int nouse1:1;
+	unsigned int code:4;
+	unsigned int nouse2:4;
+};
+
+#define CAN_MB_RX_INACTIVE	0x0
+#define CAN_MB_RX_EMPTY		0x4
+#define CAN_MB_RX_FULL		0x2
+#define CAN_MB_RX_OVERRUN	0x6
+#define CAN_MB_RX_BUSY		0x1
+
+#define CAN_MB_TX_INACTIVE	0x8
+#define CAN_MB_TX_ABORT		0x9
+#define CAN_MB_TX_ONCE		0xC
+#define CAN_MB_TX_REMOTE	0xA
+
+struct can_hw_mb {
+	union {
+		struct can_mb_cs cs;
+		unsigned int data;
+	} mb_cs;
+	unsigned int mb_id;
+	unsigned char mb_data[8];
+};
+
+#define CAN_HW_REG_MCR		0x00
+#define CAN_HW_REG_CTRL		0x04
+#define CAN_HW_REG_TIMER	0x08
+#define CAN_HW_REG_RXGMASK	0x10
+#define CAN_HW_REG_RX14MASK	0x14
+#define CAN_HW_REG_RX15MASK	0x18
+#define CAN_HW_REG_ECR		0x1C
+#define CAN_HW_REG_ESR		0x20
+#define CAN_HW_REG_IMASK2	0x24
+#define CAN_HW_REG_IMASK1	0x28
+#define CAN_HW_REG_IFLAG2	0x2C
+#define CAN_HW_REG_IFLAG1	0x30
+
+#define CAN_MB_BASE	0x0080
+#define CAN_RXMASK_BASE	0x0880
+#define CAN_FIFO_BASE	0xE0
+
+#define __MCR_MDIS		(1 << 31)
+#define __MCR_FRZ		(1 << 30)
+#define __MCR_FEN		(1 << 29)
+#define __MCR_HALT		(1 << 28)
+#define __MCR_NOTRDY		(1 << 27)
+#define __MCR_WAK_MSK		(1 << 26)
+#define __MCR_SOFT_RST		(1 << 25)
+#define __MCR_FRZ_ACK		(1 << 24)
+#define __MCR_SLF_WAK		(1 << 22)
+#define __MCR_WRN_EN		(1 << 21)
+#define __MCR_LPM_ACK		(1 << 20)
+#define __MCR_WAK_SRC		(1 << 19)
+#define __MCR_DOZE		(1 << 18)
+#define __MCR_SRX_DIS		(1 << 17)
+#define __MCR_BCC		(1 << 16)
+#define __MCR_LPRIO_EN		(1 << 13)
+#define __MCR_AEN		(1 << 12)
+#define __MCR_MAX_IDAM_OFFSET 	8
+#define __MCR_MAX_IDAM_MASK 	(0x3 << __MCR_MAX_IDAM_OFFSET)
+#define __MCR_MAX_IDAM_A	(0x0 << __MCR_MAX_IDAM_OFFSET)
+#define __MCR_MAX_IDAM_B	(0x1 << __MCR_MAX_IDAM_OFFSET)
+#define __MCR_MAX_IDAM_C	(0x2 << __MCR_MAX_IDAM_OFFSET)
+#define __MCR_MAX_IDAM_D	(0x3 << __MCR_MAX_IDAM_OFFSET)
+#define __MCR_MAX_MB_OFFSET 	0
+#define __MCR_MAX_MB_MASK 	(0x3F)
+
+#define __CTRL_PRESDIV_OFFSET	24
+#define __CTRL_PRESDIV_MASK	(0xFF << __CTRL_PRESDIV_OFFSET)
+#define __CTRL_RJW_OFFSET	22
+#define __CTRL_RJW_MASK		(0x3 << __CTRL_RJW_OFFSET)
+#define __CTRL_PSEG1_OFFSET	19
+#define __CTRL_PSEG1_MASK	(0x7 << __CTRL_PSEG1_OFFSET)
+#define __CTRL_PSEG2_OFFSET	16
+#define __CTRL_PSEG2_MASK	(0x7 << __CTRL_PSEG2_OFFSET)
+#define __CTRL_BOFF_MSK		(0x1 << 15)
+#define __CTRL_ERR_MSK		(0x1 << 14)
+#define __CTRL_CLK_SRC		(0x1 << 13)
+#define __CTRL_LPB		(0x1 << 12)
+#define __CTRL_TWRN_MSK		(0x1 << 11)
+#define __CTRL_RWRN_MSK		(0x1 << 10)
+#define __CTRL_SMP		(0x1 << 7)
+#define __CTRL_BOFF_REC		(0x1 << 6)
+#define __CTRL_TSYN		(0x1 << 5)
+#define __CTRL_LBUF		(0x1 << 4)
+#define __CTRL_LOM		(0x1 << 3)
+#define __CTRL_PROPSEG_OFFSET	0
+#define __CTRL_PROPSEG_MASK	(0x7)
+
+#define __ECR_TX_ERR_COUNTER(x) ((x) & 0xFF)
+#define __ECR_RX_ERR_COUNTER(x) (((x) >> 8) & 0xFF)
+#define __ECR_PASSIVE_THRESHOLD	128
+#define __ECR_ACTIVE_THRESHOLD	96
+
+#define __ESR_TWRN_INT		(0x1 << 17)
+#define __ESR_RWRN_INT		(0x1 << 16)
+#define __ESR_BIT1_ERR		(0x1 << 15)
+#define __ESR_BIT0_ERR		(0x1 << 14)
+#define __ESR_ACK_ERR		(0x1 << 13)
+#define __ESR_CRC_ERR		(0x1 << 12)
+#define __ESR_FRM_ERR		(0x1 << 11)
+#define __ESR_STF_ERR		(0x1 << 10)
+#define __ESR_TX_WRN		(0x1 << 9)
+#define __ESR_RX_WRN		(0x1 << 8)
+#define __ESR_IDLE		(0x1 << 7)
+#define __ESR_TXRX		(0x1 << 6)
+#define __ESR_FLT_CONF_OFF	4
+#define __ESR_FLT_CONF_MASK	(0x3 << __ESR_FLT_CONF_OFF)
+#define __ESR_BOFF_INT		(0x1 << 2)
+#define __ESR_ERR_INT		(0x1 << 1)
+#define __ESR_WAK_INT		(0x1)
+
+#define __ESR_INTERRUPTS	(__ESR_WAK_INT | __ESR_ERR_INT | \
+				__ESR_BOFF_INT | __ESR_TWRN_INT | \
+				__ESR_RWRN_INT)
+
+#define __FIFO_OV_INT		0x0080
+#define __FIFO_WARN_INT		0x0040
+#define __FIFO_RDY_INT		0x0020
+
+struct flexcan_device {
+	struct mutex mutex;
+	void *io_base;
+	struct can_hw_mb *hwmb;
+	unsigned int *rx_mask;
+	unsigned int xmit_mb;
+	unsigned int bitrate;
+	/* word 1 */
+	unsigned int br_presdiv:8;
+	unsigned int br_rjw:2;
+	unsigned int br_propseg:3;
+	unsigned int br_pseg1:3;
+	unsigned int br_pseg2:3;
+	unsigned int maxmb:6;
+	unsigned int xmit_maxmb:6;
+	unsigned int wd1_resv:1;
+
+	/* word 2 */
+	unsigned int fifo:1;
+	unsigned int wakeup:1;
+	unsigned int srx_dis:1;
+	unsigned int wak_src:1;
+	unsigned int bcc:1;
+	unsigned int lprio:1;
+	unsigned int abort:1;
+	unsigned int br_clksrc:1;
+	unsigned int loopback:1;
+	unsigned int smp:1;
+	unsigned int boff_rec:1;
+	unsigned int tsyn:1;
+	unsigned int listen:1;
+
+	unsigned int ext_msg:1;
+	unsigned int std_msg:1;
+
+	struct timer_list timer;
+	struct platform_device *dev;
+	struct regulator *core_reg;
+	struct regulator *io_reg;
+	struct clk *clk;
+	int irq;
+};
+
+#define FLEXCAN_MAX_FIFO_MB	8
+#define FLEXCAN_MAX_MB		64
+#define FLEXCAN_MAX_PRESDIV	256
+#define FLEXCAN_MAX_RJW		4
+#define FLEXCAN_MAX_PSEG1	8
+#define FLEXCAN_MAX_PSEG2	8
+#define FLEXCAN_MAX_PROPSEG	8
+#define FLEXCAN_MAX_BITRATE	1000000
+
+extern struct net_device *flexcan_device_alloc(struct platform_device *pdev,
+					       void (*setup) (struct net_device
+							      *dev));
+extern void flexcan_device_free(struct platform_device *pdev);
+
+extern void flexcan_mbm_init(struct flexcan_device *flexcan);
+extern void flexcan_mbm_isr(struct net_device *dev);
+extern int flexcan_mbm_xmit(struct flexcan_device *flexcan,
+			    struct can_frame *frame);
+#endif				/* __CAN_FLEXCAN_H__ */
diff --git a/drivers/net/can/flexcan/mbm.c b/drivers/net/can/flexcan/mbm.c
new file mode 100644
index 000000000000..b0341ba9128e
--- /dev/null
+++ b/drivers/net/can/flexcan/mbm.c
@@ -0,0 +1,347 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mbm.c
+ *
+ * @brief Driver for Freescale CAN Controller FlexCAN.
+ *
+ * @ingroup can
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/netdevice.h>
+#include <linux/if_arp.h>
+#include <linux/if_ether.h>
+#include <linux/platform_device.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include "flexcan.h"
+
+#define flexcan_swab32(x)	\
+	(((x) << 24) | ((x) >> 24) |\
+		(((x) & (__u32)0x0000ff00UL) << 8) |\
+		(((x) & (__u32)0x00ff0000UL) >> 8))
+
+static inline void flexcan_memcpy(void *dst, void *src, int len)
+{
+	int i;
+	unsigned int *d = (unsigned int *)dst, *s = (unsigned int *)src;
+	len = (len + 3) >> 2;
+	for (i = 0; i < len; i++, s++, d++)
+		*d = flexcan_swab32(*s);
+}
+
+static void flexcan_mb_bottom(struct net_device *dev, int index)
+{
+	struct flexcan_device *flexcan = netdev_priv(dev);
+	struct net_device_stats *stats = &dev->stats;
+	struct can_hw_mb *hwmb;
+	struct can_frame *frame;
+	struct sk_buff *skb;
+	unsigned int tmp;
+
+	hwmb = flexcan->hwmb + index;
+	if (flexcan->fifo || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) {
+		if (hwmb->mb_cs.cs.code == CAN_MB_TX_ABORT)
+			hwmb->mb_cs.cs.code = CAN_MB_TX_INACTIVE;
+
+		if (hwmb->mb_cs.cs.code & CAN_MB_TX_INACTIVE) {
+			if (netif_queue_stopped(dev))
+				netif_start_queue(dev);
+			return;
+		}
+	}
+	skb = dev_alloc_skb(sizeof(struct can_frame));
+	if (skb) {
+		frame = (struct can_frame *)skb_put(skb, sizeof(*frame));
+		memset(frame, 0, sizeof(*frame));
+		if (hwmb->mb_cs.cs.ide)
+			frame->can_id =
+			    (hwmb->mb_id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+		else
+			frame->can_id = (hwmb->mb_id >> 18) & CAN_SFF_MASK;
+
+		if (hwmb->mb_cs.cs.rtr)
+			frame->can_id |= CAN_RTR_FLAG;
+
+		frame->can_dlc = hwmb->mb_cs.cs.length;
+
+		if (frame->can_dlc && frame->can_dlc)
+			flexcan_memcpy(frame->data, hwmb->mb_data,
+				       frame->can_dlc);
+
+		if (flexcan->fifo
+		    || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) {
+			hwmb->mb_cs.cs.code = CAN_MB_TX_INACTIVE;
+			if (netif_queue_stopped(dev))
+				netif_start_queue(dev);
+		}
+
+		tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER);
+
+		dev->last_rx = jiffies;
+		stats->rx_packets++;
+		stats->rx_bytes += frame->can_dlc;
+
+		skb->dev = dev;
+		skb->protocol = __constant_htons(ETH_P_CAN);
+		skb->ip_summed = CHECKSUM_UNNECESSARY;
+		netif_rx(skb);
+	} else {
+		tmp = hwmb->mb_cs.data;
+		tmp = hwmb->mb_id;
+		tmp = hwmb->mb_data[0];
+		if (flexcan->fifo
+		    || (index >= (flexcan->maxmb - flexcan->xmit_maxmb))) {
+
+			hwmb->mb_cs.cs.code = CAN_MB_TX_INACTIVE;
+			if (netif_queue_stopped(dev))
+				netif_start_queue(dev);
+		}
+		tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER);
+		stats->rx_dropped++;
+	}
+}
+
+static void flexcan_fifo_isr(struct net_device *dev, unsigned int iflag1)
+{
+	struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL;
+	struct net_device_stats *stats = &dev->stats;
+	struct sk_buff *skb;
+	struct can_hw_mb *hwmb = flexcan->hwmb;
+	struct can_frame *frame;
+	unsigned int tmp;
+
+	if (iflag1 & __FIFO_RDY_INT) {
+		skb = dev_alloc_skb(sizeof(struct can_frame));
+		if (skb) {
+			frame =
+			    (struct can_frame *)skb_put(skb, sizeof(*frame));
+			memset(frame, 0, sizeof(*frame));
+			if (hwmb->mb_cs.cs.ide)
+				frame->can_id =
+				    (hwmb->mb_id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+			else
+				frame->can_id =
+				    (hwmb->mb_id >> 18) & CAN_SFF_MASK;
+
+			if (hwmb->mb_cs.cs.rtr)
+				frame->can_id |= CAN_RTR_FLAG;
+
+			frame->can_dlc = hwmb->mb_cs.cs.length;
+
+			if (frame->can_dlc && (frame->can_dlc <= 8))
+				flexcan_memcpy(frame->data, hwmb->mb_data,
+					       frame->can_dlc);
+			tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER);
+
+			dev->last_rx = jiffies;
+
+			stats->rx_packets++;
+			stats->rx_bytes += frame->can_dlc;
+
+			skb->dev = dev;
+			skb->protocol = __constant_htons(ETH_P_CAN);
+			skb->ip_summed = CHECKSUM_UNNECESSARY;
+			netif_rx(skb);
+		} else {
+			tmp = hwmb->mb_cs.data;
+			tmp = hwmb->mb_id;
+			tmp = hwmb->mb_data[0];
+			tmp = __raw_readl(flexcan->io_base + CAN_HW_REG_TIMER);
+		}
+	}
+
+	if (iflag1 & (__FIFO_OV_INT | __FIFO_WARN_INT)) {
+		skb = dev_alloc_skb(sizeof(struct can_frame));
+		if (skb) {
+			frame =
+			    (struct can_frame *)skb_put(skb, sizeof(*frame));
+			memset(frame, 0, sizeof(*frame));
+			frame->can_id = CAN_ERR_FLAG | CAN_ERR_CRTL;
+			frame->can_dlc = CAN_ERR_DLC;
+			if (iflag1 & __FIFO_WARN_INT)
+				frame->data[1] |=
+				    CAN_ERR_CRTL_TX_WARNING |
+				    CAN_ERR_CRTL_RX_WARNING;
+			if (iflag1 & __FIFO_OV_INT)
+				frame->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
+
+			skb->dev = dev;
+			skb->protocol = __constant_htons(ETH_P_CAN);
+			skb->ip_summed = CHECKSUM_UNNECESSARY;
+			netif_rx(skb);
+		}
+	}
+}
+
+/*!
+ * @brief The function call by CAN ISR to handle mb events.
+ *
+ * @param dev		the pointer of network device.
+ *
+ * @return none
+ */
+void flexcan_mbm_isr(struct net_device *dev)
+{
+	int i, iflag1, iflag2, maxmb;
+	struct flexcan_device *flexcan = dev ? netdev_priv(dev) : NULL;
+
+	if (flexcan->maxmb > 31) {
+		maxmb = flexcan->maxmb + 1 - 32;
+		iflag1 = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG1) &
+		    __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK1);
+		iflag2 = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG2) &
+		    __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK2);
+		iflag2 &= (1 << maxmb) - 1;
+		maxmb = 32;
+	} else {
+		maxmb = flexcan->maxmb + 1;
+		iflag1 = __raw_readl(flexcan->io_base + CAN_HW_REG_IFLAG1) &
+		    __raw_readl(flexcan->io_base + CAN_HW_REG_IMASK1);
+		iflag1 &= (1 << maxmb) - 1;
+		iflag2 = 0;
+	}
+
+	__raw_writel(iflag1, flexcan->io_base + CAN_HW_REG_IFLAG1);
+	__raw_writel(iflag2, flexcan->io_base + CAN_HW_REG_IFLAG2);
+
+	if (flexcan->fifo) {
+		flexcan_fifo_isr(dev, iflag1);
+		iflag1 &= 0xFFFFFF00;
+	}
+	for (i = 0; iflag1 && (i < maxmb); i++) {
+		if (iflag1 & (1 << i)) {
+			iflag1 &= ~(1 << i);
+			flexcan_mb_bottom(dev, i);
+		}
+	}
+
+	for (i = maxmb; iflag2 && (i <= flexcan->maxmb); i++) {
+		if (iflag2 & (1 << (i - 32))) {
+			iflag2 &= ~(1 << (i - 32));
+			flexcan_mb_bottom(dev, i);
+		}
+	}
+}
+
+/*!
+ * @brief function to xmit message buffer
+ *
+ * @param flexcan	the pointer of can hardware device.
+ * @param frame		the pointer of can message frame.
+ *
+ * @return	Returns 0 if xmit is success. otherwise returns non-zero.
+ */
+int flexcan_mbm_xmit(struct flexcan_device *flexcan, struct can_frame *frame)
+{
+	int i = flexcan->xmit_mb;
+	struct can_hw_mb *hwmb = flexcan->hwmb;
+
+	do {
+		if (hwmb[i].mb_cs.cs.code == CAN_MB_TX_INACTIVE)
+			break;
+		if ((++i) > flexcan->maxmb) {
+			if (flexcan->fifo)
+				i = FLEXCAN_MAX_FIFO_MB;
+			else
+				i = flexcan->xmit_maxmb + 1;
+		}
+		if (i == flexcan->xmit_mb)
+			return -1;
+	} while (1);
+
+	flexcan->xmit_mb = i + 1;
+	if (flexcan->xmit_mb > flexcan->maxmb) {
+		if (flexcan->fifo)
+			flexcan->xmit_mb = FLEXCAN_MAX_FIFO_MB;
+		else
+			flexcan->xmit_mb = flexcan->xmit_maxmb + 1;
+	}
+
+	if (frame->can_id & CAN_RTR_FLAG)
+		hwmb[i].mb_cs.cs.rtr = 1;
+	else
+		hwmb[i].mb_cs.cs.rtr = 0;
+
+	if (frame->can_id & CAN_EFF_FLAG) {
+		hwmb[i].mb_cs.cs.ide = 1;
+		hwmb[i].mb_cs.cs.srr = 1;
+		hwmb[i].mb_id = frame->can_id & CAN_EFF_MASK;
+	} else {
+		hwmb[i].mb_cs.cs.ide = 0;
+		hwmb[i].mb_id = (frame->can_id & CAN_SFF_MASK) << 18;
+	}
+
+	hwmb[i].mb_cs.cs.length = frame->can_dlc;
+	flexcan_memcpy(hwmb[i].mb_data, frame->data, frame->can_dlc);
+	hwmb[i].mb_cs.cs.code = CAN_MB_TX_ONCE;
+	return 0;
+}
+
+/*!
+ * @brief function to initial message buffer
+ *
+ * @param flexcan	the pointer of can hardware device.
+ *
+ * @return	none
+ */
+void flexcan_mbm_init(struct flexcan_device *flexcan)
+{
+	struct can_hw_mb *hwmb;
+	int rx_mb, i;
+
+	/* Set global mask to receive all messages */
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_RXGMASK);
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_RX14MASK);
+	__raw_writel(0, flexcan->io_base + CAN_HW_REG_RX15MASK);
+
+	memset(flexcan->hwmb, 0, sizeof(*hwmb) * FLEXCAN_MAX_MB);
+	/* Set individual mask to receive all messages */
+	memset(flexcan->rx_mask, 0, sizeof(unsigned int) * FLEXCAN_MAX_MB);
+
+	if (flexcan->fifo)
+		rx_mb = FLEXCAN_MAX_FIFO_MB;
+	else
+		rx_mb = flexcan->maxmb - flexcan->xmit_maxmb;
+
+	hwmb = flexcan->hwmb;
+	if (flexcan->fifo) {
+		unsigned long *id_table = flexcan->io_base + CAN_FIFO_BASE;
+		for (i = 0; i < rx_mb; i++)
+			id_table[i] = 0;
+	} else {
+		for (i = 0; i < rx_mb; i++) {
+			hwmb[i].mb_cs.cs.code = CAN_MB_RX_EMPTY;
+			/*
+			 * IDE bit can not control by mask registers
+			 * So set message buffer to receive extend
+			 * or standard message.
+			 */
+			if (flexcan->ext_msg && flexcan->std_msg)
+				hwmb[i].mb_cs.cs.ide = i & 1;
+			else {
+				if (flexcan->ext_msg)
+					hwmb[i].mb_cs.cs.ide = 1;
+			}
+		}
+	}
+
+	for (; i <= flexcan->maxmb; i++)
+		hwmb[i].mb_cs.cs.code = CAN_MB_TX_INACTIVE;
+
+	flexcan->xmit_mb = rx_mb;
+}
diff --git a/drivers/net/irda/Kconfig b/drivers/net/irda/Kconfig
index f76384221422..06151f87dacd 100644
--- a/drivers/net/irda/Kconfig
+++ b/drivers/net/irda/Kconfig
@@ -387,5 +387,9 @@ config MCS_FIR
 	  To compile it as a module, choose M here: the module will be called
 	  mcs7780.
 
+config MXC_FIR
+	tristate "Freescale MXC FIR driver"
+	depends on ARCH_MXC && IRDA
+
 endmenu
 
diff --git a/drivers/net/irda/Makefile b/drivers/net/irda/Makefile
index d82e1e3bd8c8..a54dcdeb3861 100644
--- a/drivers/net/irda/Makefile
+++ b/drivers/net/irda/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_VLSI_FIR)		+= vlsi_ir.o
 obj-$(CONFIG_VIA_FIR)		+= via-ircc.o
 obj-$(CONFIG_PXA_FICP)	        += pxaficp_ir.o
 obj-$(CONFIG_MCS_FIR)	        += mcs7780.o
+obj-$(CONFIG_MXC_FIR)	        += mxc_ir.o
 obj-$(CONFIG_AU1000_FIR)	+= au1k_ir.o
 # SIR drivers
 obj-$(CONFIG_IRTTY_SIR)		+= irtty-sir.o	sir-dev.o
diff --git a/drivers/net/irda/mxc_ir.c b/drivers/net/irda/mxc_ir.c
new file mode 100644
index 000000000000..fd5052f3a0ab
--- /dev/null
+++ b/drivers/net/irda/mxc_ir.c
@@ -0,0 +1,1781 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * Based on sa1100_ir.c - Copyright 2000-2001 Russell King
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file mxc_ir.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC FIRI.
+ *
+ * This driver is based on drivers/net/irda/sa1100_ir.c, by Russell King.
+ *
+ * @ingroup FIRI
+ */
+
+/*
+ * Include Files
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/netdevice.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+
+#include <net/irda/irda.h>
+#include <net/irda/wrapper.h>
+#include <net/irda/irda_device.h>
+
+#include <asm/irq.h>
+#include <asm/dma.h>
+#include <mach/hardware.h>
+#include <mach/mxc_uart.h>
+#include "mxc_ir.h"
+
+#define IS_SIR(mi)		( (mi)->speed <= 115200 )
+#define IS_MIR(mi)		( (mi)->speed < 4000000 && (mi)->speed >= 576000 )
+#define IS_FIR(mi)		( (mi)->speed >= 4000000 )
+
+#define SDMA_START_DELAY()	{  \
+				volatile int j,k;\
+				int i;\
+				for(i=0;i<10000;i++)\
+				k=j;\
+				}
+
+#define IRDA_FRAME_SIZE_LIMIT   2047
+#define UART_BUFF_SIZE 		14384
+
+#define UART4_UFCR_TXTL  	16
+#define UART4_UFCR_RXTL 	1
+
+#define FIRI_SDMA_TX
+#define FIRI_SDMA_RX
+
+/*!
+ * This structure is a way for the low level driver to define their own
+ * \b mxc_irda structure. This structure includes SK buffers, DMA buffers.
+ * and has other elements that are specifically required by this driver.
+ */
+struct mxc_irda {
+	/*!
+	 * This keeps track of device is running or not
+	 */
+	unsigned char open;
+
+	/*!
+	 * This holds current FIRI communication speed
+	 */
+	int speed;
+
+	/*!
+	 * This holds FIRI communication speed for next packet
+	 */
+	int newspeed;
+
+	/*!
+	 * SK buffer for transmitter
+	 */
+	struct sk_buff *txskb;
+
+	/*!
+	 * SK buffer for receiver
+	 */
+	struct sk_buff *rxskb;
+
+#ifdef FIRI_SDMA_RX
+	/*!
+	 * SK buffer for tasklet
+	 */
+	struct sk_buff *tskb;
+#endif
+
+	/*!
+	 * DMA address for transmitter
+	 */
+	dma_addr_t dma_rx_buff_phy;
+
+	/*!
+	 * DMA address for receiver
+	 */
+	dma_addr_t dma_tx_buff_phy;
+
+	/*!
+	 * DMA Transmit buffer length
+	 */
+	unsigned int dma_tx_buff_len;
+
+	/*!
+	 * DMA channel for transmitter
+	 */
+	int txdma_ch;
+
+	/*!
+	 * DMA channel for receiver
+	 */
+	int rxdma_ch;
+
+	/*!
+	 * IrDA network device statistics
+	 */
+	struct net_device_stats stats;
+
+	/*!
+	 * The device structure used to get FIRI information
+	 */
+	struct device *dev;
+
+	/*!
+	 * Resource structure for UART, which will maintain base addresses and IRQs.
+	 */
+	struct resource *uart_res;
+
+	/*!
+	 * Base address of UART, used in readl and writel.
+	 */
+	void *uart_base;
+
+	/*!
+	 * Resource structure for FIRI, which will maintain base addresses and IRQs.
+	 */
+	struct resource *firi_res;
+
+	/*!
+	 * Base address of FIRI, used in readl and writel.
+	 */
+	void *firi_base;
+
+	/*!
+	 * UART IRQ number.
+	 */
+	int uart_irq;
+
+	/*!
+	 * Second UART IRQ number in case the interrupt lines are not muxed.
+	 */
+	int uart_irq1;
+
+	/*!
+	 * UART clock needed for baud rate calculations
+	 */
+	struct clk *uart_clk;
+
+	/*!
+	 * UART clock needed for baud rate calculations
+	 */
+	unsigned long uart_clk_rate;
+
+	/*!
+	 * FIRI clock needed for baud rate calculations
+	 */
+	struct clk *firi_clk;
+
+	/*!
+	 * FIRI IRQ number.
+	 */
+	int firi_irq;
+
+	/*!
+	 * IrLAP layer instance
+	 */
+	struct irlap_cb *irlap;
+
+	/*!
+	 * Driver supported baudrate capabilities
+	 */
+	struct qos_info qos;
+
+	/*!
+	 * Temporary transmit buffer used by the driver
+	 */
+	iobuff_t tx_buff;
+
+	/*!
+	 * Temporary receive buffer used by the driver
+	 */
+	iobuff_t rx_buff;
+
+	/*!
+	 * Pointer to platform specific data structure.
+	 */
+	struct mxc_ir_platform_data *mxc_ir_plat;
+
+	/*!
+	 * This holds the power management status of this module.
+	 */
+	int suspend;
+
+};
+
+extern void gpio_firi_active(void *, unsigned int);
+extern void gpio_firi_inactive(void);
+extern void gpio_firi_init(void);
+
+void mxc_irda_firi_init(struct mxc_irda *si);
+#ifdef FIRI_SDMA_RX
+static void mxc_irda_fir_dma_rx_irq(void *id, int error_status,
+				    unsigned int count);
+#endif
+#ifdef FIRI_SDMA_TX
+static void mxc_irda_fir_dma_tx_irq(void *id, int error_status,
+				    unsigned int count);
+#endif
+
+/*!
+ * This function allocates and maps the receive buffer,
+ * unless it is already allocated.
+ *
+ * @param   si   FIRI device specific structure.
+ * @return  The function returns 0 on success and a non-zero value on
+ *          failure.
+ */
+static int mxc_irda_rx_alloc(struct mxc_irda *si)
+{
+#ifdef FIRI_SDMA_RX
+	mxc_dma_requestbuf_t dma_request;
+#endif
+	if (si->rxskb) {
+		return 0;
+	}
+
+	si->rxskb = alloc_skb(IRDA_FRAME_SIZE_LIMIT + 1, GFP_ATOMIC);
+
+	if (!si->rxskb) {
+		dev_err(si->dev, "mxc_ir: out of memory for RX SKB\n");
+		return -ENOMEM;
+	}
+
+	/*
+	 * Align any IP headers that may be contained
+	 * within the frame.
+	 */
+	skb_reserve(si->rxskb, 1);
+
+#ifdef FIRI_SDMA_RX
+	si->dma_rx_buff_phy =
+	    dma_map_single(si->dev, si->rxskb->data, IRDA_FRAME_SIZE_LIMIT,
+			   DMA_FROM_DEVICE);
+
+	dma_request.num_of_bytes = IRDA_FRAME_SIZE_LIMIT;
+	dma_request.dst_addr = si->dma_rx_buff_phy;
+	dma_request.src_addr = si->firi_res->start;
+
+	mxc_dma_config(si->rxdma_ch, &dma_request, 1, MXC_DMA_MODE_READ);
+#endif
+	return 0;
+}
+
+/*!
+ * This function is called to disable the FIRI dma
+ *
+ * @param   si  FIRI port specific structure.
+ */
+static void mxc_irda_disabledma(struct mxc_irda *si)
+{
+	/* Stop all DMA activity. */
+#ifdef FIRI_SDMA_TX
+	mxc_dma_disable(si->txdma_ch);
+#endif
+#ifdef FIRI_SDMA_RX
+	mxc_dma_disable(si->rxdma_ch);
+#endif
+}
+
+/*!
+ * This function is called to set the IrDA communications speed.
+ *
+ * @param   si     FIRI specific structure.
+ * @param   speed  new Speed to be configured for.
+ *
+ * @return  The function returns 0 on success and a non-zero value on
+ *          failure.
+ */
+static int mxc_irda_set_speed(struct mxc_irda *si, int speed)
+{
+	unsigned long flags;
+	int ret = 0;
+	unsigned int num, denom, baud;
+	unsigned int cr;
+
+	dev_dbg(si->dev, "speed:%d\n", speed);
+	switch (speed) {
+	case 9600:
+	case 19200:
+	case 38400:
+	case 57600:
+	case 115200:
+		dev_dbg(si->dev, "starting SIR\n");
+		baud = speed;
+		if (IS_FIR(si)) {
+#ifdef FIRI_SDMA_RX
+			mxc_dma_disable(si->rxdma_ch);
+#endif
+			cr = readl(si->firi_base + FIRITCR);
+			cr &= ~FIRITCR_TE;
+			writel(cr, si->firi_base + FIRITCR);
+
+			cr = readl(si->firi_base + FIRIRCR);
+			cr &= ~FIRIRCR_RE;
+			writel(cr, si->firi_base + FIRIRCR);
+
+		}
+		local_irq_save(flags);
+
+		/* Disable Tx and Rx */
+		cr = readl(si->uart_base + MXC_UARTUCR2);
+		cr &= ~(MXC_UARTUCR2_RXEN | MXC_UARTUCR2_TXEN);
+		writel(cr, si->uart_base + MXC_UARTUCR2);
+
+		gpio_firi_inactive();
+
+		num = baud / 100 - 1;
+		denom = si->uart_clk_rate / 1600 - 1;
+		if ((denom < 65536) && (si->uart_clk_rate > 1600)) {
+			writel(num, si->uart_base + MXC_UARTUBIR);
+			writel(denom, si->uart_base + MXC_UARTUBMR);
+		}
+
+		si->speed = speed;
+
+		writel(0xFFFF, si->uart_base + MXC_UARTUSR1);
+		writel(0xFFFF, si->uart_base + MXC_UARTUSR2);
+
+		/* Enable Receive Overrun and Data Ready interrupts. */
+		cr = readl(si->uart_base + MXC_UARTUCR4);
+		cr |= (MXC_UARTUCR4_OREN | MXC_UARTUCR4_DREN);
+		writel(cr, si->uart_base + MXC_UARTUCR4);
+
+		cr = readl(si->uart_base + MXC_UARTUCR2);
+		cr |= (MXC_UARTUCR2_RXEN | MXC_UARTUCR2_TXEN);
+		writel(cr, si->uart_base + MXC_UARTUCR2);
+
+		local_irq_restore(flags);
+		break;
+	case 4000000:
+		local_irq_save(flags);
+
+		/* Disable Receive Overrun and Data Ready interrupts. */
+		cr = readl(si->uart_base + MXC_UARTUCR4);
+		cr &= ~(MXC_UARTUCR4_OREN | MXC_UARTUCR4_DREN);
+		writel(cr, si->uart_base + MXC_UARTUCR4);
+
+		/* Disable Tx and Rx */
+		cr = readl(si->uart_base + MXC_UARTUCR2);
+		cr &= ~(MXC_UARTUCR2_RXEN | MXC_UARTUCR2_TXEN);
+		writel(cr, si->uart_base + MXC_UARTUCR2);
+
+		/*
+		 * FIR configuration
+		 */
+		mxc_irda_disabledma(si);
+
+		cr = readl(si->firi_base + FIRITCR);
+		cr &= ~FIRITCR_TE;
+		writel(cr, si->firi_base + FIRITCR);
+
+		gpio_firi_active(si->firi_base + FIRITCR, FIRITCR_TPP);
+
+		si->speed = speed;
+
+		cr = readl(si->firi_base + FIRIRCR);
+		cr |= FIRIRCR_RE;
+		writel(cr, si->firi_base + FIRIRCR);
+
+		dev_dbg(si->dev, "Going for fast IRDA ...\n");
+		ret = mxc_irda_rx_alloc(si);
+
+		/* clear RX status register */
+		writel(0xFFFF, si->firi_base + FIRIRSR);
+#ifdef FIRI_SDMA_RX
+		if (si->rxskb) {
+			mxc_dma_enable(si->rxdma_ch);
+		}
+#endif
+		local_irq_restore(flags);
+
+		break;
+	default:
+		dev_err(si->dev, "speed not supported by FIRI\n");
+		break;
+	}
+
+	return ret;
+}
+
+/*!
+ * This function is called to set the IrDA communications speed.
+ *
+ * @param   si     FIRI specific structure.
+ *
+ * @return  The function returns 0 on success and a non-zero value on
+ *          failure.
+ */
+static inline int mxc_irda_fir_error(struct mxc_irda *si)
+{
+	struct sk_buff *skb = si->rxskb;
+	unsigned int dd_error, crc_error, overrun_error;
+	unsigned int sr;
+
+	if (!skb) {
+		dev_err(si->dev, "no skb!\n");
+		return -1;
+	}
+
+	sr = readl(si->firi_base + FIRIRSR);
+	dd_error = sr & FIRIRSR_DDE;
+	crc_error = sr & FIRIRSR_CRCE;
+	overrun_error = sr & FIRIRSR_RFO;
+
+	if (!(dd_error | crc_error | overrun_error)) {
+		return 0;
+	}
+	dev_err(si->dev, "dde,crce,rfo=%d,%d,%d.\n", dd_error, crc_error,
+		overrun_error);
+	si->stats.rx_errors++;
+	if (crc_error) {
+		si->stats.rx_crc_errors++;
+	}
+	if (dd_error) {
+		si->stats.rx_frame_errors++;
+	}
+	if (overrun_error) {
+		si->stats.rx_frame_errors++;
+	}
+	writel(sr, si->firi_base + FIRIRSR);
+
+	return -1;
+}
+
+#ifndef FIRI_SDMA_RX
+/*!
+ * FIR interrupt service routine to handle receive.
+ *
+ * @param   dev     pointer to the net_device structure
+ */
+void mxc_irda_fir_irq_rx(struct net_device *dev)
+{
+	struct mxc_irda *si = dev->priv;
+	struct sk_buff *skb = si->rxskb;
+	unsigned int sr, len;
+	int i;
+	unsigned char *p = skb->data;
+
+	/*
+	 * Deal with any receive errors.
+	 */
+	if (mxc_irda_fir_error(si) != 0) {
+		return;
+	}
+
+	sr = readl(si->firi_base + FIRIRSR);
+
+	if (!(sr & FIRIRSR_RPE)) {
+		return;
+	}
+
+	/*
+	 * Coming here indicates that fir rx packet has been successfully recieved.
+	 * And No error happened so far.
+	 */
+	writel(sr | FIRIRSR_RPE, si->firi_base + FIRIRSR);
+
+	len = (sr & FIRIRSR_RFP) >> 8;
+
+	/* 4 bytes of CRC */
+	len -= 4;
+
+	skb_put(skb, len);
+
+	for (i = 0; i < len; i++) {
+		*p++ = readb(si->firi_base + FIRIRXFIFO);
+	}
+
+	/* Discard the four CRC bytes */
+	for (i = 0; i < 4; i++) {
+		readb(si->firi_base + FIRIRXFIFO);
+	}
+
+	/*
+	 * Deal with the case of packet complete.
+	 */
+	skb->dev = dev;
+	skb->mac.raw = skb->data;
+	skb->protocol = htons(ETH_P_IRDA);
+	si->stats.rx_packets++;
+	si->stats.rx_bytes += len;
+	netif_rx(skb);
+
+	si->rxskb = NULL;
+	mxc_irda_rx_alloc(si);
+
+	writel(0xFFFF, si->firi_base + FIRIRSR);
+
+}
+#endif
+
+/*!
+ * FIR interrupt service routine to handle transmit.
+ *
+ * @param   dev     pointer to the net_device structure
+ */
+void mxc_irda_fir_irq_tx(struct net_device *dev)
+{
+	struct mxc_irda *si = netdev_priv(dev);
+	struct sk_buff *skb = si->txskb;
+	unsigned int cr, sr;
+
+	sr = readl(si->firi_base + FIRITSR);
+	writel(sr, si->firi_base + FIRITSR);
+
+	if (sr & FIRITSR_TC) {
+
+#ifdef FIRI_SDMA_TX
+		mxc_dma_disable(si->txdma_ch);
+#endif
+		cr = readl(si->firi_base + FIRITCR);
+		cr &= ~(FIRITCR_TCIE | FIRITCR_TE);
+		writel(cr, si->firi_base + FIRITCR);
+
+		if (si->newspeed) {
+			mxc_irda_set_speed(si, si->newspeed);
+			si->newspeed = 0;
+		}
+		si->txskb = NULL;
+
+		cr = readl(si->firi_base + FIRIRCR);
+		cr |= FIRIRCR_RE;
+		writel(cr, si->firi_base + FIRIRCR);
+
+		writel(0xFFFF, si->firi_base + FIRIRSR);
+		/*
+		 * Account and free the packet.
+		 */
+		if (skb) {
+#ifdef FIRI_SDMA_TX
+			dma_unmap_single(si->dev, si->dma_tx_buff_phy, skb->len,
+					 DMA_TO_DEVICE);
+#endif
+			si->stats.tx_packets++;
+			si->stats.tx_bytes += skb->len;
+			dev_kfree_skb_irq(skb);
+		}
+		/*
+		 * Make sure that the TX queue is available for sending
+		 * (for retries).  TX has priority over RX at all times.
+		 */
+		netif_wake_queue(dev);
+	}
+}
+
+/*!
+ * This is FIRI interrupt handler.
+ *
+ * @param   dev     pointer to the net_device structure
+ */
+void mxc_irda_fir_irq(struct net_device *dev)
+{
+	struct mxc_irda *si = netdev_priv(dev);
+	unsigned int sr1, sr2;
+
+	sr1 = readl(si->firi_base + FIRIRSR);
+	sr2 = readl(si->firi_base + FIRITSR);
+
+	if (sr2 & FIRITSR_TC)
+		mxc_irda_fir_irq_tx(dev);
+#ifndef FIRI_SDMA_RX
+	if (sr1 & (FIRIRSR_RPE | FIRIRSR_RFO))
+		mxc_irda_fir_irq_rx(dev);
+#endif
+
+}
+
+/*!
+ * This is the SIR transmit routine.
+ *
+ * @param   si     FIRI specific structure.
+ *
+ * @param   dev     pointer to the net_device structure
+ *
+ * @return  The function returns 0 on success and a non-zero value on
+ *          failure.
+ */
+static int mxc_irda_sir_txirq(struct mxc_irda *si, struct net_device *dev)
+{
+	unsigned int sr1, sr2, cr;
+	unsigned int status;
+
+	sr1 = readl(si->uart_base + MXC_UARTUSR1);
+	sr2 = readl(si->uart_base + MXC_UARTUSR2);
+	cr = readl(si->uart_base + MXC_UARTUCR2);
+
+	/*
+	 * Echo cancellation for IRDA Transmit chars
+	 * Disable the receiver and enable Transmit complete.
+	 */
+	cr &= ~MXC_UARTUCR2_RXEN;
+	writel(cr, si->uart_base + MXC_UARTUCR2);
+	cr = readl(si->uart_base + MXC_UARTUCR4);
+	cr |= MXC_UARTUCR4_TCEN;
+	writel(cr, si->uart_base + MXC_UARTUCR4);
+
+	while ((sr1 & MXC_UARTUSR1_TRDY) && si->tx_buff.len) {
+
+		writel(*si->tx_buff.data++, si->uart_base + MXC_UARTUTXD);
+		si->tx_buff.len -= 1;
+		sr1 = readl(si->uart_base + MXC_UARTUSR1);
+	}
+
+	if (si->tx_buff.len == 0) {
+		si->stats.tx_packets++;
+		si->stats.tx_bytes += si->tx_buff.data - si->tx_buff.head;
+
+		/*Yoohoo...we are done...Lets stop Tx */
+		cr = readl(si->uart_base + MXC_UARTUCR1);
+		cr &= ~MXC_UARTUCR1_TRDYEN;
+		writel(cr, si->uart_base + MXC_UARTUCR1);
+
+		do {
+			status = readl(si->uart_base + MXC_UARTUSR2);
+		} while (!(status & MXC_UARTUSR2_TXDC));
+
+		if (si->newspeed) {
+			mxc_irda_set_speed(si, si->newspeed);
+			si->newspeed = 0;
+		}
+		/* I'm hungry! */
+		netif_wake_queue(dev);
+
+		/* Is the transmit complete to reenable the receiver? */
+		if (status & MXC_UARTUSR2_TXDC) {
+
+			cr = readl(si->uart_base + MXC_UARTUCR2);
+			cr |= MXC_UARTUCR2_RXEN;
+			writel(cr, si->uart_base + MXC_UARTUCR2);
+			/* Disable the Transmit complete interrupt bit */
+			cr = readl(si->uart_base + MXC_UARTUCR4);
+			cr &= ~MXC_UARTUCR4_TCEN;
+			writel(cr, si->uart_base + MXC_UARTUCR4);
+		}
+	}
+
+	return 0;
+}
+
+/*!
+ * This is the SIR receive routine.
+ *
+ * @param   si     FIRI specific structure.
+ *
+ * @param   dev     pointer to the net_device structure
+ *
+ * @return  The function returns 0 on success and a non-zero value on
+ *          failure.
+ */
+static int mxc_irda_sir_rxirq(struct mxc_irda *si, struct net_device *dev)
+{
+	unsigned int data, status;
+	volatile unsigned int sr2;
+
+	sr2 = readl(si->uart_base + MXC_UARTUSR2);
+	while ((sr2 & MXC_UARTUSR2_RDR) == 1) {
+		data = readl(si->uart_base + MXC_UARTURXD);
+		status = data & 0xf400;
+		if (status & MXC_UARTURXD_ERR) {
+			dev_err(si->dev, "Receive an incorrect data =0x%x.\n",
+				data);
+			si->stats.rx_errors++;
+			if (status & MXC_UARTURXD_OVRRUN) {
+				si->stats.rx_fifo_errors++;
+				dev_err(si->dev, "Rx overrun.\n");
+			}
+			if (status & MXC_UARTURXD_FRMERR) {
+				si->stats.rx_frame_errors++;
+				dev_err(si->dev, "Rx frame error.\n");
+			}
+			if (status & MXC_UARTURXD_PRERR) {
+				dev_err(si->dev, "Rx parity error.\n");
+			}
+			/* Other: it is the Break char.
+			 * Do nothing for it. throw out the data.
+			 */
+			async_unwrap_char(dev, &si->stats, &si->rx_buff,
+					  (data & 0xFF));
+		} else {
+			/* It is correct data. */
+			data &= 0xFF;
+			async_unwrap_char(dev, &si->stats, &si->rx_buff, data);
+
+			dev->last_rx = jiffies;
+		}
+		sr2 = readl(si->uart_base + MXC_UARTUSR2);
+
+		writel(0xFFFF, si->uart_base + MXC_UARTUSR1);
+		writel(0xFFFF, si->uart_base + MXC_UARTUSR2);
+	}			/*while */
+	return 0;
+
+}
+
+static irqreturn_t mxc_irda_irq(int irq, void *dev_id)
+{
+	struct net_device *dev = dev_id;
+	struct mxc_irda *si = netdev_priv(dev);
+
+	if (IS_FIR(si)) {
+		mxc_irda_fir_irq(dev);
+		return IRQ_HANDLED;
+	}
+
+	if (readl(si->uart_base + MXC_UARTUCR2) & MXC_UARTUCR2_RXEN) {
+		mxc_irda_sir_rxirq(si, dev);
+	}
+	if ((readl(si->uart_base + MXC_UARTUCR1) & MXC_UARTUCR1_TRDYEN) &&
+	    (readl(si->uart_base + MXC_UARTUSR1) & MXC_UARTUSR1_TRDY)) {
+		mxc_irda_sir_txirq(si, dev);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxc_irda_tx_irq(int irq, void *dev_id)
+{
+
+	struct net_device *dev = dev_id;
+	struct mxc_irda *si = netdev_priv(dev);
+
+	mxc_irda_sir_txirq(si, dev);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t mxc_irda_rx_irq(int irq, void *dev_id)
+{
+
+	struct net_device *dev = dev_id;
+	struct mxc_irda *si = netdev_priv(dev);
+
+	/* Clear the aging timer bit */
+	writel(MXC_UARTUSR1_AGTIM, si->uart_base + MXC_UARTUSR1);
+
+	mxc_irda_sir_rxirq(si, dev);
+
+	return IRQ_HANDLED;
+}
+
+#ifdef FIRI_SDMA_RX
+struct tasklet_struct dma_rx_tasklet;
+
+static void mxc_irda_rx_task(unsigned long tparam)
+{
+	struct mxc_irda *si = (struct mxc_irda *)tparam;
+	struct sk_buff *lskb = si->tskb;
+
+	si->tskb = NULL;
+	if (lskb) {
+		lskb->mac_header = lskb->data;
+		lskb->protocol = htons(ETH_P_IRDA);
+		netif_rx(lskb);
+	}
+}
+
+/*!
+ * Receiver DMA callback routine.
+ *
+ * @param   id   pointer to network device structure
+ * @param   error_status   used to pass error status to this callback function
+ * @param   count   number of bytes received
+ */
+static void mxc_irda_fir_dma_rx_irq(void *id, int error_status,
+				    unsigned int count)
+{
+	struct net_device *dev = id;
+	struct mxc_irda *si = netdev_priv(dev);
+	struct sk_buff *skb = si->rxskb;
+	unsigned int cr;
+	unsigned int len;
+
+	cr = readl(si->firi_base + FIRIRCR);
+	cr &= ~FIRIRCR_RE;
+	writel(cr, si->firi_base + FIRIRCR);
+	cr = readl(si->firi_base + FIRIRCR);
+	cr |= FIRIRCR_RE;
+	writel(cr, si->firi_base + FIRIRCR);
+	len = count - 4;	/* remove 4 bytes for CRC */
+	skb_put(skb, len);
+	skb->dev = dev;
+	si->tskb = skb;
+	tasklet_schedule(&dma_rx_tasklet);
+
+	if (si->dma_rx_buff_phy != 0)
+		dma_unmap_single(si->dev, si->dma_rx_buff_phy,
+				 IRDA_FRAME_SIZE_LIMIT, DMA_FROM_DEVICE);
+
+	si->rxskb = NULL;
+	mxc_irda_rx_alloc(si);
+
+	SDMA_START_DELAY();
+	writel(0xFFFF, si->firi_base + FIRIRSR);
+
+	if (si->rxskb) {
+		mxc_dma_enable(si->rxdma_ch);
+	}
+}
+#endif
+
+#ifdef FIRI_SDMA_TX
+/*!
+ * This function is called by SDMA Interrupt Service Routine to indicate
+ * requested DMA transfer is completed.
+ *
+ * @param   id   pointer to network device structure
+ * @param   error_status   used to pass error status to this callback function
+ * @param   count   number of bytes sent
+ */
+static void mxc_irda_fir_dma_tx_irq(void *id, int error_status,
+				    unsigned int count)
+{
+	struct net_device *dev = id;
+	struct mxc_irda *si = netdev_priv(dev);
+
+	mxc_dma_disable(si->txdma_ch);
+}
+#endif
+
+/*!
+ * This function is called by Linux IrDA network subsystem to
+ * transmit the Infrared data packet. The TX DMA channel is configured
+ * to transfer SK buffer data to FIRI TX FIFO along with DMA transfer
+ * completion routine.
+ *
+ * @param   skb   The packet that is queued to be sent
+ * @param   dev   net_device structure.
+ *
+ * @return  The function returns 0 on success and a negative value on
+ *          failure.
+ */
+static int mxc_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev)
+{
+	struct mxc_irda *si = netdev_priv(dev);
+	int speed = irda_get_next_speed(skb);
+	unsigned int cr;
+
+	/*
+	 * Does this packet contain a request to change the interface
+	 * speed?  If so, remember it until we complete the transmission
+	 * of this frame.
+	 */
+	if (speed != si->speed && speed != -1) {
+		si->newspeed = speed;
+	}
+
+	/* If this is an empty frame, we can bypass a lot. */
+	if (skb->len == 0) {
+		if (si->newspeed) {
+			si->newspeed = 0;
+			mxc_irda_set_speed(si, speed);
+		}
+		dev_kfree_skb(skb);
+		return 0;
+	}
+
+	/* We must not be transmitting... */
+	netif_stop_queue(dev);
+	if (IS_SIR(si)) {
+
+		si->tx_buff.data = si->tx_buff.head;
+		si->tx_buff.len = async_wrap_skb(skb, si->tx_buff.data,
+						 si->tx_buff.truesize);
+		cr = readl(si->uart_base + MXC_UARTUCR1);
+		cr |= MXC_UARTUCR1_TRDYEN;
+		writel(cr, si->uart_base + MXC_UARTUCR1);
+		dev_kfree_skb(skb);
+	} else {
+		unsigned int mtt = irda_get_mtt(skb);
+		unsigned char *p = skb->data;
+		unsigned int skb_len = skb->len;
+#ifdef FIRI_SDMA_TX
+		mxc_dma_requestbuf_t dma_request;
+#else
+		unsigned int i, sr;
+#endif
+
+		skb_len = skb_len + ((4 - (skb_len % 4)) % 4);
+
+		if (si->txskb) {
+			BUG();
+		}
+		si->txskb = skb;
+
+		/*
+		 * If we have a mean turn-around time, impose the specified
+		 * specified delay.  We could shorten this by timing from
+		 * the point we received the packet.
+		 */
+		if (mtt) {
+			udelay(mtt);
+		}
+
+		cr = readl(si->firi_base + FIRIRCR);
+		cr &= ~FIRIRCR_RE;
+		writel(cr, si->firi_base + FIRIRCR);
+
+		writel(skb->len - 1, si->firi_base + FIRITCTR);
+
+#ifdef FIRI_SDMA_TX
+		/*
+		 * Configure DMA Tx Channel for source and destination addresses,
+		 * Number of bytes in SK buffer to transfer and Transfer complete
+		 * callback function.
+		 */
+		si->dma_tx_buff_len = skb_len;
+		si->dma_tx_buff_phy =
+		    dma_map_single(si->dev, p, skb_len, DMA_TO_DEVICE);
+
+		dma_request.num_of_bytes = skb_len;
+		dma_request.dst_addr = si->firi_res->start + FIRITXFIFO;
+		dma_request.src_addr = si->dma_tx_buff_phy;
+
+		mxc_dma_config(si->txdma_ch, &dma_request, 1,
+			       MXC_DMA_MODE_WRITE);
+
+		mxc_dma_enable(si->txdma_ch);
+#endif
+		cr = readl(si->firi_base + FIRITCR);
+		cr |= FIRITCR_TCIE;
+		writel(cr, si->firi_base + FIRITCR);
+
+		cr |= FIRITCR_TE;
+		writel(cr, si->firi_base + FIRITCR);
+
+#ifndef FIRI_SDMA_TX
+		for (i = 0; i < skb->len;) {
+			sr = readl(si->firi_base + FIRITSR);
+			/* TFP = number of bytes in the TX FIFO for the
+			 * Transmitter
+			 * */
+			if ((sr >> 8) < 128) {
+				writeb(*p, si->firi_base + FIRITXFIFO);
+				p++;
+				i++;
+			}
+		}
+#endif
+	}
+
+	dev->trans_start = jiffies;
+	return 0;
+}
+
+/*!
+ * This function handles network interface ioctls passed to this driver..
+ *
+ * @param   dev   net device structure
+ * @param   ifreq user request data
+ * @param   cmd   command issued
+ *
+ * @return  The function returns 0 on success and a non-zero value on
+ *           failure.
+ */
+static int mxc_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd)
+{
+	struct if_irda_req *rq = (struct if_irda_req *)ifreq;
+	struct mxc_irda *si = netdev_priv(dev);
+	int ret = -EOPNOTSUPP;
+
+	switch (cmd) {
+		/* This function will be used by IrLAP to change the speed */
+	case SIOCSBANDWIDTH:
+		dev_dbg(si->dev, "%s:with cmd SIOCSBANDWIDTH\n", __FUNCTION__);
+		if (capable(CAP_NET_ADMIN)) {
+			/*
+			 * We are unable to set the speed if the
+			 * device is not running.
+			 */
+			if (si->open) {
+				ret = mxc_irda_set_speed(si, rq->ifr_baudrate);
+			} else {
+				dev_err(si->dev, "mxc_ir_ioctl: SIOCSBANDWIDTH:\
+                                         !netif_running\n");
+				ret = 0;
+			}
+		}
+		break;
+	case SIOCSMEDIABUSY:
+		dev_dbg(si->dev, "%s:with cmd SIOCSMEDIABUSY\n", __FUNCTION__);
+		ret = -EPERM;
+		if (capable(CAP_NET_ADMIN)) {
+			irda_device_set_media_busy(dev, TRUE);
+			ret = 0;
+		}
+		break;
+	case SIOCGRECEIVING:
+		rq->ifr_receiving =
+		    IS_SIR(si) ? si->rx_buff.state != OUTSIDE_FRAME : 0;
+		ret = 0;
+		break;
+	default:
+		break;
+	}
+	return ret;
+}
+
+/*!
+ * Kernel interface routine to get current statistics of the device
+ * which includes the number bytes/packets transmitted/received,
+ * receive errors, CRC errors, framing errors etc.
+ *
+ * @param  dev  the net_device structure
+ *
+ * @return This function returns IrDA network statistics
+ */
+static struct net_device_stats *mxc_irda_stats(struct net_device *dev)
+{
+	struct mxc_irda *si = netdev_priv(dev);
+	return &si->stats;
+}
+
+/*!
+ * FIRI init function
+ *
+ * @param si  FIRI device specific structure.
+ */
+void mxc_irda_firi_init(struct mxc_irda *si)
+{
+	unsigned int firi_baud, osf = 6;
+	unsigned int tcr, rcr, cr;
+
+	si->firi_clk = clk_get(si->dev, "firi_clk");
+	firi_baud = clk_round_rate(si->firi_clk, 48004500);
+	if ((firi_baud < 47995500) ||
+	    (clk_set_rate(si->firi_clk, firi_baud) < 0)) {
+		dev_err(si->dev, "Unable to set FIR clock to 48MHz.\n");
+		return;
+	}
+	clk_enable(si->firi_clk);
+
+	writel(0xFFFF, si->firi_base + FIRITSR);
+	writel(0xFFFF, si->firi_base + FIRIRSR);
+	writel(0x00, si->firi_base + FIRITCR);
+	writel(0x00, si->firi_base + FIRIRCR);
+
+	/* set _BL & _OSF */
+	cr = (osf - 1) | (16 << 5);
+	writel(cr, si->firi_base + FIRICR);
+
+#ifdef FIRI_SDMA_TX
+	tcr =
+	    FIRITCR_TDT_FIR | FIRITCR_TM_FIR | FIRITCR_TCIE |
+	    FIRITCR_PCF | FIRITCR_PC;
+#else
+	tcr = FIRITCR_TM_FIR | FIRITCR_TCIE | FIRITCR_PCF | FIRITCR_PC;
+#endif
+
+#ifdef FIRI_SDMA_RX
+	rcr =
+	    FIRIRCR_RPEDE | FIRIRCR_RM_FIR | FIRIRCR_RDT_FIR |
+	    FIRIRCR_RPA | FIRIRCR_RPP;
+#else
+	rcr =
+	    FIRIRCR_RPEDE | FIRIRCR_RM_FIR | FIRIRCR_RDT_FIR | FIRIRCR_RPEIE |
+	    FIRIRCR_RPA | FIRIRCR_PAIE | FIRIRCR_RFOIE | FIRIRCR_RPP;
+#endif
+
+	writel(tcr, si->firi_base + FIRITCR);
+	writel(rcr, si->firi_base + FIRIRCR);
+	cr = 0;
+	writel(cr, si->firi_base + FIRITCTR);
+}
+
+/*!
+ * This function initialises the UART.
+ *
+ * @param   si  FIRI port specific structure.
+ *
+ * @return  The function returns 0 on success.
+ */
+static int mxc_irda_uart_init(struct mxc_irda *si)
+{
+	unsigned int per_clk;
+	unsigned int num, denom, baud, ufcr = 0;
+	unsigned int cr;
+	int d = 1;
+	int uart_ir_mux = 0;
+
+	if (si->mxc_ir_plat)
+		uart_ir_mux = si->mxc_ir_plat->uart_ir_mux;
+	/*
+	 * Clear Status Registers 1 and 2
+	 **/
+	writel(0xFFFF, si->uart_base + MXC_UARTUSR1);
+	writel(0xFFFF, si->uart_base + MXC_UARTUSR2);
+
+	/* Configure the IOMUX for the UART */
+	gpio_firi_init();
+
+	per_clk = clk_get_rate(si->uart_clk);
+	baud = per_clk / 16;
+	if (baud > 1500000) {
+		baud = 1500000;
+		d = per_clk / ((baud * 16) + 1000);
+		if (d > 6) {
+			d = 6;
+		}
+	}
+	clk_enable(si->uart_clk);
+
+	si->uart_clk_rate = per_clk / d;
+	writel(si->uart_clk_rate / 1000, si->uart_base + MXC_UARTONEMS);
+
+	writel(si->mxc_ir_plat->ir_rx_invert | MXC_UARTUCR4_IRSC,
+	       si->uart_base + MXC_UARTUCR4);
+
+	if (uart_ir_mux) {
+		writel(MXC_UARTUCR3_RXDMUXSEL | si->mxc_ir_plat->ir_tx_invert |
+		       MXC_UARTUCR3_DSR, si->uart_base + MXC_UARTUCR3);
+	} else {
+		writel(si->mxc_ir_plat->ir_tx_invert | MXC_UARTUCR3_DSR,
+		       si->uart_base + MXC_UARTUCR3);
+	}
+
+	writel(MXC_UARTUCR2_IRTS | MXC_UARTUCR2_CTS | MXC_UARTUCR2_WS |
+	       MXC_UARTUCR2_ATEN | MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN,
+	       si->uart_base + MXC_UARTUCR2);
+	/* Wait till we are out of software reset */
+	do {
+		cr = readl(si->uart_base + MXC_UARTUCR2);
+	} while (!(cr & MXC_UARTUCR2_SRST));
+
+	ufcr |= (UART4_UFCR_TXTL << MXC_UARTUFCR_TXTL_OFFSET) |
+	    ((6 - d) << MXC_UARTUFCR_RFDIV_OFFSET) | UART4_UFCR_RXTL;
+	writel(ufcr, si->uart_base + MXC_UARTUFCR);
+
+	writel(MXC_UARTUCR1_UARTEN | MXC_UARTUCR1_IREN,
+	       si->uart_base + MXC_UARTUCR1);
+
+	baud = 9600;
+	num = baud / 100 - 1;
+	denom = si->uart_clk_rate / 1600 - 1;
+
+	if ((denom < 65536) && (si->uart_clk_rate > 1600)) {
+		writel(num, si->uart_base + MXC_UARTUBIR);
+		writel(denom, si->uart_base + MXC_UARTUBMR);
+	}
+
+	writel(0x0000, si->uart_base + MXC_UARTUTS);
+	return 0;
+
+}
+
+/*!
+ * This function enables FIRI port.
+ *
+ * @param   si  FIRI port specific structure.
+ *
+ * @return  The function returns 0 on success and a non-zero value on
+ *          failure.
+ */
+static int mxc_irda_startup(struct mxc_irda *si)
+{
+	int ret = 0;
+
+	mxc_irda_uart_init(si);
+	mxc_irda_firi_init(si);
+
+	/* configure FIRI device for speed */
+	ret = mxc_irda_set_speed(si, si->speed = 9600);
+
+	return ret;
+}
+
+/*!
+ * When an ifconfig is issued which changes the device flag to include
+ * IFF_UP this function is called. It is only called when the change
+ * occurs, not when the interface remains up. The function grabs the interrupt
+ * resources and registers FIRI interrupt service routines, requests for DMA
+ * channels, configures the DMA channel. It then initializes  the IOMUX
+ * registers to configure the pins for FIRI signals and finally initializes the
+ * various FIRI registers and enables the port for reception.
+ *
+ * @param   dev   net device structure that is being opened
+ *
+ * @return  The function returns 0 for a successful open and non-zero value
+ *          on failure.
+ */
+static int mxc_irda_start(struct net_device *dev)
+{
+	struct mxc_irda *si = netdev_priv(dev);
+	int err;
+	int ints_muxed = 0;
+	mxc_dma_device_t dev_id = 0;
+
+	if (si->uart_irq == si->uart_irq1)
+		ints_muxed = 1;
+
+	si->speed = 9600;
+
+	if (si->uart_irq == si->firi_irq) {
+		err =
+		    request_irq(si->uart_irq, mxc_irda_irq, 0, dev->name, dev);
+		if (err) {
+			dev_err(si->dev, "%s:Failed to request the IRQ\n",
+				__FUNCTION__);
+			return err;
+		}
+		/*
+		 * The interrupt must remain disabled for now.
+		 */
+		disable_irq(si->uart_irq);
+	} else {
+		err =
+		    request_irq(si->firi_irq, mxc_irda_irq, 0, dev->name, dev);
+		if (err) {
+			dev_err(si->dev, "%s:Failed to request FIRI IRQ\n",
+				__FUNCTION__);
+			return err;
+		}
+		/*
+		 * The interrupt must remain disabled for now.
+		 */
+		disable_irq(si->firi_irq);
+		if (ints_muxed) {
+
+			err = request_irq(si->uart_irq, mxc_irda_irq, 0,
+					  dev->name, dev);
+			if (err) {
+				dev_err(si->dev,
+					"%s:Failed to request UART IRQ\n",
+					__FUNCTION__);
+				goto err_irq1;
+			}
+			/*
+			 * The interrupt must remain disabled for now.
+			 */
+			disable_irq(si->uart_irq);
+		} else {
+			err = request_irq(si->uart_irq, mxc_irda_tx_irq, 0,
+					  dev->name, dev);
+			if (err) {
+				dev_err(si->dev,
+					"%s:Failed to request UART IRQ\n",
+					__FUNCTION__);
+				goto err_irq1;
+			}
+			err = request_irq(si->uart_irq1, mxc_irda_rx_irq, 0,
+					  dev->name, dev);
+			if (err) {
+				dev_err(si->dev,
+					"%s:Failed to request UART1 IRQ\n",
+					__FUNCTION__);
+				goto err_irq2;
+			}
+			/*
+			 * The interrupts must remain disabled for now.
+			 */
+			disable_irq(si->uart_irq);
+			disable_irq(si->uart_irq1);
+		}
+	}
+#ifdef FIRI_SDMA_RX
+	dev_id = MXC_DMA_FIR_RX;
+	si->rxdma_ch = mxc_dma_request(dev_id, "MXC FIRI RX");
+	if (si->rxdma_ch < 0) {
+		dev_err(si->dev, "Cannot allocate FIR DMA channel\n");
+		goto err_rx_dma;
+	}
+	mxc_dma_callback_set(si->rxdma_ch, mxc_irda_fir_dma_rx_irq,
+			     (void *)dev_get_drvdata(si->dev));
+#endif
+#ifdef FIRI_SDMA_TX
+
+	dev_id = MXC_DMA_FIR_TX;
+	si->txdma_ch = mxc_dma_request(dev_id, "MXC FIRI TX");
+	if (si->txdma_ch < 0) {
+		dev_err(si->dev, "Cannot allocate FIR DMA channel\n");
+		goto err_tx_dma;
+	}
+	mxc_dma_callback_set(si->txdma_ch, mxc_irda_fir_dma_tx_irq,
+			     (void *)dev_get_drvdata(si->dev));
+#endif
+	/* Setup the serial port port for the initial speed. */
+	err = mxc_irda_startup(si);
+	if (err) {
+		goto err_startup;
+	}
+
+	/* Open a new IrLAP layer instance. */
+	si->irlap = irlap_open(dev, &si->qos, "mxc");
+	err = -ENOMEM;
+	if (!si->irlap) {
+		goto err_irlap;
+	}
+
+	/* Now enable the interrupt and start the queue */
+	si->open = 1;
+	si->suspend = 0;
+
+	if (si->uart_irq == si->firi_irq) {
+		enable_irq(si->uart_irq);
+	} else {
+		enable_irq(si->firi_irq);
+		if (ints_muxed == 1) {
+			enable_irq(si->uart_irq);
+		} else {
+			enable_irq(si->uart_irq);
+			enable_irq(si->uart_irq1);
+		}
+	}
+
+	netif_start_queue(dev);
+	return 0;
+
+      err_irlap:
+	si->open = 0;
+	mxc_irda_disabledma(si);
+      err_startup:
+#ifdef FIRI_SDMA_TX
+	mxc_dma_free(si->txdma_ch);
+      err_tx_dma:
+#endif
+#ifdef FIRI_SDMA_RX
+	mxc_dma_free(si->rxdma_ch);
+      err_rx_dma:
+#endif
+	if (si->uart_irq1 && !ints_muxed)
+		free_irq(si->uart_irq1, dev);
+      err_irq2:
+	if (si->uart_irq != si->firi_irq)
+		free_irq(si->uart_irq, dev);
+      err_irq1:
+	if (si->firi_irq)
+		free_irq(si->firi_irq, dev);
+	return err;
+}
+
+/*!
+ * This function is called when IFF_UP flag has been cleared by the user via
+ * the ifconfig irda0 down command. This function stops any further
+ * transmissions being queued, and then disables the interrupts.
+ * Finally it resets the device.
+ * @param   dev   the net_device structure
+ *
+ * @return  int   the function always returns 0 indicating a success.
+ */
+static int mxc_irda_stop(struct net_device *dev)
+{
+	struct mxc_irda *si = netdev_priv(dev);
+	unsigned long flags;
+
+	/* Stop IrLAP */
+	if (si->irlap) {
+		irlap_close(si->irlap);
+		si->irlap = NULL;
+	}
+
+	netif_stop_queue(dev);
+
+	/*Save flags and disable the FIRI interrupts.. */
+	if (si->open) {
+		local_irq_save(flags);
+		disable_irq(si->uart_irq);
+		free_irq(si->uart_irq, dev);
+		if (si->uart_irq != si->firi_irq) {
+			disable_irq(si->firi_irq);
+			free_irq(si->firi_irq, dev);
+			if (si->uart_irq1 != si->uart_irq) {
+				disable_irq(si->uart_irq1);
+				free_irq(si->uart_irq1, dev);
+			}
+		}
+		local_irq_restore(flags);
+		si->open = 0;
+	}
+#ifdef FIRI_SDMA_RX
+	if (si->rxdma_ch) {
+		mxc_dma_disable(si->rxdma_ch);
+		mxc_dma_free(si->rxdma_ch);
+		if (si->dma_rx_buff_phy) {
+			dma_unmap_single(si->dev, si->dma_rx_buff_phy,
+					 IRDA_FRAME_SIZE_LIMIT,
+					 DMA_FROM_DEVICE);
+			si->dma_rx_buff_phy = 0;
+		}
+		si->rxdma_ch = 0;
+	}
+	tasklet_kill(&dma_rx_tasklet);
+#endif
+#ifdef FIRI_SDMA_TX
+	if (si->txdma_ch) {
+		mxc_dma_disable(si->txdma_ch);
+		mxc_dma_free(si->txdma_ch);
+		if (si->dma_tx_buff_phy) {
+			dma_unmap_single(si->dev, si->dma_tx_buff_phy,
+					 si->dma_tx_buff_len, DMA_TO_DEVICE);
+			si->dma_tx_buff_phy = 0;
+		}
+		si->txdma_ch = 0;
+	}
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_PM
+/*!
+ * This function is called to put the FIRI in a low power state. Refer to the
+ * document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device structure used to give information on which FIRI
+ *                to suspend
+ * @param   state the power state the device is entering
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_irda_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct mxc_irda *si = netdev_priv(ndev);
+	unsigned int cr;
+	unsigned long flags;
+
+	if (!si) {
+		return 0;
+	}
+	if (si->suspend == 1) {
+		dev_err(si->dev,
+			" suspend - Device is already suspended ... \n");
+		return 0;
+	}
+	if (si->open) {
+
+		netif_device_detach(ndev);
+		mxc_irda_disabledma(si);
+
+		/*Save flags and disable the FIRI interrupts.. */
+		local_irq_save(flags);
+		disable_irq(si->uart_irq);
+		if (si->uart_irq != si->firi_irq) {
+			disable_irq(si->firi_irq);
+			if (si->uart_irq != si->uart_irq1) {
+				disable_irq(si->uart_irq1);
+			}
+		}
+		local_irq_restore(flags);
+
+		/* Disable Tx and Rx and then disable the UART clock */
+		cr = readl(si->uart_base + MXC_UARTUCR2);
+		cr &= ~(MXC_UARTUCR2_TXEN | MXC_UARTUCR2_RXEN);
+		writel(cr, si->uart_base + MXC_UARTUCR2);
+		cr = readl(si->uart_base + MXC_UARTUCR1);
+		cr &= ~MXC_UARTUCR1_UARTEN;
+		writel(cr, si->uart_base + MXC_UARTUCR1);
+		clk_disable(si->uart_clk);
+
+		/*Disable Tx and Rx for FIRI and then disable the FIRI clock.. */
+		cr = readl(si->firi_base + FIRITCR);
+		cr &= ~FIRITCR_TE;
+		writel(cr, si->firi_base + FIRITCR);
+		cr = readl(si->firi_base + FIRIRCR);
+		cr &= ~FIRIRCR_RE;
+		writel(cr, si->firi_base + FIRIRCR);
+		clk_disable(si->firi_clk);
+
+		gpio_firi_inactive();
+
+		si->suspend = 1;
+		si->open = 0;
+	}
+	return 0;
+}
+
+/*!
+ * This function is called to bring the FIRI back from a low power state. Refer
+ * to the document driver-model/driver.txt in the kernel source tree for more
+ * information.
+ *
+ * @param   pdev  the device structure used to give information on which FIRI
+ *                to resume
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_irda_resume(struct platform_device *pdev)
+{
+	struct net_device *ndev = platform_get_drvdata(pdev);
+	struct mxc_irda *si = netdev_priv(ndev);
+	unsigned long flags;
+
+	if (!si) {
+		return 0;
+	}
+
+	if (si->suspend == 1 && !si->open) {
+
+		/*Initialise the UART first */
+		clk_enable(si->uart_clk);
+
+		/*Now init FIRI */
+		gpio_firi_active(si->firi_base + FIRITCR, FIRITCR_TPP);
+		mxc_irda_startup(si);
+
+		/* Enable the UART and FIRI interrupts.. */
+		local_irq_save(flags);
+		enable_irq(si->uart_irq);
+		if (si->uart_irq != si->firi_irq) {
+			enable_irq(si->firi_irq);
+			if (si->uart_irq != si->uart_irq1) {
+				enable_irq(si->uart_irq1);
+			}
+		}
+		local_irq_restore(flags);
+
+		/* Let the kernel know that we are alive and kicking.. */
+		netif_device_attach(ndev);
+
+		si->suspend = 0;
+		si->open = 1;
+	}
+	return 0;
+}
+#else
+#define mxc_irda_suspend NULL
+#define mxc_irda_resume  NULL
+#endif
+
+static int mxc_irda_init_iobuf(iobuff_t * io, int size)
+{
+	io->head = kmalloc(size, GFP_KERNEL | GFP_DMA);
+	if (io->head != NULL) {
+		io->truesize = size;
+		io->in_frame = FALSE;
+		io->state = OUTSIDE_FRAME;
+		io->data = io->head;
+	}
+	return io->head ? 0 : -ENOMEM;
+
+}
+
+static struct net_device_ops mxc_irda_ops = {
+	.ndo_start_xmit = mxc_irda_hard_xmit,
+	.ndo_open = mxc_irda_start,
+	.ndo_stop = mxc_irda_stop,
+	.ndo_do_ioctl = mxc_irda_ioctl,
+	.ndo_get_stats = mxc_irda_stats,
+};
+
+/*!
+ * This function is called during the driver binding process.
+ * This function requests for memory, initializes net_device structure and
+ * registers with kernel.
+ *
+ * @param   pdev  the device structure used to store device specific
+ *                information that is used by the suspend, resume and remove
+ *                functions
+ *
+ * @return  The function returns 0 on success and a non-zero value on failure
+ */
+static int mxc_irda_probe(struct platform_device *pdev)
+{
+	struct net_device *dev;
+	struct mxc_irda *si;
+	struct resource *uart_res, *firi_res;
+	int uart_irq, firi_irq, uart_irq1;
+	unsigned int baudrate_mask = 0;
+	int err;
+
+	uart_res = &pdev->resource[0];
+	uart_irq = pdev->resource[1].start;
+
+	firi_res = &pdev->resource[2];
+	firi_irq = pdev->resource[3].start;
+
+	uart_irq1 = pdev->resource[4].start;
+
+	if (!uart_res || uart_irq == NO_IRQ || !firi_res || firi_irq == NO_IRQ) {
+		dev_err(&pdev->dev, "Unable to find resources\n");
+		return -ENXIO;
+	}
+
+	err =
+	    request_mem_region(uart_res->start, SZ_16K,
+			       "MXC_IRDA") ? 0 : -EBUSY;
+	if (err) {
+		dev_err(&pdev->dev, "Failed to request UART memory region\n");
+		return -ENOMEM;
+	}
+
+	err =
+	    request_mem_region(firi_res->start, SZ_16K,
+			       "MXC_IRDA") ? 0 : -EBUSY;
+	if (err) {
+		dev_err(&pdev->dev, "Failed to request FIRI  memory region\n");
+		goto err_mem_1;
+	}
+
+	dev = alloc_irdadev(sizeof(struct mxc_irda));
+	if (!dev) {
+		goto err_mem_2;
+	}
+
+	si = netdev_priv(dev);
+	si->dev = &pdev->dev;
+
+	si->mxc_ir_plat = pdev->dev.platform_data;
+	si->uart_clk = si->mxc_ir_plat->uart_clk;
+
+	si->uart_res = uart_res;
+	si->firi_res = firi_res;
+	si->uart_irq = uart_irq;
+	si->firi_irq = firi_irq;
+	si->uart_irq1 = uart_irq1;
+
+	si->uart_base = ioremap(uart_res->start, SZ_16K);
+	si->firi_base = ioremap(firi_res->start, SZ_16K);
+
+	if (!(si->uart_base || si->firi_base)) {
+		err = -ENOMEM;
+		goto err_mem_3;
+	}
+
+	/*
+	 * Initialise the SIR buffers
+	 */
+	err = mxc_irda_init_iobuf(&si->rx_buff, UART_BUFF_SIZE);
+	if (err) {
+		goto err_mem_4;
+	}
+
+	err = mxc_irda_init_iobuf(&si->tx_buff, UART_BUFF_SIZE);
+	if (err) {
+		goto err_mem_5;
+	}
+
+	dev->netdev_ops = &mxc_irda_ops;
+
+	irda_init_max_qos_capabilies(&si->qos);
+
+	/*
+	 * We support
+	 * SIR(9600, 19200,38400, 57600 and 115200 bps)
+	 * FIR(4 Mbps)
+	 * Min Turn Time set to 1ms or greater.
+	 */
+	baudrate_mask |= IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200;
+	baudrate_mask |= IR_4000000 << 8;
+
+	si->qos.baud_rate.bits &= baudrate_mask;
+	si->qos.min_turn_time.bits = 0x7;
+
+	irda_qos_bits_to_value(&si->qos);
+
+#ifdef FIRI_SDMA_RX
+	si->tskb = NULL;
+	tasklet_init(&dma_rx_tasklet, mxc_irda_rx_task, (unsigned long)si);
+#endif
+	err = register_netdev(dev);
+	if (err == 0) {
+		platform_set_drvdata(pdev, dev);
+	} else {
+		kfree(si->tx_buff.head);
+	      err_mem_5:
+		kfree(si->rx_buff.head);
+	      err_mem_4:
+		iounmap(si->uart_base);
+		iounmap(si->firi_base);
+	      err_mem_3:
+		free_netdev(dev);
+	      err_mem_2:
+		release_mem_region(firi_res->start, SZ_16K);
+	      err_mem_1:
+		release_mem_region(uart_res->start, SZ_16K);
+	}
+	return err;
+}
+
+/*!
+ * Dissociates the driver from the FIRI device. Removes the appropriate FIRI
+ * port structure from the kernel.
+ *
+ * @param   pdev  the device structure used to give information on which FIRI
+ *                to remove
+ *
+ * @return  The function always returns 0.
+ */
+static int mxc_irda_remove(struct platform_device *pdev)
+{
+	struct net_device *dev = platform_get_drvdata(pdev);
+	struct mxc_irda *si = netdev_priv(dev);
+
+	if (si->uart_base)
+		iounmap(si->uart_base);
+	if (si->firi_base)
+		iounmap(si->firi_base);
+	if (si->firi_res->start)
+		release_mem_region(si->firi_res->start, SZ_16K);
+	if (si->uart_res->start)
+		release_mem_region(si->uart_res->start, SZ_16K);
+	if (si->tx_buff.head)
+		kfree(si->tx_buff.head);
+	if (si->rx_buff.head)
+		kfree(si->rx_buff.head);
+
+	platform_set_drvdata(pdev, NULL);
+	unregister_netdev(dev);
+	free_netdev(dev);
+
+	return 0;
+}
+
+/*!
+ * This structure contains pointers to the power management callback functions.
+ */
+static struct platform_driver mxcir_driver = {
+	.driver = {
+		   .name = "mxcir",
+		   },
+	.probe = mxc_irda_probe,
+	.remove = mxc_irda_remove,
+	.suspend = mxc_irda_suspend,
+	.resume = mxc_irda_resume,
+};
+
+/*!
+ * This function is used to initialize the FIRI driver module. The function
+ * registers the power management callback functions with the kernel and also
+ * registers the FIRI callback functions.
+ *
+ * @return  The function returns 0 on success and a non-zero value on failure.
+ */
+static int __init mxc_irda_init(void)
+{
+	return platform_driver_register(&mxcir_driver);
+}
+
+/*!
+ * This function is used to cleanup all resources before the driver exits.
+ */
+static void __exit mxc_irda_exit(void)
+{
+	platform_driver_unregister(&mxcir_driver);
+}
+
+module_init(mxc_irda_init);
+module_exit(mxc_irda_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_DESCRIPTION("MXC IrDA(SIR/FIR) driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/irda/mxc_ir.h b/drivers/net/irda/mxc_ir.h
new file mode 100644
index 000000000000..6b22ca129f27
--- /dev/null
+++ b/drivers/net/irda/mxc_ir.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __MXC_FIRI_REG_H__
+#define __MXC_FIRI_REG_H__
+
+#include <mach/hardware.h>
+
+/*!
+ * @defgroup FIRI Fast IR Driver
+ */
+
+/*!
+ * @file mxc_ir.h
+ *
+ * @brief  MXC FIRI header file
+ *
+ * This file defines base address and bits of FIRI registers
+ *
+ * @ingroup FIRI
+ */
+
+/*!
+ * FIRI maximum packet length
+ */
+#define FIR_MAX_RXLEN           2047
+
+/*
+ * FIRI Transmitter Control Register
+ */
+#define FIRITCR 0x00
+/*
+ * FIRI Transmitter Count Register
+ */
+#define FIRITCTR 0x04
+/*
+ * FIRI Receiver Control Register
+ */
+#define FIRIRCR 0x08
+/*
+ * FIRI Transmitter Status Register
+ */
+#define FIRITSR 0x0C
+/*
+ * FIRI Receiver Status Register
+ */
+#define FIRIRSR 0x10
+/*
+ * FIRI Transmitter FIFO
+ */
+#define FIRITXFIFO 0x14
+/*
+ * FIRI Receiver FIFO
+ */
+#define FIRIRXFIFO 0x18
+/*
+ * FIRI Control Register
+ */
+#define FIRICR 0x1C
+
+/*
+ * Bit definitions of Transmitter Controller Register
+ */
+#define FIRITCR_HAG     (1<<24)	/* H/W address generator */
+#define FIRITCR_SRF_FIR (0<<13)	/* Start field repeat factor */
+#define FIRITCR_SRF_MIR (1<<13)	/* Start field Repeat Factor */
+#define FIRITCR_TDT_MIR (2<<10)	/* TX trigger for MIR is set to 32 bytes) */
+#define FIRITCR_TDT_FIR (1<<10)	/* TX trigger for FIR is set to 16 bytes) */
+#define FIRITCR_TCIE    (1<<9)	/* TX Complete Interrupt Enable */
+#define FIRITCR_TPEIE   (1<<8)	/* TX Packet End Interrupt Enable */
+#define FIRITCR_TFUIE   (1<<7)	/* TX FIFO Under-run Interrupt Enable */
+#define FIRITCR_PCF     (1<<6)	/* Packet Complete by FIFO */
+#define FIRITCR_PC      (1<<5)	/* Packet Complete */
+#define FIRITCR_SIP     (1<<4)	/* TX Enable of SIP */
+#define FIRITCR_TPP     (1<<3)	/* TX Pulse Polarity bit */
+#define FIRITCR_TM_FIR  (0<<1)	/* TX Mode 4 Mbps */
+#define FIRITCR_TM_MIR1 (1<<1)	/* TX Mode 0.576 Mbps */
+#define FIRITCR_TM_MIR2 (1<<2)	/* TX Mode 1.152 Mbps */
+#define FIRITCR_TE      (1<<0)	/* TX Enable */
+
+/*
+ * Bit definitions of Transmitter Count Register
+ */
+#define FIRITCTR_TPL     511	/* TX Packet Length set to 512 bytes */
+
+/*
+ * Bit definitions of Receiver Control Register
+ */
+#define FIRIRCR_RAM     (1<<24)	/* RX Address Match */
+#define FIRIRCR_RPEDE   (1<<11)	/* Packet End DMA request Enable */
+#define FIRIRCR_RDT_MIR (2<<8)	/* DMA Trigger level(64 bytes in RXFIFO) */
+#define FIRIRCR_RDT_FIR (1<<8)	/* DMA Trigger level(16 bytes in RXFIFO) */
+#define FIRIRCR_RPA     (1<<7)	/* RX Packet Abort */
+#define FIRIRCR_RPEIE   (1<<6)	/* RX Packet End Interrupt Enable */
+#define FIRIRCR_PAIE    (1<<5)	/* Packet Abort Interrupt Enable */
+#define FIRIRCR_RFOIE   (1<<4)	/* RX FIFO Overrun Interrupt Enable */
+#define FIRIRCR_RPP     (1<<3)	/* RX Pulse Polarity bit */
+#define FIRIRCR_RM_FIR  (0<<1)	/* 4 Mbps */
+#define FIRIRCR_RM_MIR1 (1<<1)	/* 0.576 Mbps */
+#define FIRIRCR_RM_MIR2 (1<<2)	/* 1.152 Mbps */
+#define FIRIRCR_RE      (1<<0)	/* RX Enable */
+
+/* Transmitter Status Register */
+#define FIRITSR_TFP     0xFF00	/* Mask for available bytes in TX FIFO */
+#define FIRITSR_TC      (1<<3)	/* Transmit Complete bit */
+#define FIRITSR_SIPE    (1<<2)	/* SIP End bit */
+#define FIRITSR_TPE     (1<<1)	/* Transmit Packet End */
+#define FIRITSR_TFU     (1<<0)	/* TX FIFO Under-run */
+
+/* Receiver Status Register */
+#define FIRIRSR_RFP     0xFF00	/* mask for available bytes RX FIFO */
+#define FIRIRSR_PAS     (1<<5)	/* preamble search */
+#define FIRIRSR_RPE     (1<<4)	/* RX Packet End */
+#define FIRIRSR_RFO     (1<<3)	/* RX FIFO Overrun */
+#define FIRIRSR_BAM     (1<<2)	/* Broadcast Address Match */
+#define FIRIRSR_CRCE    (1<<1)	/* CRC error */
+#define FIRIRSR_DDE     (1<<0)	/* Address, control or data field error */
+
+/* FIRI Control Register */
+#define FIRICR_BL       (32<<5)	/* Burst Length is set to 32 */
+#define FIRICR_OSF      (0<<1)	/* Over Sampling Factor */
+
+#endif				/* __MXC_FIRI_REG_H__ */