diff options
| author | Troy Kisky <troy.kisky@boundarydevices.com> | 2015-06-09 12:15:35 -0700 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-12-24 01:27:30 +0100 |
| commit | 2cde66fe78792e8d7783287ea12b09f399e101c0 (patch) | |
| tree | 598abaa99f026cc0eb65b0cc2a32357fff0b943a /drivers/pci/host/pci-imx6.c | |
| parent | df5fd2ce051ab248d9d311740ef8c90fbbe3a046 (diff) | |
pci-imx6: fix reboot bug
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Max Krummenacher <max.krummenacher@toradex.com>
(cherry picked from commit df7b30b5b521fad21e682f318ee703be2144358b)
(cherry picked from commit 62785dfc6e934d8947b8367bf553dd2c81f5fb21)
Conflicts:
drivers/pci/host/pci-imx6.c
Diffstat (limited to 'drivers/pci/host/pci-imx6.c')
| -rw-r--r-- | drivers/pci/host/pci-imx6.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index 8de09e39edb9..24d7ea634453 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -96,6 +96,7 @@ struct imx_pcie { struct regulator *pcie_phy_regulator; struct regulator *pcie_bus_regulator; struct regulator *epdev_on; + int force_detect_state; }; /* PCIe Root Complex registers (memory-mapped) */ @@ -496,11 +497,7 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie) if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) && (gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) { - val = dw_pcie_readl_rc(pp, PCIE_PL_PFLR); - val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; - val |= PCIE_PL_PFLR_FORCE_LINK; - dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val); - + imx_pcie->force_detect_state = 1; regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); } @@ -1562,6 +1559,16 @@ static int imx_pcie_establish_link(struct imx_pcie *imx_pcie) goto out; } + if (imx_pcie->force_detect_state) { + u32 val; + + imx_pcie->force_detect_state = 0; + val = dw_pcie_readl_rc(pp, PCIE_PL_PFLR); + val &= ~PCIE_PL_PFLR_LINK_STATE_MASK; + val |= PCIE_PL_PFLR_FORCE_LINK; + dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val); + } + /* * Start Directed Speed Change so the best possible speed both link * partners support can be negotiated. |