diff options
| author | Tim Harvey <tharvey@gateworks.com> | 2014-08-07 23:36:40 -0700 |
|---|---|---|
| committer | Nitin Garg <nitin.garg@freescale.com> | 2015-09-17 09:20:24 -0500 |
| commit | c05303459272849fd572e0376a9827d7909d68f7 (patch) | |
| tree | c00405b8273e786ed0ceefe7933f53d2f4a62b29 /drivers/pci/host | |
| parent | efdb4003584734170b8d4bf909b66c8fe2a7c1d1 (diff) | |
PCI: imx6: Delay enabling reference clock for SS until it stabilizes
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is
running at the appropriate frequency.
Delay enabling the reference clock for the SS function until it has
stabilized. This prevents a high link failure rate (>5%) on certain IMX6
boards at various temperatures.
[bhelgaas: reword changelog slightly]
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
(cherry picked from commit 3fce0e882f61513c45c67e15bd0fde03341b58a5)
Diffstat (limited to 'drivers/pci/host')
| -rw-r--r-- | drivers/pci/host/pci-imx6.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c index b5988b4e56e5..233fe8a88264 100644 --- a/drivers/pci/host/pci-imx6.c +++ b/drivers/pci/host/pci-imx6.c @@ -257,11 +257,6 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); int ret; - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, - IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); - ret = clk_prepare_enable(imx6_pcie->pcie_phy); if (ret) { dev_err(pp->dev, "unable to enable pcie_phy clock\n"); @@ -283,6 +278,12 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) /* allow the clocks to stabilize */ usleep_range(200, 500); + /* power up core phy and enable ref clock */ + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, + IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); + /* Some boards don't have PCIe reset GPIO. */ if (gpio_is_valid(imx6_pcie->reset_gpio)) { gpio_set_value(imx6_pcie->reset_gpio, 0); |