diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2017-08-31 14:02:54 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:28:21 +0800 |
| commit | fcc8674b63b86ede00bec39789c909909c14b6a8 (patch) | |
| tree | 3e5fcde02d2f837288886ccdfaf97f655062b883 /drivers/pci | |
| parent | 636dba3b975510d3ea84c9a9cc7660431b1d7c4a (diff) | |
MLK-16345 PCI: imx: final workaround of ERR010728 for pcie
Description:
Initial VCO oscillation may fail under corner conditions such as
cold temperature. It causes PCIe PLL fail to lock in
initialization phase.
Project Impact:
iMX7D PCIe PLL fails to lock and PCIe doesn.t work.
workarounds:
To disable Duty-cycle Corrector(DCC) calibration after G_RST
signal is de-asserted by following the sequences:
1. De-assert the G_RST signal by clearing
SRC_PCIEPHY_RCR[PCIEPHY_G_RST].
2. de-assert DCC_FB_EN in Reg4 by writing data '0x29' to the register
address 0x306d0014.
3. assert RX_EQS, RX_EQ_SEL in Reg24 by writing data '0x48' to the
register address 0x306d0090.
4.assert ATT_MODE in Reg26 by writing data '0xbc' to the register
address 0x306d0098.
5.De-assert the CMN_RST signal by clearing register bit
SRC_PCIEPHY_RCR[PCIEPHY_BTN].
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/dwc/pci-imx6.c | 31 |
1 files changed, 19 insertions, 12 deletions
diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c index c7c413f6347c..91bf4b65f447 100644 --- a/drivers/pci/dwc/pci-imx6.c +++ b/drivers/pci/dwc/pci-imx6.c @@ -161,10 +161,15 @@ struct imx6_pcie { */ /* iMX7 PCIe PHY registers */ -#define PCIE_PHY_CMN_REG15 0x54 -#define PCIE_PHY_CMN_REG15_DLY_4 (1 << 2) -#define PCIE_PHY_CMN_REG15_PLL_PD (1 << 5) -#define PCIE_PHY_CMN_REG15_OVRD_PLL_PD (1 << 7) +#define PCIE_PHY_CMN_REG4 0x14 +#define PCIE_PHY_CMN_REG4_DCC_FB_EN (0x29) + +#define PCIE_PHY_CMN_REG24 0x90 +#define PCIE_PHY_CMN_REG24_RX_EQ BIT(6) +#define PCIE_PHY_CMN_REG24_RX_EQ_SEL BIT(3) + +#define PCIE_PHY_CMN_REG26 0x98 +#define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC /* iMX8 HSIO registers */ #define IMX8QM_LPCG_PHYX2_OFFSET 0x00000 @@ -747,14 +752,16 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) if (unlikely(imx6_pcie->phy_base == NULL)) { pr_err("phy base shouldn't be null.\n"); } else { - writel(PCIE_PHY_CMN_REG15_DLY_4, - imx6_pcie->phy_base + PCIE_PHY_CMN_REG15); - writel(PCIE_PHY_CMN_REG15_DLY_4 - | PCIE_PHY_CMN_REG15_PLL_PD - | PCIE_PHY_CMN_REG15_OVRD_PLL_PD, - imx6_pcie->phy_base + PCIE_PHY_CMN_REG15); - writel(PCIE_PHY_CMN_REG15_DLY_4, - imx6_pcie->phy_base + PCIE_PHY_CMN_REG15); + /* De-assert DCC_FB_EN by writing data "0x29". */ + writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, + imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); + /* Assert RX_EQS and RX_EQS_SEL */ + writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL + | PCIE_PHY_CMN_REG24_RX_EQ, + imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); + /* Assert ATT_MODE by writing data "0xBC". */ + writel(PCIE_PHY_CMN_REG26_ATT_MODE, + imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); } regmap_update_bits(imx6_pcie->reg_src, 0x2c, BIT(2), 0); |