diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2013-02-07 18:45:23 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:59:31 -0700 |
| commit | 8ccecfe3e9481430ba01b92a348f98d58ea81a46 (patch) | |
| tree | 8aca54dba3de768a815ec930d11e85965f6fbfe8 /drivers/pinctrl/pinctrl-max77660.c | |
| parent | 47cf7901a67047055c18456c4caaac591cea4484 (diff) | |
pinctrl: max77660: add init flag for pins which is configured as gpio
If any pin is configured as gpio and if it is require in gpio output
mode then provide provision to set the initial state of the pins.
bug 1232806
Change-Id: Ibdf34518a22c3d6b3c02d86f10186fc4be89bab4
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/198371
Diffstat (limited to 'drivers/pinctrl/pinctrl-max77660.c')
| -rw-r--r-- | drivers/pinctrl/pinctrl-max77660.c | 46 |
1 files changed, 43 insertions, 3 deletions
diff --git a/drivers/pinctrl/pinctrl-max77660.c b/drivers/pinctrl/pinctrl-max77660.c index 86ba53c9c2fa..9a972195beb0 100644 --- a/drivers/pinctrl/pinctrl-max77660.c +++ b/drivers/pinctrl/pinctrl-max77660.c @@ -23,6 +23,7 @@ #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/delay.h> +#include <linux/gpio.h> #include <linux/pm.h> #include <linux/mfd/max77660/max77660-core.h> @@ -63,6 +64,37 @@ struct max77660_pinctrl_config max77660_pin_data[MAX77660_PINS_MAX] = { MAX77660_PIN(GPIO9, 1, 1), }; +static int max77660_init_pin_gpio_mode(struct device *dev, + unsigned offset, unsigned flag) +{ + struct device *parent = dev->parent; + u8 val; + int ret; + + if (flag & GPIOF_DIR_IN) + return 0; + + if (flag & GPIOF_INIT_HIGH) + val = MAX77660_CNFG_GPIO_OUTPUT_VAL_HIGH; + else + val = MAX77660_CNFG_GPIO_OUTPUT_VAL_LOW; + + ret = max77660_reg_update(parent, MAX77660_PWR_SLAVE, + MAX77660_REG_CNFG_GPIO0 + offset, + val, MAX77660_CNFG_GPIO_OUTPUT_VAL_MASK); + if (ret < 0) { + dev_err(dev, "CNFG_GPIOx val update failed: %d\n", ret); + return ret; + } + + ret = max77660_reg_update(parent, MAX77660_PWR_SLAVE, + MAX77660_REG_CNFG_GPIO0 + offset, MAX77660_CNFG_GPIO_DIR_OUTPUT, + MAX77660_CNFG_GPIO_DIR_MASK); + if (ret < 0) + dev_err(dev, "CNFG_GPIOx dir update failed: %d\n", ret); + return ret; +} + static int __devinit max77660_pinctrl_probe(struct platform_device *pdev) { struct max77660_platform_data *pdata; @@ -136,20 +168,28 @@ skip_pup_dn: return ret; } - if (pctrl_pdata->gpio_pin_mode) + if (pctrl_pdata->gpio_pin_mode) { + ret = max77660_init_pin_gpio_mode(&pdev->dev, i, + pctrl_pdata->gpio_init_flag); + if (ret < 0) { + dev_err(&pdev->dev, + "Pin init failed: %d\n", ret); + return ret; + } ret = max77660_reg_clr_bits(parent, MAX77660_PWR_SLAVE, MAX77660_REG_AME1_GPIO + pcfg->reg_offset, pcfg->ame_mask); - else + } else { ret = max77660_reg_set_bits(parent, MAX77660_PWR_SLAVE, MAX77660_REG_AME1_GPIO + pcfg->reg_offset, pcfg->ame_mask); + } if (ret < 0) { dev_err(&pdev->dev, "AMEx_GPIO update failed: %d\n", ret); return ret; } - }; + } return 0; } |