diff options
| author | Pritesh Raithatha <praithatha@nvidia.com> | 2012-11-30 18:46:32 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:44:40 -0700 |
| commit | 4ddb93ee17386f6634816bdda563c10dc07b3b5e (patch) | |
| tree | 0780fce41cd24fddf2b2e8d5d2b638e9e8417e4d /drivers/pinctrl/pinctrl-tegra.h | |
| parent | 8e2ca518f7aba12e564998ec32d2df4d374d1463 (diff) | |
pinctrl: tegra: add drive-type config param
drive-type is not supported for pinctrl-tegra20 and pinctrl-tegra30
so set drvtype_reg to -1 for them.
Bug 1003210
Change-Id: I330fb8049a3e3d6f905e385aedb782d06f1ca002
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/167754
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'drivers/pinctrl/pinctrl-tegra.h')
| -rw-r--r-- | drivers/pinctrl/pinctrl-tegra.h | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h index 4c69d808cb6a..c45b36e57aca 100644 --- a/drivers/pinctrl/pinctrl-tegra.h +++ b/drivers/pinctrl/pinctrl-tegra.h @@ -1,7 +1,7 @@ /* * Driver for the NVIDIA Tegra pinmux * - * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -69,6 +69,10 @@ struct tegra_function { * @slwr_width: Slew Rising field width. 0 if unsupported. * @slwf_bit: Slew Falling register bit. 0 if unsupported. * @slwf_width: Slew Falling field width. 0 if unsupported. + * @drvtype_reg: Drive type fields register offset. -1 if unsupported. + * @drvtype_bank: Drive type fields register bank. 0 if unsupported. + * @drvtype_bit: Drive type register bit. 0 if unsupported. + * @drvtype_width: Drive type field width. 0 if unsupported. * * A representation of a group of pins (possibly just one pin) in the Tegra * pin controller. Each group allows some parameter or parameters to be @@ -92,6 +96,7 @@ struct tegra_pingroup { s16 ioreset_reg; s16 rcv_sel_reg; s16 drv_reg; + s16 drvtype_reg; u32 mux_bank:2; u32 pupd_bank:2; u32 tri_bank:2; @@ -101,6 +106,7 @@ struct tegra_pingroup { u32 rcv_sel_bank:2; u32 lock_bank:2; u32 drv_bank:2; + u32 drvtype_bank:2; u32 mux_bit:5; u32 pupd_bit:5; u32 tri_bit:5; @@ -116,10 +122,12 @@ struct tegra_pingroup { u32 drvup_bit:5; u32 slwr_bit:5; u32 slwf_bit:5; + u32 drvtype_bit:5; u32 drvdn_width:6; u32 drvup_width:6; u32 slwr_width:6; u32 slwf_width:6; + u32 drvtype_width:6; }; /** |