diff options
| author | Timo Alho <talho@nvidia.com> | 2014-05-01 21:00:16 +0300 |
|---|---|---|
| committer | Mandar Padmawar <mpadmawar@nvidia.com> | 2014-05-08 22:45:48 -0700 |
| commit | 59b217ee39041b0fe877093b61ed563b87ee6749 (patch) | |
| tree | b0c9b5447c68d88255bf139371b784e74c4ddf9d /drivers/platform | |
| parent | 5e9e0e798b8285f4119de6cd316ba0924f9db88f (diff) | |
arm: tegra: sysedp: Update AP+DRAM table for T132
Bug 1469388
Change-Id: I54cf4e56b0ee7041697a5bf373e9012bff789dc1
Signed-off-by: Timo Alho <talho@nvidia.com>
Reviewed-on: http://git-master/r/404025
(cherry picked from commit 54ff9f73e27a7d61f01a92bd8d887b9c4fc43ebe)
Reviewed-on: http://git-master/r/406403
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Diffstat (limited to 'drivers/platform')
| -rw-r--r-- | drivers/platform/tegra/tegra13_edp.c | 65 |
1 files changed, 31 insertions, 34 deletions
diff --git a/drivers/platform/tegra/tegra13_edp.c b/drivers/platform/tegra/tegra13_edp.c index 017cc97b080e..9976f0c308c4 100644 --- a/drivers/platform/tegra/tegra13_edp.c +++ b/drivers/platform/tegra/tegra13_edp.c @@ -20,40 +20,37 @@ #ifdef CONFIG_SYSEDP_FRAMEWORK static struct tegra_sysedp_corecap t132_sysedp_corecap[] = { -/* - Initial table for T132 -*/ - /*mW CPU intensive load GPU intensive load */ - /*mW budget gpu(khz) mem(khz) budget gpu(khz) mem(khz) pthrot(mW)*/ - {5000, {4000, 108000, 933000}, {4000, 108000, 933000}, 918 }, - {6000, {6000, 108000, 933000}, {4500, 180000, 933000}, 2109 }, - {7000, {7000, 180000, 933000}, {4500, 396000, 933000}, 2589 }, - {8000, {7000, 180000, 933000}, {4500, 468000, 933000}, 3068 }, - {9000, {8000, 252000, 933000}, {4500, 612000, 933000}, 3630 }, - {10000, {10000, 252000, 933000}, {7500, 396000, 933000}, 4425 }, - {11000, {10000, 396000, 933000}, {7000, 468000, 933000}, 5301 }, - {12000, {12000, 324000, 933000}, {7000, 612000, 933000}, 5253 }, - {13000, {13000, 324000, 933000}, {7000, 684000, 933000}, 6874 }, - {14000, {14000, 252000, 933000}, {7000, 708000, 933000}, 6771 }, - {15000, {14000, 396000, 933000}, {7500, 708000, 933000}, 7819 }, - {16000, {14000, 468000, 933000}, {7000, 804000, 933000}, 8053 }, - {17000, {14000, 468000, 933000}, {7000, 853000, 933000}, 8975 }, - {18000, {14000, 540000, 933000}, {7500, 853000, 933000}, 9204 }, - {19000, {14000, 612000, 933000}, {9000, 853000, 933000}, 9998 }, - {20000, {14000, 612000, 933000}, {10000, 853000, 933000}, 10825 }, - {21000, {14000, 708000, 933000}, {10500, 853000, 933000}, 10908 }, - {22000, {14000, 708000, 933000}, {12000, 853000, 933000}, 11305 }, - {23000, {14000, 708000, 933000}, {12500, 853000, 933000}, 12696 }, - {24000, {14000, 756000, 933000}, {13000, 853000, 933000}, 13524 }, - {25000, {14000, 853000, 933000}, {14000, 853000, 933000}, 13524 }, - {26000, {14000, 853000, 933000}, {14000, 853000, 933000}, 13999 }, - {27000, {14000, 853000, 933000}, {14000, 853000, 933000}, 15002 }, - {28000, {14000, 853000, 933000}, {14000, 853000, 933000}, 15022 }, - {29000, {14000, 853000, 933000}, {14000, 853000, 933000}, 15621 }, - {30000, {14000, 853000, 933000}, {14000, 853000, 933000}, 15621 }, - {31000, {14000, 853000, 933000}, {14000, 853000, 933000}, 15621 }, - {32000, {14000, 853000, 933000}, {14000, 853000, 933000}, 16330 }, - {33000, {14000, 853000, 933000}, {14000, 853000, 933000}, 17721 }, + /*mW CPU intensive load GPU intensive load */ + /*mW budget gpu(khz) mem(khz) budget gpu(khz) mem(khz) pthrot(mW)*/ + {5000, {3000, 180000, 933000}, {3000, 180000, 933000}, 2739 }, + {6000, {4000, 180000, 933000}, {3500, 252000, 933000}, 3509 }, + {7000, {5000, 180000, 933000}, {3500, 324000, 933000}, 4084 }, + {8000, {6000, 252000, 933000}, {3500, 396000, 933000}, 4564 }, + {9000, {6000, 180000, 933000}, {3500, 468000, 933000}, 5043 }, + {10000, {7000, 180000, 933000}, {6000, 396000, 933000}, 5868 }, + {11000, {7000, 252000, 933000}, {6000, 468000, 933000}, 6348 }, + {12000, {7000, 396000, 933000}, {6500, 468000, 933000}, 7307 }, + {13000, {9000, 180000, 933000}, {6000, 540000, 933000}, 7714 }, + {14000, {10000, 252000, 933000}, {6000, 612000, 933000}, 8835 }, + {15000, {10000, 324000, 933000}, {6000, 684000, 933000}, 9600 }, + {16000, {11000, 252000, 933000}, {6000, 708000, 933000}, 9978 }, + {17000, {12000, 180000, 933000}, {6000, 756000, 933000}, 10434 }, + {18000, {12000, 324000, 933000}, {7000, 756000, 933000}, 11393 }, + {19000, {13000, 252000, 933000}, {7000, 804000, 933000}, 11935 }, + {20000, {13000, 324000, 933000}, {7500, 804000, 933000}, 12414 }, + {21000, {14000, 252000, 933000}, {6500, 853000, 933000}, 13643 }, + {22000, {14000, 396000, 933000}, {9000, 853000, 933000}, 14602 }, + {23000, {15000, 252000, 933000}, {9000, 853000, 933000}, 13643 }, + {24000, {16000, 180000, 933000}, {9500, 853000, 933000}, 14432 }, + {25000, {16800, 180000, 933000}, {10000, 853000, 933000}, 15815 }, + {26000, {16800, 324000, 933000}, {11000, 853000, 933000}, 16774 }, + {27000, {16800, 468000, 933000}, {11000, 853000, 933000}, 17733 }, + {28000, {16800, 540000, 933000}, {11500, 853000, 933000}, 18479 }, + {29000, {16800, 540000, 933000}, {13000, 853000, 933000}, 18479 }, + {30000, {16800, 648000, 933000}, {13000, 853000, 933000}, 20252 }, + {31000, {16800, 708000, 933000}, {13500, 853000, 933000}, 21407 }, + {32000, {16800, 708000, 933000}, {14000, 853000, 933000}, 21407 }, + {33000, {16800, 756000, 933000}, {14500, 853000, 933000}, 22430 }, }; struct tegra_sysedp_corecap *tegra_get_sysedp_corecap(unsigned int *sz) |