diff options
| author | Leonard Crestez <leonard.crestez@nxp.com> | 2018-05-08 21:19:36 +0300 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:31:24 +0800 |
| commit | f2792f57e8386e3ac493a5c5b0af84d944340da2 (patch) | |
| tree | d4114d5572db5b6806120a656ab6a6926fc41188 /drivers/soc | |
| parent | aed41aebab6e0ae826a27943c6f8f550ac48975b (diff) | |
MLK-18138-1: soc: imx: gpc: Spin on generic GPC_CNTR bit, not GPU_VPU stuff
This was introduced while porting patches from imx_4.9.y. In the 4.9
branch there are specific power_on and power_off functions for PU but in
upstream this code was refactored to make the code generic for each PGC
block.
Fixes: ce181a6440dc ("MLK-13479-1: ARM: imx: gpc: delay 2us instead of sw+sw2iso delay")
While we're at it remove GPU_VPU_{PUP,PND}_REQ because they're not used.
Upstream forgot to delete these bits while refactoring.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/imx/gpc.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gpc.c index 5de0eefe3cf4..e9e61f77eb04 100644 --- a/drivers/soc/imx/gpc.c +++ b/drivers/soc/imx/gpc.c @@ -49,9 +49,6 @@ #define GPC_PGC_DISP_PDN 0x240 #define GPC_PGC_DISP_SR 0x24c -#define GPU_VPU_PUP_REQ BIT(1) -#define GPU_VPU_PDN_REQ BIT(0) - #define GPC_CLK_MAX 10 #define DEFAULT_IPG_RATE 66000000 #define GPC_PU_UP_DELAY_MARGIN 2 @@ -116,7 +113,7 @@ static void _imx6_pm_domain_power_off(struct generic_pm_domain *genpd) /* Wait ISO + ISO2SW IPG clock cycles */ udelay(DIV_ROUND_UP(iso + iso2sw, pd->ipg_rate_mhz)); - while (readl_relaxed(gpc_base + GPC_CNTR) & GPU_VPU_PDN_REQ) + while (readl_relaxed(gpc_base + GPC_CNTR) & val) ; } @@ -153,7 +150,7 @@ static void _imx6_pm_domain_power_on(struct generic_pm_domain *genpd) val = BIT(pd->cntr_pdn_bit + 1); regmap_update_bits(pd->regmap, GPC_CNTR, val, val); - while (readl_relaxed(gpc_base + GPC_CNTR) & GPU_VPU_PUP_REQ) + while (readl_relaxed(gpc_base + GPC_CNTR) & val) ; /* Wait power switch done */ udelay(2 * DEFAULT_IPG_RATE / ipg_rate + |