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authorTomoya MORINAGA <tomoya.rohm@gmail.com>2011-12-09 13:13:28 +0900
committerGrant Likely <grant.likely@secretlab.ca>2012-03-09 20:57:28 -0700
commitf258b44e22e07f5e98ac2260c70acff5784791b6 (patch)
treeba56ceefdfac4fae105ef098d036a128606fb097 /drivers/spi
parent7d05b3e868ee0f9231baf40cb77be3df5dd1f18c (diff)
spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
This patch supports a spi mode setup and bit order setup by IO control. spi mode: mode 0 to mode 3 bit order: LSB first, MSB first Signed-off-by: Tomoya MORINAGA <tomoya.rohm@gmail.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/spi')
-rw-r--r--drivers/spi/spi-topcliff-pch.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 4fdb83a765d8..5a477e91426f 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -1434,6 +1434,7 @@ static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev)
master->num_chipselect = PCH_MAX_CS;
master->setup = pch_spi_setup;
master->transfer = pch_spi_transfer;
+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
data->board_dat = board_dat;
data->plat_dev = plat_dev;