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authorHenry Ptasinski <henryp@broadcom.com>2011-06-29 16:46:51 -0700
committerGreg Kroah-Hartman <gregkh@suse.de>2011-07-05 09:57:13 -0700
commit8a76f1eee1cb8933fb22d1211fdb4358513c3239 (patch)
tree6aa7557c74ede84935b61938330cb029c1250c18 /drivers/staging/brcm80211/brcmsmac
parentafe6867f969009c5a4cad520179801c782ca63aa (diff)
staging: brcm80211: run scripts/cleanfile to remove whitespace errors
Used scripts/cleanfile to remove assorted whitespace errors. Signed-off-by: Henry Ptasinski <henryp@broadcom.com> Reviewed-by: Roland Vossen <rvossen@broadcom.com> Reviewed-by: Arend van Spriel <arend@broadcom.com> Reviewed-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/staging/brcm80211/brcmsmac')
-rw-r--r--drivers/staging/brcm80211/brcmsmac/d11.h30
-rw-r--r--drivers/staging/brcm80211/brcmsmac/main.c6
-rw-r--r--drivers/staging/brcm80211/brcmsmac/nicpci.c10
-rw-r--r--drivers/staging/brcm80211/brcmsmac/otp.c4
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phy_hal.h6
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phy_int.h4
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.c18
-rw-r--r--drivers/staging/brcm80211/brcmsmac/phy/phyreg_n.h14
-rw-r--r--drivers/staging/brcm80211/brcmsmac/rate.h6
-rw-r--r--drivers/staging/brcm80211/brcmsmac/scb.h2
-rw-r--r--drivers/staging/brcm80211/brcmsmac/types.h2
11 files changed, 51 insertions, 51 deletions
diff --git a/drivers/staging/brcm80211/brcmsmac/d11.h b/drivers/staging/brcm80211/brcmsmac/d11.h
index 44f4bc0f243c..bb8bb380d832 100644
--- a/drivers/staging/brcm80211/brcmsmac/d11.h
+++ b/drivers/staging/brcm80211/brcmsmac/d11.h
@@ -1148,25 +1148,25 @@ struct tx_status {
#define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2)
/* CW RSSI for LCNPHY */
-#define M_LCN_RSSI_0 0x1332
-#define M_LCN_RSSI_1 0x1338
-#define M_LCN_RSSI_2 0x133e
-#define M_LCN_RSSI_3 0x1344
+#define M_LCN_RSSI_0 0x1332
+#define M_LCN_RSSI_1 0x1338
+#define M_LCN_RSSI_2 0x133e
+#define M_LCN_RSSI_3 0x1344
/* SNR for LCNPHY */
-#define M_LCN_SNR_A_0 0x1334
-#define M_LCN_SNR_B_0 0x1336
+#define M_LCN_SNR_A_0 0x1334
+#define M_LCN_SNR_B_0 0x1336
-#define M_LCN_SNR_A_1 0x133a
-#define M_LCN_SNR_B_1 0x133c
+#define M_LCN_SNR_A_1 0x133a
+#define M_LCN_SNR_B_1 0x133c
-#define M_LCN_SNR_A_2 0x1340
-#define M_LCN_SNR_B_2 0x1342
+#define M_LCN_SNR_A_2 0x1340
+#define M_LCN_SNR_B_2 0x1342
-#define M_LCN_SNR_A_3 0x1346
-#define M_LCN_SNR_B_3 0x1348
+#define M_LCN_SNR_A_3 0x1346
+#define M_LCN_SNR_B_3 0x1348
-#define M_LCN_LAST_RESET (81*2)
+#define M_LCN_LAST_RESET (81*2)
#define M_LCN_LAST_LOC (63*2)
#define M_LCNPHY_RESET_STATUS (4902)
#define M_LCNPHY_DSC_TIME (0x98d*2)
@@ -1279,7 +1279,7 @@ struct shm_acparams {
/* Flags in M_HOST_FLAGS4 */
#define MHF4_BPHY_TXCORE0 0x0080 /* force bphy Tx on core 0 (board level WAR) */
-#define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */
+#define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */
/* Flags in M_HOST_FLAGS5 */
#define MHF5_4313_GPIOCTRL 0x0001
@@ -1673,7 +1673,7 @@ struct macstat {
#define BPHY_PEAK_ENERGY_HI 0x34
#define BPHY_SYNC_CTL 0x35
#define BPHY_TX_PWR_CTRL 0x36
-#define BPHY_TX_EST_PWR 0x37
+#define BPHY_TX_EST_PWR 0x37
#define BPHY_STEP 0x38
#define BPHY_WARMUP 0x39
#define BPHY_LMS_CFF_READ 0x3a
diff --git a/drivers/staging/brcm80211/brcmsmac/main.c b/drivers/staging/brcm80211/brcmsmac/main.c
index 0eba6da839d7..7c91b0ba2711 100644
--- a/drivers/staging/brcm80211/brcmsmac/main.c
+++ b/drivers/staging/brcm80211/brcmsmac/main.c
@@ -224,7 +224,7 @@ const u8 prio2fifo[NUMPRIO] = {
#define _WLC_PREC_NC 14 /* NC - Network Control */
#define MAXMACLIST 64 /* max # source MAC matches */
-#define BCN_TEMPLATE_COUNT 2
+#define BCN_TEMPLATE_COUNT 2
#define WLC_BSSCFG_HW_BCN 0x20 /* The BSS is generating beacons in HW */
@@ -856,7 +856,7 @@ ratespec_t brcms_c_lowest_basic_rspec(struct brcms_c_info *wlc,
/* This function changes the phytxctl for beacon based on current beacon ratespec AND txant
* setting as per this table:
* ratespec CCK ant = wlc->stf->txant
- * OFDM ant = 3
+ * OFDM ant = 3
*/
void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
ratespec_t bcn_rspec)
@@ -1356,7 +1356,7 @@ struct wlc_pub *brcms_c_pub(void *wlc)
return ((struct brcms_c_info *) wlc)->pub;
}
-#define CHIP_SUPPORTS_11N(wlc) 1
+#define CHIP_SUPPORTS_11N(wlc) 1
/*
* The common driver entry routine. Error codes should be unique
diff --git a/drivers/staging/brcm80211/brcmsmac/nicpci.c b/drivers/staging/brcm80211/brcmsmac/nicpci.c
index 70d41735c0a1..a5eebf3f5aa7 100644
--- a/drivers/staging/brcm80211/brcmsmac/nicpci.c
+++ b/drivers/staging/brcm80211/brcmsmac/nicpci.c
@@ -65,9 +65,9 @@
#define MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
/* serdes regs (rev < 10) */
-#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
-#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
-#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
+#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
+#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
+#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
/* SERDES RX registers */
#define SERDES_RX_CTRL 1 /* Rx cntrl */
@@ -100,8 +100,8 @@
#define PCIE_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
/* different register spaces to access thr'u pcie indirect access */
-#define PCIE_CONFIGREGS 1 /* Access to config space */
-#define PCIE_PCIEREGS 2 /* Access to pcie registers */
+#define PCIE_CONFIGREGS 1 /* Access to config space */
+#define PCIE_PCIEREGS 2 /* Access to pcie registers */
/* PCIE protocol PHY diagnostic registers */
#define PCIE_PLP_STATUSREG 0x204 /* Status */
diff --git a/drivers/staging/brcm80211/brcmsmac/otp.c b/drivers/staging/brcm80211/brcmsmac/otp.c
index 4e19b35b9f42..7edc435bfe9c 100644
--- a/drivers/staging/brcm80211/brcmsmac/otp.c
+++ b/drivers/staging/brcm80211/brcmsmac/otp.c
@@ -460,8 +460,8 @@ static otp_fn_t ipxotp_fn = {
* otp_size()
* otp_read_bit()
* otp_init()
- * otp_read_region()
- * otp_nvread()
+ * otp_read_region()
+ * otp_nvread()
*/
int otp_status(void *oh)
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_hal.h b/drivers/staging/brcm80211/brcmsmac/phy/phy_hal.h
index 756ad715596a..3c125c3f476f 100644
--- a/drivers/staging/brcm80211/brcmsmac/phy/phy_hal.h
+++ b/drivers/staging/brcm80211/brcmsmac/phy/phy_hal.h
@@ -80,9 +80,9 @@
#define PHY_MUTE_FOR_PREISM 1
#define PHY_MUTE_ALL 0xffffffff
-#define PHY_NOISE_FIXED_VAL (-95)
-#define PHY_NOISE_FIXED_VAL_NPHY (-92)
-#define PHY_NOISE_FIXED_VAL_LCNPHY (-92)
+#define PHY_NOISE_FIXED_VAL (-95)
+#define PHY_NOISE_FIXED_VAL_NPHY (-92)
+#define PHY_NOISE_FIXED_VAL_LCNPHY (-92)
#define PHY_MODE_CAL 0x0002
#define PHY_MODE_NOISEM 0x0004
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_int.h b/drivers/staging/brcm80211/brcmsmac/phy/phy_int.h
index 9506da5d2dac..68938feb6cc7 100644
--- a/drivers/staging/brcm80211/brcmsmac/phy/phy_int.h
+++ b/drivers/staging/brcm80211/brcmsmac/phy/phy_int.h
@@ -63,7 +63,7 @@ typedef void (*detachfn_t) (phy_info_t *);
#undef ISNPHY
#undef ISLCNPHY
#define ISNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_N)
-#define ISLCNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
+#define ISLCNPHY(pi) PHYTYPE_IS((pi)->pubpi.phy_type, PHY_TYPE_LCN)
#define ISPHY_11N_CAP(pi) (ISNPHY(pi) || ISLCNPHY(pi))
@@ -1092,7 +1092,7 @@ extern void wlc_phy_txpower_recalc_target(phy_info_t *pi);
#define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
#define LCNPHY_TX_POWER_TABLE_SIZE 128
#define LCNPHY_MAX_TX_POWER_INDEX (LCNPHY_TX_POWER_TABLE_SIZE - 1)
-#define LCNPHY_TBL_ID_TXPWRCTL 0x07
+#define LCNPHY_TBL_ID_TXPWRCTL 0x07
#define LCNPHY_TX_PWR_CTRL_OFF 0
#define LCNPHY_TX_PWR_CTRL_SW (0x1 << 15)
#define LCNPHY_TX_PWR_CTRL_HW ((0x1 << 15) | \
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.c b/drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.c
index efa985c5fe7a..4d35e5de543c 100644
--- a/drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.c
+++ b/drivers/staging/brcm80211/brcmsmac/phy/phy_lcn.c
@@ -26,8 +26,8 @@
#include "phy_lcn.h"
#define PLL_2064_NDIV 90
-#define PLL_2064_LOW_END_VCO 3000
-#define PLL_2064_LOW_END_KVCO 27
+#define PLL_2064_LOW_END_VCO 3000
+#define PLL_2064_LOW_END_KVCO 27
#define PLL_2064_HIGH_END_VCO 4200
#define PLL_2064_HIGH_END_KVCO 68
#define PLL_2064_LOOP_BW_DOUBLER 200
@@ -38,7 +38,7 @@
#define PLL_2064_MHZ 1000000
#define PLL_2064_OPEN_LOOP_DELAY 5
-#define TEMPSENSE 1
+#define TEMPSENSE 1
#define VBATSENSE 2
#define NOISE_IF_UPD_CHK_INTERVAL 1
@@ -50,10 +50,10 @@
#define NOISE_IF_CHK 1
#define NOISE_IF_ON 2
-#define PAPD_BLANKING_PROFILE 3
+#define PAPD_BLANKING_PROFILE 3
#define PAPD2LUT 0
-#define PAPD_CORR_NORM 0
-#define PAPD_BLANKING_THRESHOLD 0
+#define PAPD_CORR_NORM 0
+#define PAPD_BLANKING_THRESHOLD 0
#define PAPD_STOP_AFTER_LAST_UPDATE 0
#define LCN_TARGET_PWR 60
@@ -108,9 +108,9 @@
#define LCNPHY_TBL_ID_SAMPLEPLAY 0x15
#define LCNPHY_TBL_ID_SAMPLEPLAY1 0x16
-#define LCNPHY_TX_PWR_CTRL_RATE_OFFSET 832
-#define LCNPHY_TX_PWR_CTRL_MAC_OFFSET 128
-#define LCNPHY_TX_PWR_CTRL_GAIN_OFFSET 192
+#define LCNPHY_TX_PWR_CTRL_RATE_OFFSET 832
+#define LCNPHY_TX_PWR_CTRL_MAC_OFFSET 128
+#define LCNPHY_TX_PWR_CTRL_GAIN_OFFSET 192
#define LCNPHY_TX_PWR_CTRL_IQ_OFFSET 320
#define LCNPHY_TX_PWR_CTRL_LO_OFFSET 448
#define LCNPHY_TX_PWR_CTRL_PWR_OFFSET 576
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/phyreg_n.h b/drivers/staging/brcm80211/brcmsmac/phy/phyreg_n.h
index 211bc3a842af..a97c3a799479 100644
--- a/drivers/staging/brcm80211/brcmsmac/phy/phyreg_n.h
+++ b/drivers/staging/brcm80211/brcmsmac/phy/phyreg_n.h
@@ -123,13 +123,13 @@
#define NPHY_REV3_RFSEQ_CMD_CLR_RXRX_BIAS 0xf
#define NPHY_REV3_RFSEQ_CMD_END 0x1f
-#define NPHY_RSSI_SEL_W1 0x0
-#define NPHY_RSSI_SEL_W2 0x1
-#define NPHY_RSSI_SEL_NB 0x2
-#define NPHY_RSSI_SEL_IQ 0x3
-#define NPHY_RSSI_SEL_TSSI_2G 0x4
-#define NPHY_RSSI_SEL_TSSI_5G 0x5
-#define NPHY_RSSI_SEL_TBD 0x6
+#define NPHY_RSSI_SEL_W1 0x0
+#define NPHY_RSSI_SEL_W2 0x1
+#define NPHY_RSSI_SEL_NB 0x2
+#define NPHY_RSSI_SEL_IQ 0x3
+#define NPHY_RSSI_SEL_TSSI_2G 0x4
+#define NPHY_RSSI_SEL_TSSI_5G 0x5
+#define NPHY_RSSI_SEL_TBD 0x6
#define NPHY_RAIL_I 0x0
#define NPHY_RAIL_Q 0x1
diff --git a/drivers/staging/brcm80211/brcmsmac/rate.h b/drivers/staging/brcm80211/brcmsmac/rate.h
index 8b4de8bec3c9..268125fdd0e2 100644
--- a/drivers/staging/brcm80211/brcmsmac/rate.h
+++ b/drivers/staging/brcm80211/brcmsmac/rate.h
@@ -84,7 +84,7 @@ extern const mcs_info_t mcs_table[];
#define WLC_HTPHY 127 /* HT PHY Membership */
#define RSPEC_ACTIVE(rspec) (rspec & (RSPEC_RATE_MASK | RSPEC_MIMORATE))
-#define RSPEC2RATE(rspec) ((rspec & RSPEC_MIMORATE) ? \
+#define RSPEC2RATE(rspec) ((rspec & RSPEC_MIMORATE) ? \
MCS_RATE((rspec & RSPEC_RATE_MASK), RSPEC_IS40MHZ(rspec), RSPEC_ISSGI(rspec)) : \
(rspec & RSPEC_RATE_MASK))
/* return rate in unit of 500Kbps -- for internal use in wlc_rate_sel.c */
@@ -111,8 +111,8 @@ extern const mcs_info_t mcs_table[];
#define PLCP3_STC_SHIFT 4
/* Rate info table; takes a legacy rate or ratespec_t */
-#define IS_MCS(r) (r & RSPEC_MIMORATE)
-#define IS_OFDM(r) (!IS_MCS(r) && (rate_info[(r) & RSPEC_RATE_MASK] & WLC_RATE_FLAG))
+#define IS_MCS(r) (r & RSPEC_MIMORATE)
+#define IS_OFDM(r) (!IS_MCS(r) && (rate_info[(r) & RSPEC_RATE_MASK] & WLC_RATE_FLAG))
#define IS_CCK(r) (!IS_MCS(r) && ( \
((r) & WLC_RATE_MASK) == WLC_RATE_1M || \
((r) & WLC_RATE_MASK) == WLC_RATE_2M || \
diff --git a/drivers/staging/brcm80211/brcmsmac/scb.h b/drivers/staging/brcm80211/brcmsmac/scb.h
index 62e005ede1c5..e814e5e10c0d 100644
--- a/drivers/staging/brcm80211/brcmsmac/scb.h
+++ b/drivers/staging/brcm80211/brcmsmac/scb.h
@@ -50,7 +50,7 @@ struct scb_ampdu {
scb_ampdu_tid_ini_t ini[AMPDU_MAX_SCB_TID]; /* initiator info - per tid (NUMPRIO) */
};
-#define SCB_MAGIC 0xbeefcafe
+#define SCB_MAGIC 0xbeefcafe
/* station control block - one per remote MAC address */
struct scb {
diff --git a/drivers/staging/brcm80211/brcmsmac/types.h b/drivers/staging/brcm80211/brcmsmac/types.h
index af1514eb6b2d..b1370be7dece 100644
--- a/drivers/staging/brcm80211/brcmsmac/types.h
+++ b/drivers/staging/brcm80211/brcmsmac/types.h
@@ -96,7 +96,7 @@
* 2 4330a0
*/
-#define SSLPNCONF 0x0000000f /* Supported sslpnphy revs:
+#define SSLPNCONF 0x0000000f /* Supported sslpnphy revs:
* 0 4329a0/k0
* 1 4329b0/4329C0
* 2 4319a0