diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2011-11-08 18:38:59 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:49:55 -0800 |
| commit | 20f0354ffb895c9eeb2393e22fce70902397e52b (patch) | |
| tree | 1c5ddca585026016075f8d66e72228c4ab79d799 /drivers/tty/serial | |
| parent | a2480080a52bf8d4fe5dc68530443bf53eccc4eb (diff) | |
Serial: tegra: Allow 2% error in selecting clock source for baudrate.
Allowing 2% error in calculated baudrate when finding the best clock
source uart controller.
bug 896117
Change-Id: I08260a4d9c24d8303a1e176e8a871c90dfbe0825
Reviewed-on: http://git-master/r/62980
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rfc09a6aa7b2abf126ded97c87e8b46138cf30d18
Diffstat (limited to 'drivers/tty/serial')
| -rw-r--r-- | drivers/tty/serial/tegra_hsuart.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/tty/serial/tegra_hsuart.c b/drivers/tty/serial/tegra_hsuart.c index eb2e208f8760..277361698d08 100644 --- a/drivers/tty/serial/tegra_hsuart.c +++ b/drivers/tty/serial/tegra_hsuart.c @@ -1070,14 +1070,20 @@ static unsigned long find_best_clock_source(struct tegra_uart_port *t, unsigned long fin_rate = rate; int final_index = -1; int count; + unsigned long error_2perc; pdata = u->dev->platform_data; if (!pdata || !pdata->parent_clk_count) return fin_rate; + error_2perc = (rate / 50); + for (count = 0; count < pdata->parent_clk_count; ++count) { parent_rate = pdata->parent_clk_list[count].fixed_clk_rate; + if (parent_rate < rate) + continue; + #ifndef CONFIG_ARCH_TEGRA_2x_SOC divider = clk_div71_get_divider(parent_rate, rate); @@ -1091,8 +1097,12 @@ static unsigned long find_best_clock_source(struct tegra_uart_port *t, final_index = count; fin_err = err_rate; fin_rate = new_rate; + if (fin_err < error_2perc) + break; } } + if (fin_err < error_2perc) + break; } #endif /* Get the divisor by uart controller dll/dlm */ @@ -1107,8 +1117,12 @@ static unsigned long find_best_clock_source(struct tegra_uart_port *t, final_index = count; fin_err = err_rate; fin_rate = parent_rate; + if (fin_err < error_2perc) + break; } } + if (fin_err < error_2perc) + break; } } |