diff options
| author | Pradeep Goudagunta <pgoudagunta@nvidia.com> | 2011-08-10 17:39:51 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:48:10 -0800 |
| commit | e7f18ba15667a2ee3cedbc39891095557f53c08d (patch) | |
| tree | efa32b659104859a63e37029de20cbbe882de493 /drivers/tty | |
| parent | 94ce60fa064d84038535da58070cd33c76b4fec0 (diff) | |
serial: tegra: Check tx fifo status before writing
TX fifo should be checked before writing into it, if it is full then stop
writing.
Bug 847599
Original-Change-Id: I12c654e3709fe42ec3494d90ac4fa256a790e9b5
Reviewed-on: http://git-master/r/46351
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R6e82e11cfa4924b4ceb06fb753905e328f6a4dcd
Diffstat (limited to 'drivers/tty')
| -rw-r--r-- | drivers/tty/serial/tegra_hsuart.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/tty/serial/tegra_hsuart.c b/drivers/tty/serial/tegra_hsuart.c index ba855c51a57f..9d6fd3ff4209 100644 --- a/drivers/tty/serial/tegra_hsuart.c +++ b/drivers/tty/serial/tegra_hsuart.c @@ -54,6 +54,7 @@ #define UART_RX_DMA_BUFFER_SIZE (2048*4) #define UART_LSR_FIFOE 0x80 +#define UART_LSR_TXFIFO_FULL 0x100 #define UART_IER_EORD 0x20 #define UART_MCR_RTS_EN 0x40 #define UART_MCR_CTS_EN 0x20 @@ -134,6 +135,14 @@ static inline u8 uart_readb(struct tegra_uart_port *t, unsigned long reg) return val; } +static inline u32 uart_readl(struct tegra_uart_port *t, unsigned long reg) +{ + u32 val = readl(t->uport.membase + (reg << t->uport.regshift)); + dev_vdbg(t->uport.dev, "%s: %p %03lx = %02x\n", __func__, + t->uport.membase, reg << t->uport.regshift, val); + return val; +} + static inline void uart_writeb(struct tegra_uart_port *t, u8 val, unsigned long reg) { @@ -161,9 +170,17 @@ static void fill_tx_fifo(struct tegra_uart_port *t, int max_bytes) { int i; struct circ_buf *xmit = &t->uport.state->xmit; +#ifndef CONFIG_ARCH_TEGRA_2x_SOC + unsigned long lsr; +#endif for (i = 0; i < max_bytes; i++) { BUG_ON(uart_circ_empty(xmit)); +#ifndef CONFIG_ARCH_TEGRA_2x_SOC + lsr = uart_readl(t, UART_LSR); + if ((lsr & UART_LSR_TXFIFO_FULL)) + break; +#endif uart_writeb(t, xmit->buf[xmit->tail], UART_TX); xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); t->uport.icount.tx++; |