diff options
| author | JC Kuo <jckuo@nvidia.com> | 2013-01-30 15:12:10 +0800 |
|---|---|---|
| committer | Riham Haidar <rhaidar@nvidia.com> | 2013-02-01 18:37:25 -0800 |
| commit | 55dd8c7bf186f1e15278522e551901b2c506fe5c (patch) | |
| tree | ff97a4237ae440e6a5e39e98568b5bc2403e52c8 /drivers/usb | |
| parent | b70c83d0c933419f8e7f09f3139a275702c6b0d3 (diff) | |
xhci: tegra: WAR for utmi bias pd bit
This is a workaround for utmi bias pad power down bit setting.
BIAS_PD bit of UTMIP_BIAS_CFG0 register has to be cleared if xusb
owns any of the utmi ports.
Bug 1167876
Change-Id: I0cfae12c516ec7bb10b3e13a8dc7c526c2294551
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Reviewed-on: http://git-master/r/196024
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Henry Lin <henryl@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/usb')
| -rw-r--r-- | drivers/usb/host/xhci-tegra.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c index 7bf3cef7c8ab..637a1bc77409 100644 --- a/drivers/usb/host/xhci-tegra.c +++ b/drivers/usb/host/xhci-tegra.c @@ -1550,6 +1550,33 @@ tegra_xhci_padctl_enable_usb_vbus(struct tegra_xhci_hcd *tegra) writel(reg, tegra->padctl_base + USB2_OC_MAP_0); } +static void utmip_biaspd_workaround(struct tegra_xhci_hcd *tegra) +{ +#define TEGRA_USB_BASE 0x7D000000 +#define UTMIP_BIAS_CFG0 0x80c +#define UTMIP_BIASPD (1 << 10) + + void __iomem *pad_base = IO_ADDRESS(TEGRA_USB_BASE); + struct platform_device *pdev = tegra->pdev; + u32 reg; + + /* Workaround: Clear BIASPD bit from UTMIP_BIAS_CFG0 register + * + * REASON: USB 2.0 phy driver will power down utmip bias circuit when + * neither UTMI0 nor UTMI1 is using by USB 2.0 drivers. However, USB 3.0 + * controller might still need UTMI bias pad to be working. + * + * TODO: This is shared bit between USB2 and USB3 so check with USB 2.0 + * team and do it in a common place */ + reg = ioread32(pad_base + UTMIP_BIAS_CFG0); + if (reg & UTMIP_BIASPD) { + dev_info(&pdev->dev, "%s: (WAR) powering up UTMI BIAS pad\n", + __func__); + reg &= ~UTMIP_BIASPD; + iowrite32(reg, pad_base + UTMIP_BIAS_CFG0); + } +} + /* This function assigns the USB ports to the controllers, * then programs the port capabilities and pad parameters * of ports assigned to XUSB after booted to OS. @@ -1656,6 +1683,8 @@ tegra_xhci_padctl_portmap_and_caps(struct tegra_xhci_hcd *tegra) reg = readl(tegra->padctl_base + HSIC_PAD1_CTL_0_0); reg &= xusb_padctl->hsic_pad0_ctl1; writel(reg, tegra->padctl_base + HSIC_PAD1_CTL_0_0); + + utmip_biaspd_workaround(tegra); } /* This function read XUSB registers and stores in device context */ |