diff options
| author | Liu Ying <Ying.Liu@freescale.com> | 2015-09-11 14:58:02 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:23:25 +0800 |
| commit | 3a7e701188ec761130f1b679f45e336ea9046794 (patch) | |
| tree | 3d0fbcd787c72132dd853c185ad7e92d1aa4c4af /drivers/video/fbdev/mxc/mxc_ipuv3_fb.c | |
| parent | ac25797c3a52cea6a8148835a879854798d6a994 (diff) | |
MLK-11316-1 mxc IPUv3: PRE: Export a function to set PRE_CTRL register
In order to workaround the PRE SoC bug recorded by errata ERR009624, the
software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.
This patch exports a function to set the PRE_CTRL register so that it could be
used by the software when the PRE automatic writing doesn't happen for sure.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit e64bbcd9243a17f9eba9cb3abb6f2c1939eae110)
Diffstat (limited to 'drivers/video/fbdev/mxc/mxc_ipuv3_fb.c')
| -rw-r--r-- | drivers/video/fbdev/mxc/mxc_ipuv3_fb.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/video/fbdev/mxc/mxc_ipuv3_fb.c b/drivers/video/fbdev/mxc/mxc_ipuv3_fb.c index d45b414126a6..355b4778e1d8 100644 --- a/drivers/video/fbdev/mxc/mxc_ipuv3_fb.c +++ b/drivers/video/fbdev/mxc/mxc_ipuv3_fb.c @@ -704,6 +704,10 @@ static int _setup_disp_channel2(struct fb_info *fbi) ipu_base = pre.store_addr; mxc_fbi->store_addr = ipu_base; + retval = ipu_pre_set_ctrl(mxc_fbi->pre_num, &pre); + if (retval < 0) + return retval; + retval = ipu_pre_sdw_update(mxc_fbi->pre_num); if (retval < 0) { dev_err(fbi->device, |