ENGR00126873 mx50: fix esdhc clock setting issue

There's a little issue in the original esdhc clock setting
that we used the wrong predefined microes for clock setting.

That will cause such an issue that if we want to select PPL2
as the clock source of esdhc1, but actually we get a PLL1 as
the clock source of esdhc2.
That will cause the final clock frequency of esdhc1 to be
a double of the expected frequency,(PLL1 800Mhz, PLL2 400Mhz)
and then some cards may be unable to work on sd1.

Signed-off-by: Aisheng.Dong <b29396@freescale.com>

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