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authorSanjay Singh Rawat <srawat@nvidia.com>2011-09-22 20:00:47 +0530
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:49:07 -0800
commit7d85aacb6596f07bb7c60eaf0e47206293bc3601 (patch)
tree8e966ed1a75145dac35288a98d041c75e60688af /drivers/video/tegra/dc/hdmi.c
parent88d04d8409a721b9fda2af332b43059bcade79f7 (diff)
video: tegra: Do correct pixel clock validation of HDMI sink
Resolution wise the pixel clock of the peripheral and supported resolution mode if found different was checked whether in permissible range or not. PICOS2KHZ macro argument is taken as denominator in division, in multiple argument case care should be taken. Bug 878912 Similar Bug 872389 Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-on: http://git-master/r/54050 (cherry picked from commit 927b647e437133a9d28336ed697447e41b09b9c7) Change-Id: I6056cbb01d6eea9c1f01168e55d78356ed00108a Reviewed-on: http://git-master/r/55142 Tested-by: Sanjay Singh Rawat <srawat@nvidia.com> Reviewed-by: Donghan Ryu <dryu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: Rd019e00ceac2bd3280dd3a847b49a4601dabc82a
Diffstat (limited to 'drivers/video/tegra/dc/hdmi.c')
-rw-r--r--drivers/video/tegra/dc/hdmi.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/video/tegra/dc/hdmi.c b/drivers/video/tegra/dc/hdmi.c
index 506d59a24bf5..67a7d673181b 100644
--- a/drivers/video/tegra/dc/hdmi.c
+++ b/drivers/video/tegra/dc/hdmi.c
@@ -666,12 +666,18 @@ static bool tegra_dc_hdmi_mode_equal(const struct fb_videomode *mode1,
int clock_per_frame = tegra_dc_calc_clock_per_frame(mode1);
/* allows up to 1Hz of pixclock difference */
- return mode1->xres == mode2->xres &&
- mode1->yres == mode2->yres &&
- (mode1->pixclock == mode2->pixclock ||
- (abs(PICOS2KHZ(mode1->pixclock - mode2->pixclock)) *
- 1000 / clock_per_frame <= 1)) &&
- mode1->vmode == mode2->vmode;
+ if (mode1->pixclock != mode2->pixclock) {
+ return (mode1->xres == mode2->xres &&
+ mode1->yres == mode2->yres &&
+ mode1->vmode == mode2->vmode &&
+ (abs(PICOS2KHZ(mode1->pixclock) -
+ PICOS2KHZ(mode2->pixclock)) *
+ 1000 / clock_per_frame <= 1));
+ } else {
+ return (mode1->xres == mode2->xres &&
+ mode1->yres == mode2->yres &&
+ mode1->vmode == mode2->vmode);
+ }
}
static bool tegra_dc_hdmi_valid_pixclock(const struct tegra_dc *dc,